* [PATCH v6 01/18] ARM: tegra: Compile sleep-tegra20/30.S unconditionally
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
@ 2019-10-15 16:59 ` Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 02/18] ARM: tegra: Add tegra_pm_park_secondary_cpu() Dmitry Osipenko
` (17 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 16:59 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The sleep-tegra*.S provides functionality required for suspend/resume
and CPU hotplugging. The new unified CPUIDLE driver will support multiple
hardware generations starting from Terga20 and ending with Tegra124, the
driver will utilize functions that are provided by the assembly and thus
it is cleaner to compile that code without any build-dependencies in order
to avoid churning with #ifdef's.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/Makefile | 6 ++----
arch/arm/mach-tegra/sleep.h | 2 --
2 files changed, 2 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 6c1dff2eccc2..965862608ff6 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -8,13 +8,13 @@ obj-y += reset.o
obj-y += reset-handler.o
obj-y += sleep.o
obj-y += tegra.o
+obj-y += sleep-tegra20.o
+obj-y += sleep-tegra30.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
endif
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
@@ -22,12 +22,10 @@ endif
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
endif
-obj-$(CONFIG_ARCH_TEGRA_124_SOC) += sleep-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 78ef32a907c8..63e2205cbc82 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -120,10 +120,8 @@ void tegra_resume(void);
int tegra_sleep_cpu_finish(unsigned long);
void tegra_disable_clean_inv_dcache(u32 flag);
-#ifdef CONFIG_HOTPLUG_CPU
void tegra20_hotplug_shutdown(void);
void tegra30_hotplug_shutdown(void);
-#endif
void tegra20_cpu_shutdown(int cpu);
int tegra20_cpu_is_resettable_soon(void);
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 02/18] ARM: tegra: Add tegra_pm_park_secondary_cpu()
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 01/18] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Dmitry Osipenko
@ 2019-10-15 16:59 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 03/18] ARM: tegra: Remove pen-locking from cpuidle-tegra20 Dmitry Osipenko
` (16 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 16:59 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
This function resembles tegra_cpu_die() of the hotplug code, but
this variant is more suitable to be used for CPU PM because it's made
specifically to be used by cpu_suspend(). In short this function puts
secondary CPU offline, it will be used by the new CPUIDLE driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/pm.c | 14 ++++++++++++++
arch/arm/mach-tegra/pm.h | 5 +++++
2 files changed, 19 insertions(+)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 3cab81b82866..f5ff3dd1dd81 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -436,4 +436,18 @@ void __init tegra_init_suspend(void)
suspend_set_ops(&tegra_suspend_ops);
}
+
+int tegra_pm_park_secondary_cpu(unsigned long cpu)
+{
+ if (cpu > 0) {
+ tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS);
+
+ if (tegra_get_chip_id() == TEGRA20)
+ tegra20_hotplug_shutdown();
+ else
+ tegra30_hotplug_shutdown();
+ }
+
+ return -EINVAL;
+}
#endif
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 569151b3edc0..9a790f00237f 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -31,8 +31,13 @@ extern void (*tegra_tear_down_cpu)(void);
#ifdef CONFIG_PM_SLEEP
void tegra_init_suspend(void);
+int tegra_pm_park_secondary_cpu(unsigned long cpu);
#else
static inline void tegra_init_suspend(void) {}
+static inline int tegra_pm_park_secondary_cpu(unsigned long cpu)
+{
+ return -ENOTSUPP;
+}
#endif
#endif /* _MACH_TEGRA_PM_H_ */
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 03/18] ARM: tegra: Remove pen-locking from cpuidle-tegra20
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 01/18] ARM: tegra: Compile sleep-tegra20/30.S unconditionally Dmitry Osipenko
2019-10-15 16:59 ` [PATCH v6 02/18] ARM: tegra: Add tegra_pm_park_secondary_cpu() Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 04/18] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Dmitry Osipenko
` (15 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Pen-locking is meant to block CPU0 if CPU1 wakes up during of entering
into LP2 because of some interrupt firing up, preventing unnecessary LP2
enter that will be resumed immediately. Apparently this case doesn't
happen often in practice, I checked how often it takes place and found
that after ~20 hours of browsing web, managing email, watching videos and
idling (15+ hours) there is only a dozen of early LP2 entering abortions
and they all happened while device was idling. Thus let's remove the
pen-locking and make LP2 entering uninterruptible, simplifying code quite
a lot. This will also become very handy for the upcoming unified cpuidle
driver, allowing to have a common LP2 code-path across of different
hardware generations.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 46 +------
arch/arm/mach-tegra/pm.c | 7 --
arch/arm/mach-tegra/pm.h | 1 -
arch/arm/mach-tegra/reset-handler.S | 11 --
arch/arm/mach-tegra/reset.h | 9 +-
arch/arm/mach-tegra/sleep-tegra20.S | 170 --------------------------
arch/arm/mach-tegra/sleep.h | 12 --
7 files changed, 5 insertions(+), 251 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 2447427cb4a8..4da5d72ae030 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -15,6 +15,7 @@
#include <linux/cpuidle.h>
#include <linux/cpu_pm.h>
#include <linux/kernel.h>
+#include <linux/ktime.h>
#include <linux/module.h>
#include <soc/tegra/flowctrl.h>
@@ -65,28 +66,8 @@ static struct cpuidle_driver tegra_idle_driver = {
#ifdef CONFIG_PM_SLEEP
#ifdef CONFIG_SMP
-static int tegra20_reset_sleeping_cpu_1(void)
-{
- int ret = 0;
-
- tegra_pen_lock();
-
- if (readb(tegra20_cpu1_resettable_status) == CPU_RESETTABLE)
- tegra20_cpu_shutdown(1);
- else
- ret = -EINVAL;
-
- tegra_pen_unlock();
-
- return ret;
-}
-
static void tegra20_wake_cpu1_from_reset(void)
{
- tegra_pen_lock();
-
- tegra20_cpu_clear_resettable();
-
/* enable cpu clock on cpu */
tegra_enable_cpu_clock(1);
@@ -95,39 +76,20 @@ static void tegra20_wake_cpu1_from_reset(void)
/* unhalt the cpu */
flowctrl_write_cpu_halt(1, 0);
-
- tegra_pen_unlock();
-}
-
-static int tegra20_reset_cpu_1(void)
-{
- if (!cpu_online(1) || !tegra20_reset_sleeping_cpu_1())
- return 0;
-
- tegra20_wake_cpu1_from_reset();
- return -EBUSY;
}
#else
static inline void tegra20_wake_cpu1_from_reset(void)
{
}
-
-static inline int tegra20_reset_cpu_1(void)
-{
- return 0;
-}
#endif
static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
- while (tegra20_cpu_is_resettable_soon())
+ while (!tegra_cpu_rail_off_ready())
cpu_relax();
- if (tegra20_reset_cpu_1() || !tegra_cpu_rail_off_ready())
- return false;
-
tegra_idle_lp2_last();
if (cpu_online(1))
@@ -141,9 +103,7 @@ static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
- cpu_suspend(0, tegra20_sleep_cpu_secondary_finish);
-
- tegra20_cpu_clear_resettable();
+ cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu);
return true;
}
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index f5ff3dd1dd81..1ff499068bb1 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -137,18 +137,11 @@ bool tegra_set_cpu_in_lp2(void)
if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
last_cpu = true;
- else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1)
- tegra20_cpu_set_resettable_soon();
spin_unlock(&tegra_lp2_lock);
return last_cpu;
}
-int tegra_cpu_do_idle(void)
-{
- return cpu_do_idle();
-}
-
static int tegra_sleep_cpu(unsigned long v2p)
{
/*
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 9a790f00237f..b9cc12222bb1 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -25,7 +25,6 @@ void tegra30_sleep_core_init(void);
void tegra_clear_cpu_in_lp2(void);
bool tegra_set_cpu_in_lp2(void);
-int tegra_cpu_do_idle(void);
void tegra_idle_lp2_last(void);
extern void (*tegra_tear_down_cpu)(void);
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 67b763fea005..df44828a34d3 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -183,17 +183,6 @@ after_errata:
bleq __die @ CPU not present (to OS)
#endif
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
- /* Are we on Tegra20? */
- cmp r6, #TEGRA20
- bne 1f
- /* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
- mov r0, #CPU_NOT_RESETTABLE
- cmp r10, #0
- strbne r0, [r12, #RESET_DATA(RESETTABLE_STATUS)]
-1:
-#endif
-
/* Waking up from LP1? */
ldr r8, [r12, #RESET_DATA(MASK_LP1)]
tst r8, r11 @ if in_lp1
diff --git a/arch/arm/mach-tegra/reset.h b/arch/arm/mach-tegra/reset.h
index a4cfc08159f6..51265592cb1a 100644
--- a/arch/arm/mach-tegra/reset.h
+++ b/arch/arm/mach-tegra/reset.h
@@ -16,9 +16,8 @@
#define TEGRA_RESET_STARTUP_SECONDARY 3
#define TEGRA_RESET_STARTUP_LP2 4
#define TEGRA_RESET_STARTUP_LP1 5
-#define TEGRA_RESET_RESETTABLE_STATUS 6
-#define TEGRA_RESET_TF_PRESENT 7
-#define TEGRA_RESET_DATA_SIZE 8
+#define TEGRA_RESET_TF_PRESENT 6
+#define TEGRA_RESET_DATA_SIZE 7
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
@@ -42,10 +41,6 @@ void __tegra_cpu_reset_handler_end(void);
(IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_LP2] - \
(u32)__tegra_cpu_reset_handler_start)))
-#define tegra20_cpu1_resettable_status \
- (IO_ADDRESS(TEGRA_IRAM_BASE + TEGRA_IRAM_RESET_HANDLER_OFFSET + \
- ((u32)&__tegra_cpu_reset_handler_data[TEGRA_RESET_RESETTABLE_STATUS] - \
- (u32)__tegra_cpu_reset_handler_start)))
#endif
#define tegra_cpu_reset_handler_offset \
diff --git a/arch/arm/mach-tegra/sleep-tegra20.S b/arch/arm/mach-tegra/sleep-tegra20.S
index 9a89f30d53ca..0e00ba8cf646 100644
--- a/arch/arm/mach-tegra/sleep-tegra20.S
+++ b/arch/arm/mach-tegra/sleep-tegra20.S
@@ -43,9 +43,6 @@
#define APB_MISC_XM2CFGCPADCTRL2 0x8e4
#define APB_MISC_XM2CFGDPADCTRL2 0x8e8
-#define __tegra20_cpu1_resettable_status_offset \
- (__tegra_cpu_reset_handler_data_offset + RESET_DATA(RESETTABLE_STATUS))
-
.macro pll_enable, rd, r_car_base, pll_base
ldr \rd, [\r_car_base, #\pll_base]
tst \rd, #(1 << 30)
@@ -90,10 +87,6 @@ ENDPROC(tegra20_hotplug_shutdown)
ENTRY(tegra20_cpu_shutdown)
cmp r0, #0
reteq lr @ must not be called for CPU 0
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_RESETTABLE
- strb r12, [r1, r2]
cpu_to_halt_reg r1, r0
ldr r3, =TEGRA_FLOW_CTRL_VIRT
@@ -116,107 +109,6 @@ ENDPROC(tegra20_cpu_shutdown)
#endif
#ifdef CONFIG_PM_SLEEP
-/*
- * tegra_pen_lock
- *
- * spinlock implementation with no atomic test-and-set and no coherence
- * using Peterson's algorithm on strongly-ordered registers
- * used to synchronize a cpu waking up from wfi with entering lp2 on idle
- *
- * The reference link of Peterson's algorithm:
- * http://en.wikipedia.org/wiki/Peterson's_algorithm
- *
- * SCRATCH37 = r1 = !turn (inverted from Peterson's algorithm)
- * on cpu 0:
- * r2 = flag[0] (in SCRATCH38)
- * r3 = flag[1] (in SCRATCH39)
- * on cpu1:
- * r2 = flag[1] (in SCRATCH39)
- * r3 = flag[0] (in SCRATCH38)
- *
- * must be called with MMU on
- * corrupts r0-r3, r12
- */
-ENTRY(tegra_pen_lock)
- mov32 r3, TEGRA_PMC_VIRT
- cpu_id r0
- add r1, r3, #PMC_SCRATCH37
- cmp r0, #0
- addeq r2, r3, #PMC_SCRATCH38
- addeq r3, r3, #PMC_SCRATCH39
- addne r2, r3, #PMC_SCRATCH39
- addne r3, r3, #PMC_SCRATCH38
-
- mov r12, #1
- str r12, [r2] @ flag[cpu] = 1
- dsb
- str r12, [r1] @ !turn = cpu
-1: dsb
- ldr r12, [r3]
- cmp r12, #1 @ flag[!cpu] == 1?
- ldreq r12, [r1]
- cmpeq r12, r0 @ !turn == cpu?
- beq 1b @ while !turn == cpu && flag[!cpu] == 1
-
- ret lr @ locked
-ENDPROC(tegra_pen_lock)
-
-ENTRY(tegra_pen_unlock)
- dsb
- mov32 r3, TEGRA_PMC_VIRT
- cpu_id r0
- cmp r0, #0
- addeq r2, r3, #PMC_SCRATCH38
- addne r2, r3, #PMC_SCRATCH39
- mov r12, #0
- str r12, [r2]
- ret lr
-ENDPROC(tegra_pen_unlock)
-
-/*
- * tegra20_cpu_clear_resettable(void)
- *
- * Called to clear the "resettable soon" flag in IRAM variable when
- * it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_clear_resettable)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_NOT_RESETTABLE
- strb r12, [r1, r2]
- ret lr
-ENDPROC(tegra20_cpu_clear_resettable)
-
-/*
- * tegra20_cpu_set_resettable_soon(void)
- *
- * Called to set the "resettable soon" flag in IRAM variable when
- * it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_set_resettable_soon)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- mov r12, #CPU_RESETTABLE_SOON
- strb r12, [r1, r2]
- ret lr
-ENDPROC(tegra20_cpu_set_resettable_soon)
-
-/*
- * tegra20_cpu_is_resettable_soon(void)
- *
- * Returns true if the "resettable soon" flag in IRAM variable has been
- * set because it is expected that the secondary CPU will be idle soon.
- */
-ENTRY(tegra20_cpu_is_resettable_soon)
- mov32 r1, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r2, =__tegra20_cpu1_resettable_status_offset
- ldrb r12, [r1, r2]
- cmp r12, #CPU_RESETTABLE_SOON
- moveq r0, #1
- movne r0, #0
- ret lr
-ENDPROC(tegra20_cpu_is_resettable_soon)
-
/*
* tegra20_sleep_core_finish(unsigned long v2p)
*
@@ -242,68 +134,6 @@ ENTRY(tegra20_sleep_core_finish)
ret r3
ENDPROC(tegra20_sleep_core_finish)
-/*
- * tegra20_sleep_cpu_secondary_finish(unsigned long v2p)
- *
- * Enters WFI on secondary CPU by exiting coherency.
- */
-ENTRY(tegra20_sleep_cpu_secondary_finish)
- stmfd sp!, {r4-r11, lr}
-
- mrc p15, 0, r11, c1, c0, 1 @ save actlr before exiting coherency
-
- /* Flush and disable the L1 data cache */
- mov r0, #TEGRA_FLUSH_CACHE_LOUIS
- bl tegra_disable_clean_inv_dcache
-
- mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
- mov r3, #CPU_RESETTABLE
- strb r3, [r0, r4]
-
- bl tegra_cpu_do_idle
-
- /*
- * cpu may be reset while in wfi, which will return through
- * tegra_resume to cpu_resume
- * or interrupt may wake wfi, which will return here
- * cpu state is unchanged - MMU is on, cache is on, coherency
- * is off, and the data cache is off
- *
- * r11 contains the original actlr
- */
-
- bl tegra_pen_lock
-
- mov32 r0, TEGRA_IRAM_RESET_BASE_VIRT
- ldr r4, =__tegra20_cpu1_resettable_status_offset
- mov r3, #CPU_NOT_RESETTABLE
- strb r3, [r0, r4]
-
- bl tegra_pen_unlock
-
- /* Re-enable the data cache */
- mrc p15, 0, r10, c1, c0, 0
- orr r10, r10, #CR_C
- mcr p15, 0, r10, c1, c0, 0
- isb
-
- mcr p15, 0, r11, c1, c0, 1 @ reenable coherency
-
- /* Invalidate the TLBs & BTAC */
- mov r1, #0
- mcr p15, 0, r1, c8, c3, 0 @ invalidate shared TLBs
- mcr p15, 0, r1, c7, c1, 6 @ invalidate shared BTAC
- dsb
- isb
-
- /* the cpu was running with coherency disabled,
- * caches may be out of date */
- bl v7_flush_kern_cache_louis
-
- ldmfd sp!, {r4 - r11, pc}
-ENDPROC(tegra20_sleep_cpu_secondary_finish)
-
/*
* tegra20_tear_down_cpu
*
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 63e2205cbc82..4978def9db46 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -114,8 +114,6 @@
.endm
#else
-void tegra_pen_lock(void);
-void tegra_pen_unlock(void);
void tegra_resume(void);
int tegra_sleep_cpu_finish(unsigned long);
void tegra_disable_clean_inv_dcache(u32 flag);
@@ -123,16 +121,6 @@ void tegra_disable_clean_inv_dcache(u32 flag);
void tegra20_hotplug_shutdown(void);
void tegra30_hotplug_shutdown(void);
-void tegra20_cpu_shutdown(int cpu);
-int tegra20_cpu_is_resettable_soon(void);
-void tegra20_cpu_clear_resettable(void);
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void tegra20_cpu_set_resettable_soon(void);
-#else
-static inline void tegra20_cpu_set_resettable_soon(void) {}
-#endif
-
-int tegra20_sleep_cpu_secondary_finish(unsigned long);
void tegra20_tear_down_cpu(void);
int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 04/18] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (2 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 03/18] ARM: tegra: Remove pen-locking from cpuidle-tegra20 Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 05/18] ARM: tegra: Propagate error from tegra_idle_lp2_last() Dmitry Osipenko
` (14 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The Tegra30 CPUIDLE driver has intention to check whether primary CPU was
the last CPU that entered LP2 (CC6) idle-state, but that functionality
never got utilized because driver never supported the CC6 state for the
case where any secondary CPU is online. The new cpuidle driver will
properly support CC6 on Tegra30, including the case where secondary CPUs
are online, and that knowledge about what CPUs entered into CC6 won't be
needed at all because new driver will use different approach by making use
of the coupled idle-state and explicitly parking secondary CPUs before
entering into CC6. Thus this patch is just a minor cleanup change.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra30.c | 14 ++++----------
arch/arm/mach-tegra/pm.c | 8 +-------
arch/arm/mach-tegra/pm.h | 2 +-
3 files changed, 6 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index c6128526877d..a3ce8dabfe18 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -98,22 +98,16 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
int index)
{
bool entered_lp2 = false;
- bool last_cpu;
local_fiq_disable();
- last_cpu = tegra_set_cpu_in_lp2();
+ tegra_set_cpu_in_lp2();
cpu_pm_enter();
- if (dev->cpu == 0) {
- if (last_cpu)
- entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv,
- index);
- else
- cpu_do_idle();
- } else {
+ if (dev->cpu == 0)
+ entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);
+ else
entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
- }
cpu_pm_exit();
tegra_clear_cpu_in_lp2();
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 1ff499068bb1..a72f9a2d3cb7 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -123,11 +123,9 @@ void tegra_clear_cpu_in_lp2(void)
spin_unlock(&tegra_lp2_lock);
}
-bool tegra_set_cpu_in_lp2(void)
+void tegra_set_cpu_in_lp2(void)
{
int phy_cpu_id = cpu_logical_map(smp_processor_id());
- bool last_cpu = false;
- cpumask_t *cpu_lp2_mask = tegra_cpu_lp2_mask;
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
spin_lock(&tegra_lp2_lock);
@@ -135,11 +133,7 @@ bool tegra_set_cpu_in_lp2(void)
BUG_ON((*cpu_in_lp2 & BIT(phy_cpu_id)));
*cpu_in_lp2 |= BIT(phy_cpu_id);
- if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask))
- last_cpu = true;
-
spin_unlock(&tegra_lp2_lock);
- return last_cpu;
}
static int tegra_sleep_cpu(unsigned long v2p)
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index b9cc12222bb1..2c294f6365c0 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -24,7 +24,7 @@ void tegra30_lp1_iram_hook(void);
void tegra30_sleep_core_init(void);
void tegra_clear_cpu_in_lp2(void);
-bool tegra_set_cpu_in_lp2(void);
+void tegra_set_cpu_in_lp2(void);
void tegra_idle_lp2_last(void);
extern void (*tegra_tear_down_cpu)(void);
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 05/18] ARM: tegra: Propagate error from tegra_idle_lp2_last()
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (3 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 04/18] ARM: tegra: Change tegra_set_cpu_in_lp2() type to void Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 06/18] ARM: tegra: Expose PM functions required for new cpuidle driver Dmitry Osipenko
` (13 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Technically cpu_suspend() may fail and it's never good to lose information
about failure. For example things like cpuidle core could correctly sample
idling time in the case of failure.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 6 ++++--
arch/arm/mach-tegra/cpuidle-tegra30.c | 4 +---
arch/arm/mach-tegra/pm.c | 8 ++++++--
arch/arm/mach-tegra/pm.h | 2 +-
4 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 4da5d72ae030..74ba37992259 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -87,15 +87,17 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
+ bool ret;
+
while (!tegra_cpu_rail_off_ready())
cpu_relax();
- tegra_idle_lp2_last();
+ ret = !tegra_idle_lp2_last();
if (cpu_online(1))
tegra20_wake_cpu1_from_reset();
- return true;
+ return ret;
}
#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index a3ce8dabfe18..17cbd118abee 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -68,9 +68,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
return false;
}
- tegra_idle_lp2_last();
-
- return true;
+ return !tegra_idle_lp2_last();
}
#ifdef CONFIG_SMP
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index a72f9a2d3cb7..a094acaca307 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -189,14 +189,16 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
tegra_pmc_enter_suspend_mode(mode);
}
-void tegra_idle_lp2_last(void)
+int tegra_idle_lp2_last(void)
{
+ int err;
+
tegra_pm_set(TEGRA_SUSPEND_LP2);
cpu_cluster_pm_enter();
suspend_cpu_complex();
- cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
+ err = cpu_suspend(PHYS_OFFSET - PAGE_OFFSET, &tegra_sleep_cpu);
/*
* Resume L2 cache if it wasn't re-enabled early during resume,
@@ -208,6 +210,8 @@ void tegra_idle_lp2_last(void)
restore_cpu_complex();
cpu_cluster_pm_exit();
+
+ return err;
}
enum tegra_suspend_mode tegra_pm_validate_suspend_mode(
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 2c294f6365c0..7d72f31dee77 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -25,7 +25,7 @@ void tegra30_sleep_core_init(void);
void tegra_clear_cpu_in_lp2(void);
void tegra_set_cpu_in_lp2(void);
-void tegra_idle_lp2_last(void);
+int tegra_idle_lp2_last(void);
extern void (*tegra_tear_down_cpu)(void);
#ifdef CONFIG_PM_SLEEP
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 06/18] ARM: tegra: Expose PM functions required for new cpuidle driver
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (4 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 05/18] ARM: tegra: Propagate error from tegra_idle_lp2_last() Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 07/18] ARM: tegra: Rename some of the newly exposed PM functions Dmitry Osipenko
` (12 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The upcoming unified CPUIDLE driver will be added to the drivers/cpuidle/
directory and it will require all these exposed Tegra PM-core functions.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra114.c | 3 +-
arch/arm/mach-tegra/cpuidle-tegra20.c | 2 +-
arch/arm/mach-tegra/cpuidle-tegra30.c | 3 +-
arch/arm/mach-tegra/irq.c | 3 +-
arch/arm/mach-tegra/pm.h | 8 -----
arch/arm/mach-tegra/sleep.h | 1 -
arch/arm/mach-tegra/tegra.c | 1 -
.../mach-tegra => include/soc/tegra}/irq.h | 8 +++--
include/soc/tegra/pm.h | 31 +++++++++++++++++++
9 files changed, 43 insertions(+), 17 deletions(-)
rename {arch/arm/mach-tegra => include/soc/tegra}/irq.h (59%)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 5118f777fd66..2d8527837aeb 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -12,13 +12,14 @@
#include <linux/firmware/trusted_foundations.h>
+#include <soc/tegra/pm.h>
+
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include <asm/psci.h>
#include "cpuidle.h"
-#include "pm.h"
#include "sleep.h"
#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 74ba37992259..7de2151a2e0c 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -19,6 +19,7 @@
#include <linux/module.h>
#include <soc/tegra/flowctrl.h>
+#include <soc/tegra/pm.h>
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
@@ -27,7 +28,6 @@
#include "cpuidle.h"
#include "iomap.h"
#include "irq.h"
-#include "pm.h"
#include "reset.h"
#include "sleep.h"
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 17cbd118abee..3e91c29891f7 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -17,12 +17,13 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <soc/tegra/pm.h>
+
#include <asm/cpuidle.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
#include "cpuidle.h"
-#include "pm.h"
#include "sleep.h"
#ifdef CONFIG_PM_SLEEP
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index ace7a390b5fe..4e1ee70b2a3f 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -18,9 +18,10 @@
#include <linux/of.h>
#include <linux/syscore_ops.h>
+#include <soc/tegra/irq.h>
+
#include "board.h"
#include "iomap.h"
-#include "irq.h"
#define SGI_MASK 0xFFFF
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h
index 7d72f31dee77..81525f5f4a44 100644
--- a/arch/arm/mach-tegra/pm.h
+++ b/arch/arm/mach-tegra/pm.h
@@ -23,20 +23,12 @@ void tegra20_sleep_core_init(void);
void tegra30_lp1_iram_hook(void);
void tegra30_sleep_core_init(void);
-void tegra_clear_cpu_in_lp2(void);
-void tegra_set_cpu_in_lp2(void);
-int tegra_idle_lp2_last(void);
extern void (*tegra_tear_down_cpu)(void);
#ifdef CONFIG_PM_SLEEP
void tegra_init_suspend(void);
-int tegra_pm_park_secondary_cpu(unsigned long cpu);
#else
static inline void tegra_init_suspend(void) {}
-static inline int tegra_pm_park_secondary_cpu(unsigned long cpu)
-{
- return -ENOTSUPP;
-}
#endif
#endif /* _MACH_TEGRA_PM_H_ */
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index 4978def9db46..4718a3cb45a1 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -122,7 +122,6 @@ void tegra20_hotplug_shutdown(void);
void tegra30_hotplug_shutdown(void);
void tegra20_tear_down_cpu(void);
-int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);
#endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index e512e606eabd..00aaf495bbf7 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -42,7 +42,6 @@
#include "common.h"
#include "cpuidle.h"
#include "iomap.h"
-#include "irq.h"
#include "pm.h"
#include "reset.h"
#include "sleep.h"
diff --git a/arch/arm/mach-tegra/irq.h b/include/soc/tegra/irq.h
similarity index 59%
rename from arch/arm/mach-tegra/irq.h
rename to include/soc/tegra/irq.h
index 7a94cf121448..8eb11a7109e4 100644
--- a/arch/arm/mach-tegra/irq.h
+++ b/include/soc/tegra/irq.h
@@ -3,9 +3,11 @@
* Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
*/
-#ifndef __TEGRA_IRQ_H
-#define __TEGRA_IRQ_H
+#ifndef __SOC_TEGRA_IRQ_H
+#define __SOC_TEGRA_IRQ_H
+#if defined(CONFIG_ARM)
bool tegra_pending_sgi(void);
-
#endif
+
+#endif /* __SOC_TEGRA_IRQ_H */
diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h
index 951fcd738d55..1974e8405098 100644
--- a/include/soc/tegra/pm.h
+++ b/include/soc/tegra/pm.h
@@ -6,6 +6,8 @@
#ifndef __SOC_TEGRA_PM_H__
#define __SOC_TEGRA_PM_H__
+#include <linux/errno.h>
+
enum tegra_suspend_mode {
TEGRA_SUSPEND_NONE = 0,
TEGRA_SUSPEND_LP2, /* CPU voltage off */
@@ -20,6 +22,12 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
/* low-level resume entry point */
void tegra_resume(void);
+
+int tegra30_sleep_cpu_secondary_finish(unsigned long arg);
+void tegra_clear_cpu_in_lp2(void);
+void tegra_set_cpu_in_lp2(void);
+int tegra_idle_lp2_last(void);
+int tegra_pm_park_secondary_cpu(unsigned long cpu);
#else
static inline enum tegra_suspend_mode
tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
@@ -30,6 +38,29 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode)
static inline void tegra_resume(void)
{
}
+
+static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg)
+{
+ return -ENOTSUPP;
+}
+
+static inline void tegra_clear_cpu_in_lp2(void)
+{
+}
+
+static inline void tegra_set_cpu_in_lp2(void)
+{
+}
+
+static inline int tegra_idle_lp2_last(void)
+{
+ return -ENOTSUPP;
+}
+
+static inline int tegra_pm_park_secondary_cpu(unsigned long cpu)
+{
+ return -ENOTSUPP;
+}
#endif /* CONFIG_PM_SLEEP */
#endif /* __SOC_TEGRA_PM_H__ */
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 07/18] ARM: tegra: Rename some of the newly exposed PM functions
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (5 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 06/18] ARM: tegra: Expose PM functions required for new cpuidle driver Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 08/18] ARM: tegra: Make outer_disable() open-coded Dmitry Osipenko
` (11 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Rename some of the recently exposed PM functions, prefixing them with
"tegra_pm_" in order to make the naming of the PM functions consistent.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra114.c | 6 +++---
arch/arm/mach-tegra/cpuidle-tegra20.c | 6 +++---
arch/arm/mach-tegra/cpuidle-tegra30.c | 8 ++++----
arch/arm/mach-tegra/pm.c | 10 +++++-----
arch/arm/mach-tegra/sleep-tegra30.S | 6 +++---
include/soc/tegra/pm.h | 16 ++++++++--------
6 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index 2d8527837aeb..858c30cc5dc7 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -35,17 +35,17 @@ static int tegra114_idle_power_down(struct cpuidle_device *dev,
{
local_fiq_disable();
- tegra_set_cpu_in_lp2();
+ tegra_pm_set_cpu_in_lp2();
cpu_pm_enter();
call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
/* Do suspend by ourselves if the firmware does not implement it */
if (call_firmware_op(do_idle, 0) == -ENOSYS)
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
+ tegra_pm_clear_cpu_in_lp2();
local_fiq_enable();
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 7de2151a2e0c..77702dd42479 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -92,7 +92,7 @@ static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
while (!tegra_cpu_rail_off_ready())
cpu_relax();
- ret = !tegra_idle_lp2_last();
+ ret = !tegra_pm_enter_lp2();
if (cpu_online(1))
tegra20_wake_cpu1_from_reset();
@@ -137,7 +137,7 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
local_fiq_disable();
- tegra_set_cpu_in_lp2();
+ tegra_pm_set_cpu_in_lp2();
cpu_pm_enter();
if (dev->cpu == 0)
@@ -146,7 +146,7 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
+ tegra_pm_clear_cpu_in_lp2();
local_fiq_enable();
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 3e91c29891f7..a4f0add46a27 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -69,7 +69,7 @@ static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
return false;
}
- return !tegra_idle_lp2_last();
+ return !tegra_pm_enter_lp2();
}
#ifdef CONFIG_SMP
@@ -79,7 +79,7 @@ static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
{
smp_wmb();
- cpu_suspend(0, tegra30_sleep_cpu_secondary_finish);
+ cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
return true;
}
@@ -100,7 +100,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
local_fiq_disable();
- tegra_set_cpu_in_lp2();
+ tegra_pm_set_cpu_in_lp2();
cpu_pm_enter();
if (dev->cpu == 0)
@@ -109,7 +109,7 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
cpu_pm_exit();
- tegra_clear_cpu_in_lp2();
+ tegra_pm_clear_cpu_in_lp2();
local_fiq_enable();
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index a094acaca307..7d9ef26e52a7 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -110,7 +110,7 @@ static void suspend_cpu_complex(void)
flowctrl_cpu_suspend_enter(cpu);
}
-void tegra_clear_cpu_in_lp2(void)
+void tegra_pm_clear_cpu_in_lp2(void)
{
int phy_cpu_id = cpu_logical_map(smp_processor_id());
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -123,7 +123,7 @@ void tegra_clear_cpu_in_lp2(void)
spin_unlock(&tegra_lp2_lock);
}
-void tegra_set_cpu_in_lp2(void)
+void tegra_pm_set_cpu_in_lp2(void)
{
int phy_cpu_id = cpu_logical_map(smp_processor_id());
u32 *cpu_in_lp2 = tegra_cpu_lp2_mask;
@@ -189,7 +189,7 @@ static void tegra_pm_set(enum tegra_suspend_mode mode)
tegra_pmc_enter_suspend_mode(mode);
}
-int tegra_idle_lp2_last(void)
+int tegra_pm_enter_lp2(void)
{
int err;
@@ -356,7 +356,7 @@ static int tegra_suspend_enter(suspend_state_t state)
tegra_suspend_enter_lp1();
break;
case TEGRA_SUSPEND_LP2:
- tegra_set_cpu_in_lp2();
+ tegra_pm_set_cpu_in_lp2();
break;
default:
break;
@@ -377,7 +377,7 @@ static int tegra_suspend_enter(suspend_state_t state)
tegra_suspend_exit_lp1();
break;
case TEGRA_SUSPEND_LP2:
- tegra_clear_cpu_in_lp2();
+ tegra_pm_clear_cpu_in_lp2();
break;
default:
break;
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index b408fa56eb89..386319a3d2d2 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -262,11 +262,11 @@ ENTRY(tegra30_sleep_core_finish)
ENDPROC(tegra30_sleep_core_finish)
/*
- * tegra30_sleep_cpu_secondary_finish(unsigned long v2p)
+ * tegra30_pm_secondary_cpu_suspend(unsigned long unused_arg)
*
* Enters LP2 on secondary CPU by exiting coherency and powergating the CPU.
*/
-ENTRY(tegra30_sleep_cpu_secondary_finish)
+ENTRY(tegra30_pm_secondary_cpu_suspend)
mov r7, lr
/* Flush and disable the L1 data cache */
@@ -278,7 +278,7 @@ ENTRY(tegra30_sleep_cpu_secondary_finish)
bl tegra30_cpu_shutdown
mov r0, #1 @ never return here
ret r7
-ENDPROC(tegra30_sleep_cpu_secondary_finish)
+ENDPROC(tegra30_pm_secondary_cpu_suspend)
/*
* tegra30_tear_down_cpu
diff --git a/include/soc/tegra/pm.h b/include/soc/tegra/pm.h
index 1974e8405098..08477d7bfab9 100644
--- a/include/soc/tegra/pm.h
+++ b/include/soc/tegra/pm.h
@@ -23,10 +23,10 @@ tegra_pm_validate_suspend_mode(enum tegra_suspend_mode mode);
/* low-level resume entry point */
void tegra_resume(void);
-int tegra30_sleep_cpu_secondary_finish(unsigned long arg);
-void tegra_clear_cpu_in_lp2(void);
-void tegra_set_cpu_in_lp2(void);
-int tegra_idle_lp2_last(void);
+int tegra30_pm_secondary_cpu_suspend(unsigned long arg);
+void tegra_pm_clear_cpu_in_lp2(void);
+void tegra_pm_set_cpu_in_lp2(void);
+int tegra_pm_enter_lp2(void);
int tegra_pm_park_secondary_cpu(unsigned long cpu);
#else
static inline enum tegra_suspend_mode
@@ -39,20 +39,20 @@ static inline void tegra_resume(void)
{
}
-static inline int tegra30_sleep_cpu_secondary_finish(unsigned long arg)
+static inline int tegra30_pm_secondary_cpu_suspend(unsigned long arg)
{
return -ENOTSUPP;
}
-static inline void tegra_clear_cpu_in_lp2(void)
+static inline void tegra_pm_clear_cpu_in_lp2(void)
{
}
-static inline void tegra_set_cpu_in_lp2(void)
+static inline void tegra_pm_set_cpu_in_lp2(void)
{
}
-static inline int tegra_idle_lp2_last(void)
+static inline int tegra_pm_enter_lp2(void)
{
return -ENOTSUPP;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 08/18] ARM: tegra: Make outer_disable() open-coded
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (6 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 07/18] ARM: tegra: Rename some of the newly exposed PM functions Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Dmitry Osipenko
` (10 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The outer_disable() of Tegra's suspend code is open-coded now since
that helper produces spurious warning message about secondary CPUs being
online when CPU enters into LP2 from cpuidle. The secondaries are actually
halted by the cpuidle driver on entering into LP2 idle-state, but the
online status is not touched by the cpuidle. This fixes a storm of
warnings once LP2 idling state is enabled on Tegra30. The outer_disable()
helper has sanity checks for interrupts and secondary CPUs being disabled
and we are pretty confident about the interrupts state during of CPU
idling / system suspend. The rail-off status check is added in this patch
as equivalent for the "num_online_cpus() > 1".
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/pm.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 7d9ef26e52a7..d1e1a61b12cf 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -138,6 +138,10 @@ void tegra_pm_set_cpu_in_lp2(void)
static int tegra_sleep_cpu(unsigned long v2p)
{
+ if (tegra_cpu_car_ops->rail_off_ready &&
+ WARN_ON(!tegra_cpu_rail_off_ready()))
+ return -EBUSY;
+
/*
* L2 cache disabling using kernel API only allowed when all
* secondary CPU's are offline. Cache have to be disabled with
@@ -146,9 +150,10 @@ static int tegra_sleep_cpu(unsigned long v2p)
* if any of secondary CPU's is online and this is the LP2-idle
* code-path only for Tegra20/30.
*/
- if (trusted_foundations_registered())
- outer_disable();
-
+#ifdef CONFIG_OUTER_CACHE
+ if (trusted_foundations_registered() && outer_cache.disable)
+ outer_cache.disable();
+#endif
/*
* Note that besides of setting up CPU reset vector this firmware
* call may also do the following, depending on the FW version:
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (7 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 08/18] ARM: tegra: Make outer_disable() open-coded Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-29 13:19 ` Thierry Reding
2019-10-15 17:00 ` [PATCH v6 10/18] arm: tegra20: cpuidle: Handle case where secondary CPU hangs on entering LP2 Dmitry Osipenko
` (9 subsequent siblings)
18 siblings, 1 reply; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in
order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
include/linux/clk/tegra.h | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/include/linux/clk/tegra.h b/include/linux/clk/tegra.h
index 6a7cbc3cfadc..2b1b35240074 100644
--- a/include/linux/clk/tegra.h
+++ b/include/linux/clk/tegra.h
@@ -108,6 +108,19 @@ static inline void tegra_cpu_clock_resume(void)
tegra_cpu_car_ops->resume();
}
+#else
+static inline bool tegra_cpu_rail_off_ready(void)
+{
+ return false;
+}
+
+static inline void tegra_cpu_clock_suspend(void)
+{
+}
+
+static inline void tegra_cpu_clock_resume(void)
+{
+}
#endif
extern void tegra210_xusb_pll_hw_control_enable(void);
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP
2019-10-15 17:00 ` [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Dmitry Osipenko
@ 2019-10-29 13:19 ` Thierry Reding
0 siblings, 0 replies; 28+ messages in thread
From: Thierry Reding @ 2019-10-29 13:19 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Jonathan Hunter, Peter De Schrijver, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 480 bytes --]
On Tue, Oct 15, 2019 at 08:00:06PM +0300, Dmitry Osipenko wrote:
> The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
> strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in
> order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n.
>
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
> include/linux/clk/tegra.h | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Applied to for-5.5/clk, thanks.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v6 10/18] arm: tegra20: cpuidle: Handle case where secondary CPU hangs on entering LP2
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (8 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 09/18] clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 11/18] arm: tegra20: cpuidle: Make abort_flag atomic Dmitry Osipenko
` (8 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
It is possible that something may go wrong with the secondary CPU, in that
case it is much nicer to get a dump of the flow-controller state before
hanging machine.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 46 +++++++++++++++++++++++++--
1 file changed, 44 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index 77702dd42479..bc5873e92af5 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -83,14 +83,56 @@ static inline void tegra20_wake_cpu1_from_reset(void)
}
#endif
+static void tegra20_report_cpus_state(void)
+{
+ unsigned int cpu, lcpu;
+
+ pr_err("secondary CPU taking too long to park\n");
+
+ for_each_cpu(lcpu, cpu_possible_mask) {
+ cpu = cpu_logical_map(lcpu);
+
+ pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n",
+ cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu));
+ }
+}
+
+static int tegra20_wait_for_secondary_cpu_parking(void)
+{
+ unsigned int retries = 3;
+
+ while (retries--) {
+ ktime_t timeout = ktime_add_ms(ktime_get(), 500);
+
+ /*
+ * The primary CPU0 core shall wait for the secondaries
+ * shutdown in order to power-off CPU's cluster safely.
+ * The timeout value depends on the current CPU frequency,
+ * it takes about 40-150us in average and over 1000us in
+ * a worst case scenario.
+ */
+ do {
+ if (tegra_cpu_rail_off_ready())
+ return 0;
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ tegra20_report_cpus_state();
+ }
+
+ pr_err("timed out waiting secondaries to park\n");
+
+ return -ETIMEDOUT;
+}
+
static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
{
bool ret;
- while (!tegra_cpu_rail_off_ready())
- cpu_relax();
+ if (tegra20_wait_for_secondary_cpu_parking())
+ return false;
ret = !tegra_pm_enter_lp2();
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 11/18] arm: tegra20: cpuidle: Make abort_flag atomic
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (9 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 10/18] arm: tegra20: cpuidle: Handle case where secondary CPU hangs on entering LP2 Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 12/18] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier Dmitry Osipenko
` (7 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Replace memory accessors with atomic API just to make code consistent
with the abort_barrier. The new variant may be even more correct now since
atomic_read() will prevent compiler from generating wrong things like
carrying abort_flag value in a register instead of re-fetching it from
memory.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index bc5873e92af5..fe80f1988120 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -32,7 +32,7 @@
#include "sleep.h"
#ifdef CONFIG_PM_SLEEP
-static bool abort_flag;
+static atomic_t abort_flag;
static atomic_t abort_barrier;
static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
@@ -167,13 +167,14 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
bool entered_lp2 = false;
if (tegra_pending_sgi())
- WRITE_ONCE(abort_flag, true);
+ atomic_set(&abort_flag, 1);
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
- if (abort_flag) {
+ if (atomic_read(&abort_flag)) {
cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
- abort_flag = false; /* clean flag for next coming */
+ /* clean flag for next coming */
+ atomic_set(&abort_flag, 0);
return -EINTR;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 12/18] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (10 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 11/18] arm: tegra20: cpuidle: Make abort_flag atomic Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 13/18] cpuidle: Refactor and move NVIDIA Tegra20 driver into drivers/cpuidle/ Dmitry Osipenko
` (6 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
There is no good justification for smp_rmb() after returning from LP2
because there are no memory operations that require SMP synchronization.
Thus remove the confusing barrier.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/cpuidle-tegra20.c | 2 --
arch/arm/mach-tegra/cpuidle-tegra30.c | 2 --
2 files changed, 4 deletions(-)
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index fe80f1988120..af2cd339db43 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -193,8 +193,6 @@ static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
local_fiq_enable();
- smp_rmb();
-
return entered_lp2 ? index : 0;
}
#endif
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index a4f0add46a27..80ae64bcdf50 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -113,8 +113,6 @@ static int tegra30_idle_lp2(struct cpuidle_device *dev,
local_fiq_enable();
- smp_rmb();
-
return (entered_lp2) ? index : 0;
}
#endif
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 13/18] cpuidle: Refactor and move NVIDIA Tegra20 driver into drivers/cpuidle/
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (11 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 12/18] arm: tegra20/30: cpuidle: Remove unnecessary memory barrier Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 14/18] cpuidle: tegra: Squash Tegra30 driver into the common driver Dmitry Osipenko
` (5 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The driver's code is refactored in a way that will make it easy to support
Tegra30/114/124 SoCs by this driver later on. The functionality is equal
to the old Tegra20 driver, only the code's structure changed a tad and
it's a platform driver now.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/Makefile | 3 -
arch/arm/mach-tegra/cpuidle-tegra20.c | 215 ----------------------
arch/arm/mach-tegra/cpuidle.c | 14 +-
arch/arm/mach-tegra/cpuidle.h | 4 -
drivers/cpuidle/Kconfig.arm | 8 +
drivers/cpuidle/Makefile | 1 +
drivers/cpuidle/cpuidle-tegra.c | 251 ++++++++++++++++++++++++++
include/soc/tegra/cpuidle.h | 2 +-
8 files changed, 263 insertions(+), 235 deletions(-)
delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra20.c
create mode 100644 drivers/cpuidle/cpuidle-tegra.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 965862608ff6..8425bb5608d5 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,9 +12,6 @@ obj-y += sleep-tegra20.o
obj-y += sleep-tegra30.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o
-endif
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
ifeq ($(CONFIG_CPU_IDLE),y)
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
deleted file mode 100644
index af2cd339db43..000000000000
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ /dev/null
@@ -1,215 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/clk/tegra.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/ktime.h>
-#include <linux/module.h>
-
-#include <soc/tegra/flowctrl.h>
-#include <soc/tegra/pm.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-
-#include "cpuidle.h"
-#include "iomap.h"
-#include "irq.h"
-#include "reset.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-static atomic_t abort_flag;
-static atomic_t abort_barrier;
-static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
-#define TEGRA20_MAX_STATES 2
-#else
-#define TEGRA20_MAX_STATES 1
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
- .states = {
- ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- {
- .enter = tegra20_idle_lp2_coupled,
- .exit_latency = 5000,
- .target_residency = 10000,
- .power_usage = 0,
- .flags = CPUIDLE_FLAG_COUPLED |
- CPUIDLE_FLAG_TIMER_STOP,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
- .state_count = TEGRA20_MAX_STATES,
- .safe_state_index = 0,
-};
-
-#ifdef CONFIG_PM_SLEEP
-#ifdef CONFIG_SMP
-static void tegra20_wake_cpu1_from_reset(void)
-{
- /* enable cpu clock on cpu */
- tegra_enable_cpu_clock(1);
-
- /* take the CPU out of reset */
- tegra_cpu_out_of_reset(1);
-
- /* unhalt the cpu */
- flowctrl_write_cpu_halt(1, 0);
-}
-#else
-static inline void tegra20_wake_cpu1_from_reset(void)
-{
-}
-#endif
-
-static void tegra20_report_cpus_state(void)
-{
- unsigned int cpu, lcpu;
-
- pr_err("secondary CPU taking too long to park\n");
-
- for_each_cpu(lcpu, cpu_possible_mask) {
- cpu = cpu_logical_map(lcpu);
-
- pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n",
- cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu));
- }
-}
-
-static int tegra20_wait_for_secondary_cpu_parking(void)
-{
- unsigned int retries = 3;
-
- while (retries--) {
- ktime_t timeout = ktime_add_ms(ktime_get(), 500);
-
- /*
- * The primary CPU0 core shall wait for the secondaries
- * shutdown in order to power-off CPU's cluster safely.
- * The timeout value depends on the current CPU frequency,
- * it takes about 40-150us in average and over 1000us in
- * a worst case scenario.
- */
- do {
- if (tegra_cpu_rail_off_ready())
- return 0;
-
- } while (ktime_before(ktime_get(), timeout));
-
- tegra20_report_cpus_state();
- }
-
- pr_err("timed out waiting secondaries to park\n");
-
- return -ETIMEDOUT;
-}
-
-static bool tegra20_cpu_cluster_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- bool ret;
-
- if (tegra20_wait_for_secondary_cpu_parking())
- return false;
-
- ret = !tegra_pm_enter_lp2();
-
- if (cpu_online(1))
- tegra20_wake_cpu1_from_reset();
-
- return ret;
-}
-
-#ifdef CONFIG_SMP
-static bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- cpu_suspend(dev->cpu, tegra_pm_park_secondary_cpu);
-
- return true;
-}
-#else
-static inline bool tegra20_idle_enter_lp2_cpu_1(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- return true;
-}
-#endif
-
-static int tegra20_idle_lp2_coupled(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- bool entered_lp2 = false;
-
- if (tegra_pending_sgi())
- atomic_set(&abort_flag, 1);
-
- cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
-
- if (atomic_read(&abort_flag)) {
- cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
- /* clean flag for next coming */
- atomic_set(&abort_flag, 0);
- return -EINTR;
- }
-
- local_fiq_disable();
-
- tegra_pm_set_cpu_in_lp2();
- cpu_pm_enter();
-
- if (dev->cpu == 0)
- entered_lp2 = tegra20_cpu_cluster_power_down(dev, drv, index);
- else
- entered_lp2 = tegra20_idle_enter_lp2_cpu_1(dev, drv, index);
-
- cpu_pm_exit();
- tegra_pm_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- return entered_lp2 ? index : 0;
-}
-#endif
-
-/*
- * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
- * they are legacy IRQs or MSI, are lost when LP2 is enabled. To work around
- * this, simply disable LP2 if the PCI driver and DT node are both enabled.
- */
-void tegra20_cpuidle_pcie_irqs_in_use(void)
-{
- pr_info_once(
- "Disabling cpuidle LP2 state, since PCIe IRQs are in use\n");
- tegra_idle_driver.states[1].disabled = true;
-}
-
-int __init tegra20_cpuidle_init(void)
-{
- return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
-}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index d565c44cfc93..eee85d517783 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -14,6 +14,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
+#include <linux/platform_device.h>
#include <soc/tegra/fuse.h>
@@ -23,8 +24,7 @@ void __init tegra_cpuidle_init(void)
{
switch (tegra_get_chip_id()) {
case TEGRA20:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
- tegra20_cpuidle_init();
+ platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
break;
case TEGRA30:
if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
@@ -38,13 +38,3 @@ void __init tegra_cpuidle_init(void)
break;
}
}
-
-void tegra_cpuidle_pcie_irqs_in_use(void)
-{
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
- tegra20_cpuidle_pcie_irqs_in_use();
- break;
- }
-}
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index 4e1f459f5bd8..eeb37baf18e1 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -7,15 +7,11 @@
#define __MACH_TEGRA_CPUIDLE_H
#ifdef CONFIG_CPU_IDLE
-int tegra20_cpuidle_init(void);
-void tegra20_cpuidle_pcie_irqs_in_use(void);
int tegra30_cpuidle_init(void);
int tegra114_cpuidle_init(void);
void tegra_cpuidle_init(void);
-void tegra_cpuidle_pcie_irqs_in_use(void);
#else
static inline void tegra_cpuidle_init(void) {}
-static inline void tegra_cpuidle_pcie_irqs_in_use(void) {}
#endif
#endif
diff --git a/drivers/cpuidle/Kconfig.arm b/drivers/cpuidle/Kconfig.arm
index d8530475493c..6952bf7bb260 100644
--- a/drivers/cpuidle/Kconfig.arm
+++ b/drivers/cpuidle/Kconfig.arm
@@ -86,3 +86,11 @@ config ARM_MVEBU_V7_CPUIDLE
depends on ARCH_MVEBU && !ARM64
help
Select this to enable cpuidle on Armada 370, 38x and XP processors.
+
+config ARM_TEGRA_CPUIDLE
+ bool "CPU Idle Driver for NVIDIA Tegra SoCs"
+ depends on ARCH_TEGRA && !ARM64
+ select ARCH_NEEDS_CPU_IDLE_COUPLED if SMP
+ select ARM_CPU_SUSPEND
+ help
+ Select this to enable cpuidle for NVIDIA Tegra20/30/114/124 SoCs.
diff --git a/drivers/cpuidle/Makefile b/drivers/cpuidle/Makefile
index ee70d5cc5b99..a15e4808d295 100644
--- a/drivers/cpuidle/Makefile
+++ b/drivers/cpuidle/Makefile
@@ -22,6 +22,7 @@ obj-$(CONFIG_ARM_AT91_CPUIDLE) += cpuidle-at91.o
obj-$(CONFIG_ARM_EXYNOS_CPUIDLE) += cpuidle-exynos.o
obj-$(CONFIG_ARM_CPUIDLE) += cpuidle-arm.o
obj-$(CONFIG_ARM_PSCI_CPUIDLE) += cpuidle-psci.o
+obj-$(CONFIG_ARM_TEGRA_CPUIDLE) += cpuidle-tegra.o
###############################################################################
# MIPS drivers
diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c
new file mode 100644
index 000000000000..491fc90387c3
--- /dev/null
+++ b/drivers/cpuidle/cpuidle-tegra.c
@@ -0,0 +1,251 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * CPU idle driver for Tegra CPUs
+ *
+ * Copyright (c) 2010-2013, NVIDIA Corporation.
+ * Copyright (c) 2011 Google, Inc.
+ * Author: Colin Cross <ccross@android.com>
+ * Gary King <gking@nvidia.com>
+ *
+ * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
+ *
+ * Tegra20/124 driver unification by Dmitry Osipenko <digetx@gmail.com>
+ */
+
+#define pr_fmt(fmt) "tegra-cpuidle: " fmt
+
+#include <linux/atomic.h>
+#include <linux/cpuidle.h>
+#include <linux/cpumask.h>
+#include <linux/cpu_pm.h>
+#include <linux/errno.h>
+#include <linux/ktime.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include <linux/clk/tegra.h>
+
+#include <soc/tegra/cpuidle.h>
+#include <soc/tegra/flowctrl.h>
+#include <soc/tegra/fuse.h>
+#include <soc/tegra/irq.h>
+#include <soc/tegra/pm.h>
+
+#include <asm/cpuidle.h>
+#include <asm/smp_plat.h>
+#include <asm/suspend.h>
+
+enum {
+ TEGRA_C1,
+ TEGRA_CC6,
+ TEGRA_STATE_COUNT,
+};
+
+static atomic_t tegra_idle_barrier;
+static atomic_t tegra_abort_flag;
+
+static void tegra_cpuidle_report_cpus_state(void)
+{
+ unsigned int cpu, lcpu;
+
+ pr_err("secondary CPU taking too long to park\n");
+
+ for_each_cpu(lcpu, cpu_possible_mask) {
+ cpu = cpu_logical_map(lcpu);
+
+ pr_err("cpu%u: online=%d flowctrl_csr=0x%08x\n",
+ cpu, cpu_online(lcpu), flowctrl_read_cpu_csr(cpu));
+ }
+}
+
+static int tegra_cpuidle_wait_for_secondary_cpus_parking(void)
+{
+ unsigned int retries = 3;
+
+ while (retries--) {
+ ktime_t timeout = ktime_add_ms(ktime_get(), 500);
+
+ /*
+ * The primary CPU0 core shall wait for the secondaries
+ * shutdown in order to power-off CPU's cluster safely.
+ * The timeout value depends on the current CPU frequency,
+ * it takes about 40-150us in average and over 1000us in
+ * a worst case scenario.
+ */
+ do {
+ if (tegra_cpu_rail_off_ready())
+ return 0;
+
+ } while (ktime_before(ktime_get(), timeout));
+
+ tegra_cpuidle_report_cpus_state();
+ }
+
+ pr_err("timed out waiting secondaries to park\n");
+
+ return -ETIMEDOUT;
+}
+
+static void tegra_cpuidle_unpark_secondary_cpus(void)
+{
+ unsigned int cpu, lcpu;
+
+ for_each_cpu(lcpu, cpu_online_mask) {
+ cpu = cpu_logical_map(lcpu);
+
+ if (cpu > 0) {
+ tegra_enable_cpu_clock(cpu);
+ tegra_cpu_out_of_reset(cpu);
+ flowctrl_write_cpu_halt(cpu, 0);
+ }
+ }
+}
+
+static int tegra_cpuidle_cc6_enter(unsigned int cpu)
+{
+ int ret;
+
+ if (cpu > 0) {
+ ret = cpu_suspend(cpu, tegra_pm_park_secondary_cpu);
+ } else {
+ ret = tegra_cpuidle_wait_for_secondary_cpus_parking();
+ if (!ret)
+ ret = tegra_pm_enter_lp2();
+
+ tegra_cpuidle_unpark_secondary_cpus();
+ }
+
+ return ret;
+}
+
+static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev)
+{
+ if (tegra_pending_sgi()) {
+ /*
+ * CPU got local interrupt that will be lost after GIC's
+ * shutdown because GIC driver doesn't save/restore the
+ * pending SGI state across CPU cluster PM. Abort and retry
+ * next time.
+ */
+ atomic_set(&tegra_abort_flag, 1);
+ }
+
+ cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
+
+ if (atomic_read(&tegra_abort_flag)) {
+ cpuidle_coupled_parallel_barrier(dev, &tegra_idle_barrier);
+ atomic_set(&tegra_abort_flag, 0);
+ return -EINTR;
+ }
+
+ return 0;
+}
+
+static int tegra_cpuidle_state_enter(struct cpuidle_device *dev,
+ int index, unsigned int cpu)
+{
+ int ret;
+
+ /*
+ * CC6 state is the "CPU cluster power-off" state. In order to
+ * enter this state, at first the secondary CPU cores need to be
+ * parked into offline mode, then the last CPU should clean out
+ * remaining dirty cache lines into DRAM and trigger Flow Controller
+ * logic that turns off the cluster's power domain (which includes
+ * CPU cores, GIC and L2 cache).
+ */
+ if (index == TEGRA_CC6) {
+ ret = tegra_cpuidle_coupled_barrier(dev);
+ if (ret)
+ return ret;
+ }
+
+ local_fiq_disable();
+ tegra_pm_set_cpu_in_lp2();
+ cpu_pm_enter();
+
+ switch (index) {
+ case TEGRA_CC6:
+ ret = tegra_cpuidle_cc6_enter(cpu);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ cpu_pm_exit();
+ tegra_pm_clear_cpu_in_lp2();
+ local_fiq_enable();
+
+ return ret;
+}
+
+static int tegra_cpuidle_enter(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ unsigned int cpu = cpu_logical_map(dev->cpu);
+ int err;
+
+ err = tegra_cpuidle_state_enter(dev, index, cpu);
+ if (err && err != -EINTR)
+ pr_err_once("cpu%u failed to enter idle state %d err: %d\n",
+ cpu, index, err);
+
+ return err ? -1 : index;
+}
+
+static struct cpuidle_driver tegra_idle_driver = {
+ .name = "tegra_idle",
+ .states = {
+ [TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+ [TEGRA_CC6] = {
+ .enter = tegra_cpuidle_enter,
+ .exit_latency = 5000,
+ .target_residency = 10000,
+ .power_usage = 0,
+ .flags = CPUIDLE_FLAG_TIMER_STOP |
+ CPUIDLE_FLAG_COUPLED,
+ .name = "CC6",
+ .desc = "CPU cluster powered off",
+ },
+ },
+ .state_count = TEGRA_STATE_COUNT,
+ .safe_state_index = TEGRA_C1,
+};
+
+/*
+ * Tegra20 HW appears to have a bug such that PCIe device interrupts, whether
+ * they are legacy IRQs or MSI, are lost when CC6 is enabled. To work around
+ * this, simply disable CC6 if the PCI driver and DT node are both enabled.
+ */
+void tegra_cpuidle_pcie_irqs_in_use(void)
+{
+ if (tegra_idle_driver.states[TEGRA_CC6].disabled ||
+ tegra_get_chip_id() != TEGRA20)
+ return;
+
+ pr_info("disabling CC6 state, since PCIe IRQs are in use\n");
+ tegra_idle_driver.states[TEGRA_CC6].disabled = true;
+}
+
+static int tegra_cpuidle_probe(struct platform_device *pdev)
+{
+ /*
+ * Required suspend-resume functionality, which is provided by the
+ * Tegra-arch core and PMC driver, is unavailable if PM-sleep option
+ * is disabled.
+ */
+ if (!IS_ENABLED(CONFIG_PM_SLEEP))
+ tegra_idle_driver.states[TEGRA_CC6].disabled = true;
+
+ return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
+}
+
+static struct platform_driver tegra_cpuidle_driver = {
+ .probe = tegra_cpuidle_probe,
+ .driver = {
+ .name = "tegra-cpuidle",
+ },
+};
+builtin_platform_driver(tegra_cpuidle_driver);
diff --git a/include/soc/tegra/cpuidle.h b/include/soc/tegra/cpuidle.h
index 029ba1f4b2cc..5665975015d8 100644
--- a/include/soc/tegra/cpuidle.h
+++ b/include/soc/tegra/cpuidle.h
@@ -6,7 +6,7 @@
#ifndef __SOC_TEGRA_CPUIDLE_H__
#define __SOC_TEGRA_CPUIDLE_H__
-#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_TEGRA) && defined(CONFIG_CPU_IDLE)
+#ifdef CONFIG_ARM_TEGRA_CPUIDLE
void tegra_cpuidle_pcie_irqs_in_use(void);
#else
static inline void tegra_cpuidle_pcie_irqs_in_use(void)
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 14/18] cpuidle: tegra: Squash Tegra30 driver into the common driver
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (12 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 13/18] cpuidle: Refactor and move NVIDIA Tegra20 driver into drivers/cpuidle/ Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 15/18] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Dmitry Osipenko
` (4 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Tegra20 and Terga30 SoCs have common C1 and CC6 idling states and thus
share the same code paths, there is no point in having separate drivers
for a similar hardware. This patch merely moves functionality of the old
driver into the new, although the CC6 state is kept disabled for now since
old driver had a rudimentary support for this state (allowing to enter
into CC6 only when secondary CPUs are put offline), while new driver can
provide a full-featured support. The new feature will be enabled by
another patch.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/Makefile | 3 -
arch/arm/mach-tegra/cpuidle-tegra30.c | 123 --------------------------
arch/arm/mach-tegra/cpuidle.c | 5 +-
arch/arm/mach-tegra/cpuidle.h | 1 -
drivers/cpuidle/cpuidle-tegra.c | 75 ++++++++++++++--
5 files changed, 71 insertions(+), 136 deletions(-)
delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra30.c
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 8425bb5608d5..99c5f4274e5c 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -13,9 +13,6 @@ obj-y += sleep-tegra30.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
-endif
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
deleted file mode 100644
index 80ae64bcdf50..000000000000
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ /dev/null
@@ -1,123 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/clk/tegra.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <soc/tegra/pm.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-
-#include "cpuidle.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index);
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
-#ifdef CONFIG_PM_SLEEP
- .state_count = 2,
-#else
- .state_count = 1,
-#endif
- .states = {
- [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- [1] = {
- .enter = tegra30_idle_lp2,
- .exit_latency = 2000,
- .target_residency = 2200,
- .power_usage = 0,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
-};
-
-#ifdef CONFIG_PM_SLEEP
-static bool tegra30_cpu_cluster_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- /* All CPUs entering LP2 is not working.
- * Don't let CPU0 enter LP2 when any secondary CPU is online.
- */
- if (num_online_cpus() > 1 || !tegra_cpu_rail_off_ready()) {
- cpu_do_idle();
- return false;
- }
-
- return !tegra_pm_enter_lp2();
-}
-
-#ifdef CONFIG_SMP
-static bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- smp_wmb();
-
- cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
-
- return true;
-}
-#else
-static inline bool tegra30_cpu_core_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- return true;
-}
-#endif
-
-static int tegra30_idle_lp2(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- bool entered_lp2 = false;
-
- local_fiq_disable();
-
- tegra_pm_set_cpu_in_lp2();
- cpu_pm_enter();
-
- if (dev->cpu == 0)
- entered_lp2 = tegra30_cpu_cluster_power_down(dev, drv, index);
- else
- entered_lp2 = tegra30_cpu_core_power_down(dev, drv, index);
-
- cpu_pm_exit();
- tegra_pm_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- return (entered_lp2) ? index : 0;
-}
-#endif
-
-int __init tegra30_cpuidle_init(void)
-{
- return cpuidle_register(&tegra_idle_driver, NULL);
-}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
index eee85d517783..fa0dcf3c2c45 100644
--- a/arch/arm/mach-tegra/cpuidle.c
+++ b/arch/arm/mach-tegra/cpuidle.c
@@ -24,11 +24,8 @@ void __init tegra_cpuidle_init(void)
{
switch (tegra_get_chip_id()) {
case TEGRA20:
- platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
- break;
case TEGRA30:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC))
- tegra30_cpuidle_init();
+ platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
break;
case TEGRA114:
case TEGRA124:
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
index eeb37baf18e1..5423a05a69f6 100644
--- a/arch/arm/mach-tegra/cpuidle.h
+++ b/arch/arm/mach-tegra/cpuidle.h
@@ -7,7 +7,6 @@
#define __MACH_TEGRA_CPUIDLE_H
#ifdef CONFIG_CPU_IDLE
-int tegra30_cpuidle_init(void);
int tegra114_cpuidle_init(void);
void tegra_cpuidle_init(void);
#else
diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c
index 491fc90387c3..1a2cff5d4ff3 100644
--- a/drivers/cpuidle/cpuidle-tegra.c
+++ b/drivers/cpuidle/cpuidle-tegra.c
@@ -37,6 +37,7 @@
enum {
TEGRA_C1,
+ TEGRA_C7,
TEGRA_CC6,
TEGRA_STATE_COUNT,
};
@@ -118,6 +119,11 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu)
return ret;
}
+static int tegra_cpuidle_c7_enter(void)
+{
+ return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
+}
+
static int tegra_cpuidle_coupled_barrier(struct cpuidle_device *dev)
{
if (tegra_pending_sgi()) {
@@ -165,6 +171,9 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev,
cpu_pm_enter();
switch (index) {
+ case TEGRA_C7:
+ ret = tegra_cpuidle_c7_enter();
+ break;
case TEGRA_CC6:
ret = tegra_cpuidle_cc6_enter(cpu);
break;
@@ -180,6 +189,28 @@ static int tegra_cpuidle_state_enter(struct cpuidle_device *dev,
return ret;
}
+static int tegra_cpuidle_adjust_state_index(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index, unsigned int cpu)
+{
+ /*
+ * On Tegra30 CPU0 can't be power-gated while secondary CPUs
+ * are active because it gates the whole CPU cluster.
+ */
+ if (cpu != 0 || index != TEGRA_C7 || tegra_get_chip_id() != TEGRA30)
+ return index;
+
+ if (!IS_ENABLED(CONFIG_PM_SLEEP) || num_online_cpus() > 1)
+ index = TEGRA_C1;
+ else
+ index = TEGRA_CC6;
+
+ if (drv->states[index].disabled || dev->states_usage[index].disable)
+ index = -1;
+
+ return index;
+}
+
static int tegra_cpuidle_enter(struct cpuidle_device *dev,
struct cpuidle_driver *drv,
int index)
@@ -187,10 +218,17 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev,
unsigned int cpu = cpu_logical_map(dev->cpu);
int err;
- err = tegra_cpuidle_state_enter(dev, index, cpu);
- if (err && err != -EINTR)
- pr_err_once("cpu%u failed to enter idle state %d err: %d\n",
- cpu, index, err);
+ index = tegra_cpuidle_adjust_state_index(dev, drv, index, cpu);
+ if (index < 0)
+ return index;
+
+ if (index == TEGRA_C1)
+ err = arm_cpuidle_simple_enter(dev, drv, index);
+ else
+ err = tegra_cpuidle_state_enter(dev, index, cpu);
+
+ if (err && (err != -EINTR || index != TEGRA_CC6))
+ pr_err_once("failed to enter state %d err: %d\n", index, err);
return err ? -1 : index;
}
@@ -199,6 +237,15 @@ static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.states = {
[TEGRA_C1] = ARM_CPUIDLE_WFI_STATE_PWR(600),
+ [TEGRA_C7] = {
+ .enter = tegra_cpuidle_enter,
+ .exit_latency = 2000,
+ .target_residency = 2200,
+ .power_usage = 100,
+ .flags = CPUIDLE_FLAG_TIMER_STOP,
+ .name = "C7",
+ .desc = "CPU core powered off",
+ },
[TEGRA_CC6] = {
.enter = tegra_cpuidle_enter,
.exit_latency = 5000,
@@ -236,8 +283,26 @@ static int tegra_cpuidle_probe(struct platform_device *pdev)
* Tegra-arch core and PMC driver, is unavailable if PM-sleep option
* is disabled.
*/
- if (!IS_ENABLED(CONFIG_PM_SLEEP))
+ if (!IS_ENABLED(CONFIG_PM_SLEEP)) {
+ tegra_idle_driver.states[TEGRA_C7].disabled = true;
+ tegra_idle_driver.states[TEGRA_CC6].disabled = true;
+ }
+
+ /*
+ * Generic WFI state (also known as C1 or LP3) and the coupled CPU
+ * cluster power-off (CC6 or LP2) states are common for all Tegra SoCs.
+ */
+ switch (tegra_get_chip_id()) {
+ case TEGRA20:
+ /* Tegra20 isn't capable to power-off individual CPU cores */
+ tegra_idle_driver.states[TEGRA_C7].disabled = true;
+ break;
+ case TEGRA30:
tegra_idle_driver.states[TEGRA_CC6].disabled = true;
+ break;
+ default:
+ return -EINVAL;
+ }
return cpuidle_register(&tegra_idle_driver, cpu_possible_mask);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 15/18] cpuidle: tegra: Support CPU cluster power-down state on Tegra30
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (13 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 14/18] cpuidle: tegra: Squash Tegra30 driver into the common driver Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 16/18] cpuidle: tegra: Squash Tegra114 driver into the common driver Dmitry Osipenko
` (3 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The new Tegra CPU Idle driver now has a unified code path for the coupled
CC6 (LP2) state, this allows to enable the deepest idling state on Tegra30
SoC where the whole CPU cluster is power-gated.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
drivers/cpuidle/cpuidle-tegra.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c
index 1a2cff5d4ff3..e38a2f6c11e1 100644
--- a/drivers/cpuidle/cpuidle-tegra.c
+++ b/drivers/cpuidle/cpuidle-tegra.c
@@ -298,7 +298,6 @@ static int tegra_cpuidle_probe(struct platform_device *pdev)
tegra_idle_driver.states[TEGRA_C7].disabled = true;
break;
case TEGRA30:
- tegra_idle_driver.states[TEGRA_CC6].disabled = true;
break;
default:
return -EINVAL;
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 16/18] cpuidle: tegra: Squash Tegra114 driver into the common driver
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (14 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 15/18] cpuidle: tegra: Support CPU cluster power-down state on Tegra30 Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 17/18] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Dmitry Osipenko
` (2 subsequent siblings)
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
Tegra20/30/114/124 SoCs have common idling states, thus there is no much
point in having separate drivers for a similar hardware. This patch moves
Tegra114/124 arch/ drivers into the common driver without any functional
changes. The CC6 state is kept disabled on Tegra114/124 because the core
Tegra PM code needs some more work in order to support that state.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/mach-tegra/Makefile | 7 --
arch/arm/mach-tegra/cpuidle-tegra114.c | 90 --------------------------
arch/arm/mach-tegra/cpuidle.c | 37 -----------
arch/arm/mach-tegra/cpuidle.h | 16 -----
arch/arm/mach-tegra/tegra.c | 6 +-
drivers/cpuidle/cpuidle-tegra.c | 44 ++++++++++++-
6 files changed, 47 insertions(+), 153 deletions(-)
delete mode 100644 arch/arm/mach-tegra/cpuidle-tegra114.c
delete mode 100644 arch/arm/mach-tegra/cpuidle.c
delete mode 100644 arch/arm/mach-tegra/cpuidle.h
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 99c5f4274e5c..07572b5373b8 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -10,19 +10,12 @@ obj-y += sleep.o
obj-y += tegra.o
obj-y += sleep-tegra20.o
obj-y += sleep-tegra30.o
-obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
-endif
obj-$(CONFIG_ARCH_TEGRA_124_SOC) += pm-tegra30.o
-ifeq ($(CONFIG_CPU_IDLE),y)
-obj-$(CONFIG_ARCH_TEGRA_124_SOC) += cpuidle-tegra114.o
-endif
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
deleted file mode 100644
index 858c30cc5dc7..000000000000
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ /dev/null
@@ -1,90 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Copyright (c) 2013, NVIDIA Corporation. All rights reserved.
- */
-
-#include <asm/firmware.h>
-#include <linux/tick.h>
-#include <linux/cpuidle.h>
-#include <linux/cpu_pm.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <linux/firmware/trusted_foundations.h>
-
-#include <soc/tegra/pm.h>
-
-#include <asm/cpuidle.h>
-#include <asm/smp_plat.h>
-#include <asm/suspend.h>
-#include <asm/psci.h>
-
-#include "cpuidle.h"
-#include "sleep.h"
-
-#ifdef CONFIG_PM_SLEEP
-#define TEGRA114_MAX_STATES 2
-#else
-#define TEGRA114_MAX_STATES 1
-#endif
-
-#ifdef CONFIG_PM_SLEEP
-static int tegra114_idle_power_down(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- local_fiq_disable();
-
- tegra_pm_set_cpu_in_lp2();
- cpu_pm_enter();
-
- call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
-
- /* Do suspend by ourselves if the firmware does not implement it */
- if (call_firmware_op(do_idle, 0) == -ENOSYS)
- cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
-
- cpu_pm_exit();
- tegra_pm_clear_cpu_in_lp2();
-
- local_fiq_enable();
-
- return index;
-}
-
-static void tegra114_idle_enter_s2idle(struct cpuidle_device *dev,
- struct cpuidle_driver *drv,
- int index)
-{
- tegra114_idle_power_down(dev, drv, index);
-}
-#endif
-
-static struct cpuidle_driver tegra_idle_driver = {
- .name = "tegra_idle",
- .owner = THIS_MODULE,
- .state_count = TEGRA114_MAX_STATES,
- .states = {
- [0] = ARM_CPUIDLE_WFI_STATE_PWR(600),
-#ifdef CONFIG_PM_SLEEP
- [1] = {
- .enter = tegra114_idle_power_down,
- .enter_s2idle = tegra114_idle_enter_s2idle,
- .exit_latency = 500,
- .target_residency = 1000,
- .flags = CPUIDLE_FLAG_TIMER_STOP,
- .power_usage = 0,
- .name = "powered-down",
- .desc = "CPU power gated",
- },
-#endif
- },
-};
-
-int __init tegra114_cpuidle_init(void)
-{
- if (!psci_smp_available())
- return cpuidle_register(&tegra_idle_driver, NULL);
-
- return 0;
-}
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c
deleted file mode 100644
index fa0dcf3c2c45..000000000000
--- a/arch/arm/mach-tegra/cpuidle.c
+++ /dev/null
@@ -1,37 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- * arch/arm/mach-tegra/cpuidle.c
- *
- * CPU idle driver for Tegra CPUs
- *
- * Copyright (c) 2010-2012, NVIDIA Corporation.
- * Copyright (c) 2011 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- * Gary King <gking@nvidia.com>
- *
- * Rework for 3.3 by Peter De Schrijver <pdeschrijver@nvidia.com>
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <soc/tegra/fuse.h>
-
-#include "cpuidle.h"
-
-void __init tegra_cpuidle_init(void)
-{
- switch (tegra_get_chip_id()) {
- case TEGRA20:
- case TEGRA30:
- platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
- break;
- case TEGRA114:
- case TEGRA124:
- if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) ||
- IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC))
- tegra114_cpuidle_init();
- break;
- }
-}
diff --git a/arch/arm/mach-tegra/cpuidle.h b/arch/arm/mach-tegra/cpuidle.h
deleted file mode 100644
index 5423a05a69f6..000000000000
--- a/arch/arm/mach-tegra/cpuidle.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
- */
-
-#ifndef __MACH_TEGRA_CPUIDLE_H
-#define __MACH_TEGRA_CPUIDLE_H
-
-#ifdef CONFIG_CPU_IDLE
-int tegra114_cpuidle_init(void);
-void tegra_cpuidle_init(void);
-#else
-static inline void tegra_cpuidle_init(void) {}
-#endif
-
-#endif
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 00aaf495bbf7..f1ce2857a251 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -36,11 +36,11 @@
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach-types.h>
+#include <asm/psci.h>
#include <asm/setup.h>
#include "board.h"
#include "common.h"
-#include "cpuidle.h"
#include "iomap.h"
#include "pm.h"
#include "reset.h"
@@ -85,7 +85,6 @@ static void __init tegra_dt_init(void)
static void __init tegra_dt_init_late(void)
{
tegra_init_suspend();
- tegra_cpuidle_init();
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("compal,paz00"))
@@ -94,6 +93,9 @@ static void __init tegra_dt_init_late(void)
if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) &&
of_machine_is_compatible("nvidia,tegra20"))
platform_device_register_simple("tegra20-cpufreq", -1, NULL, 0);
+
+ if (IS_ENABLED(CONFIG_ARM_TEGRA_CPUIDLE) && !psci_smp_available())
+ platform_device_register_simple("tegra-cpuidle", -1, NULL, 0);
}
static const char * const tegra_dt_board_compat[] = {
diff --git a/drivers/cpuidle/cpuidle-tegra.c b/drivers/cpuidle/cpuidle-tegra.c
index e38a2f6c11e1..412d21fd13ed 100644
--- a/drivers/cpuidle/cpuidle-tegra.c
+++ b/drivers/cpuidle/cpuidle-tegra.c
@@ -24,6 +24,7 @@
#include <linux/types.h>
#include <linux/clk/tegra.h>
+#include <linux/firmware/trusted_foundations.h>
#include <soc/tegra/cpuidle.h>
#include <soc/tegra/flowctrl.h>
@@ -32,6 +33,7 @@
#include <soc/tegra/pm.h>
#include <asm/cpuidle.h>
+#include <asm/firmware.h>
#include <asm/smp_plat.h>
#include <asm/suspend.h>
@@ -45,6 +47,11 @@ enum {
static atomic_t tegra_idle_barrier;
static atomic_t tegra_abort_flag;
+static inline bool tegra_cpuidle_using_firmware(void)
+{
+ return firmware_ops->prepare_idle && firmware_ops->do_idle;
+}
+
static void tegra_cpuidle_report_cpus_state(void)
{
unsigned int cpu, lcpu;
@@ -121,6 +128,16 @@ static int tegra_cpuidle_cc6_enter(unsigned int cpu)
static int tegra_cpuidle_c7_enter(void)
{
+ int err;
+
+ if (tegra_cpuidle_using_firmware()) {
+ err = call_firmware_op(prepare_idle, TF_PM_MODE_LP2_NOFLUSH_L2);
+ if (err)
+ return err;
+
+ return call_firmware_op(do_idle, 0);
+ }
+
return cpu_suspend(0, tegra30_pm_secondary_cpu_suspend);
}
@@ -233,6 +250,13 @@ static int tegra_cpuidle_enter(struct cpuidle_device *dev,
return err ? -1 : index;
}
+static void tegra114_enter_s2idle(struct cpuidle_device *dev,
+ struct cpuidle_driver *drv,
+ int index)
+{
+ tegra_cpuidle_enter(dev, drv, index);
+}
+
static struct cpuidle_driver tegra_idle_driver = {
.name = "tegra_idle",
.states = {
@@ -276,6 +300,15 @@ void tegra_cpuidle_pcie_irqs_in_use(void)
tegra_idle_driver.states[TEGRA_CC6].disabled = true;
}
+static void tegra_cpuidle_setup_tegra114_c7_state(void)
+{
+ struct cpuidle_state *s = &tegra_idle_driver.states[TEGRA_C7];
+
+ s->enter_s2idle = tegra114_enter_s2idle;
+ s->target_residency = 1000;
+ s->exit_latency = 500;
+}
+
static int tegra_cpuidle_probe(struct platform_device *pdev)
{
/*
@@ -284,7 +317,9 @@ static int tegra_cpuidle_probe(struct platform_device *pdev)
* is disabled.
*/
if (!IS_ENABLED(CONFIG_PM_SLEEP)) {
- tegra_idle_driver.states[TEGRA_C7].disabled = true;
+ if (!tegra_cpuidle_using_firmware())
+ tegra_idle_driver.states[TEGRA_C7].disabled = true;
+
tegra_idle_driver.states[TEGRA_CC6].disabled = true;
}
@@ -299,6 +334,13 @@ static int tegra_cpuidle_probe(struct platform_device *pdev)
break;
case TEGRA30:
break;
+ case TEGRA114:
+ case TEGRA124:
+ tegra_cpuidle_setup_tegra114_c7_state();
+
+ /* coupled CC6 (LP2) state isn't implemented yet */
+ tegra_idle_driver.states[TEGRA_CC6].disabled = true;
+ break;
default:
return -EINVAL;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 17/18] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (15 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 16/18] cpuidle: tegra: Squash Tegra114 driver into the common driver Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-15 17:00 ` [PATCH v6 18/18] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Dmitry Osipenko
2019-10-16 19:21 ` [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Peter De Schrijver
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and
it is now a proper platform driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e039680d3c72..e15cc31aeaf3 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -110,6 +110,7 @@ CONFIG_CPU_IDLE=y
CONFIG_ARM_CPUIDLE=y
CONFIG_ARM_ZYNQ_CPUIDLE=y
CONFIG_ARM_EXYNOS_CPUIDLE=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_KERNEL_MODE_NEON=y
CONFIG_RASPBERRYPI_FIRMWARE=y
CONFIG_TRUSTED_FOUNDATIONS=y
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* [PATCH v6 18/18] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (16 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 17/18] ARM: multi_v7_defconfig: Enable Tegra cpuidle driver Dmitry Osipenko
@ 2019-10-15 17:00 ` Dmitry Osipenko
2019-10-16 19:21 ` [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Peter De Schrijver
18 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-15 17:00 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Peter De Schrijver,
Rafael J. Wysocki, Daniel Lezcano
Cc: linux-pm, linux-tegra, linux-kernel
The Tegra CPU Idle driver was moved out into driver/cpuidle/ directory and
it is now a proper platform driver.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
arch/arm/configs/tegra_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/tegra_defconfig b/arch/arm/configs/tegra_defconfig
index 8f5c6a5b444c..9a2f11a780a8 100644
--- a/arch/arm/configs/tegra_defconfig
+++ b/arch/arm/configs/tegra_defconfig
@@ -25,6 +25,7 @@ CONFIG_CPU_FREQ=y
CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPUFREQ_DT=y
CONFIG_CPU_IDLE=y
+CONFIG_ARM_TEGRA_CPUIDLE=y
CONFIG_VFP=y
CONFIG_NEON=y
CONFIG_TRUSTED_FOUNDATIONS=y
--
2.23.0
^ permalink raw reply related [flat|nested] 28+ messages in thread* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-15 16:59 [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Dmitry Osipenko
` (17 preceding siblings ...)
2019-10-15 17:00 ` [PATCH v6 18/18] ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig Dmitry Osipenko
@ 2019-10-16 19:21 ` Peter De Schrijver
2019-10-16 19:47 ` Dmitry Osipenko
18 siblings, 1 reply; 28+ messages in thread
From: Peter De Schrijver @ 2019-10-16 19:21 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
> Hello,
>
> This series does the following:
>
> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
> into common drivers/cpuidle/ directory.
>
> 2. Enables CPU cluster power-down idling state on Tegra30.
>
> In the end there is a quite nice clean up of the Tegra CPUIDLE drivers
> and of the Tegra's arch code in general. Please review, thanks!
>
> Changelog:
>
> v6: - Addressed request from Thierry Reding to change the way patches are
> organized by making changes in a more incremental manner.
>
> - tegra_sleep_cpu() now checks for the secondary CPUs to be offline
> in the "Make outer_disable() open-coded" patch.
>
> v5: - Rebased on a recent linux-next, fixed one minor conflict in Kconfig.
>
> - Improved commit's message of the "Support CPU cluster power-down state
> on Tegra30" patch.
>
> - The "Support CPU cluster power-down state on Tegra30" patch is also
> got split and now there is additional "Make outer_disable() open-coded"
> patch.
>
> - Made minor cosmetic changes to the "Introduce unified driver for
> NVIDIA Tegra SoCs" patch by improving error message and renaming
> one variable.
>
> v4: - Fixed compilation with !CONFIG_CACHE_L2X0 (and tested that it still
> works).
>
> - Replaced ktime_compare() with ktime_before() in the new driver,
> for consistency.
>
> v3: - Addressed review comments that were made by Jon Hunter to v2 by
> splitting patches into smaller (and simpler) chunks, better
> documenting changes in the commit messages and using proper error
> codes in the code.
>
> Warnings are replaced with a useful error messages in the code of
> "Introduce unified driver for NVIDIA Tegra SoCs" patch.
>
> Secondary CPUs parking timeout increased to 100ms because I found
> that it actually may happen to take more than 1ms if CPU is running
> on a *very* low frequency.
>
> Added diagnostic messages that are reporting Flow Controller state
> when CPU parking fails.
>
> Further polished cpuidle driver's code.
>
> The coupled state entering is now aborted if there is a pending SGI
> (Software Generated Interrupt) because it will be lost after GIC's
> power-cycling. Like it was done by the old Tegra20 CPUIDLE driver.
>
> v2: - Added patches to enable the new cpuidle driver in the defconfigs:
>
> ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
> ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
>
> - Dropped patches that removed CPUIDLE_FLAG_TIMER_STOP from the idling
> states because that flag actually doesn't have any negative effects,
> but still is correct for the case of a local CPU timer on older Tegra
> SoCs:
>
> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from Tegra114/124 idle-state
> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from all states
>
> - The "Add unified driver for NVIDIA Tegra SoCs" patch got more polish.
> Tegra30 and Terga114 states are now squashed into a single common C7
> state (following Parker TRM terminology, see 17.2.2.2 Power Management
> States), more comments added, etc minor changes.
It would be useful to switch the power state terminology to the one used
for later chips:
LP0 becomes SC7
LP1 becomes C1
LP2 becomes CC7
Meaning of these states is as follows
C is a core state:
C1 clock gating
C2 not defined
C3 not defined
C4 not defined
C5 not defined
C6 not defined for ARM cores
C7 power-gating
CC is a CPU cluster C state:
CC1 cluster clock gated
CC2 not defined
CC3 fmax@Vmin: not used prior to Tegra186
CC4: cluster retention: no longer supported
CC5: not defined
CC6: cluster power gating
CC7: cluster rail gating
SC is a System C state:
SC1: not defined
SC2: not defined
SC3: not defined
SC4: not defined
SC5: not defined
SC6: not defined
SC7: VDD_SOC off
Cheers,
Peter.
^ permalink raw reply [flat|nested] 28+ messages in thread* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-16 19:21 ` [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s) Peter De Schrijver
@ 2019-10-16 19:47 ` Dmitry Osipenko
2019-10-16 20:14 ` Dmitry Osipenko
0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-16 19:47 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
16.10.2019 22:21, Peter De Schrijver пишет:
> On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
>> Hello,
>>
>> This series does the following:
>>
>> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
>> into common drivers/cpuidle/ directory.
>>
>> 2. Enables CPU cluster power-down idling state on Tegra30.
>>
>> In the end there is a quite nice clean up of the Tegra CPUIDLE drivers
>> and of the Tegra's arch code in general. Please review, thanks!
>>
>> Changelog:
>>
>> v6: - Addressed request from Thierry Reding to change the way patches are
>> organized by making changes in a more incremental manner.
>>
>> - tegra_sleep_cpu() now checks for the secondary CPUs to be offline
>> in the "Make outer_disable() open-coded" patch.
>>
>> v5: - Rebased on a recent linux-next, fixed one minor conflict in Kconfig.
>>
>> - Improved commit's message of the "Support CPU cluster power-down state
>> on Tegra30" patch.
>>
>> - The "Support CPU cluster power-down state on Tegra30" patch is also
>> got split and now there is additional "Make outer_disable() open-coded"
>> patch.
>>
>> - Made minor cosmetic changes to the "Introduce unified driver for
>> NVIDIA Tegra SoCs" patch by improving error message and renaming
>> one variable.
>>
>> v4: - Fixed compilation with !CONFIG_CACHE_L2X0 (and tested that it still
>> works).
>>
>> - Replaced ktime_compare() with ktime_before() in the new driver,
>> for consistency.
>>
>> v3: - Addressed review comments that were made by Jon Hunter to v2 by
>> splitting patches into smaller (and simpler) chunks, better
>> documenting changes in the commit messages and using proper error
>> codes in the code.
>>
>> Warnings are replaced with a useful error messages in the code of
>> "Introduce unified driver for NVIDIA Tegra SoCs" patch.
>>
>> Secondary CPUs parking timeout increased to 100ms because I found
>> that it actually may happen to take more than 1ms if CPU is running
>> on a *very* low frequency.
>>
>> Added diagnostic messages that are reporting Flow Controller state
>> when CPU parking fails.
>>
>> Further polished cpuidle driver's code.
>>
>> The coupled state entering is now aborted if there is a pending SGI
>> (Software Generated Interrupt) because it will be lost after GIC's
>> power-cycling. Like it was done by the old Tegra20 CPUIDLE driver.
>>
>> v2: - Added patches to enable the new cpuidle driver in the defconfigs:
>>
>> ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
>> ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
>>
>> - Dropped patches that removed CPUIDLE_FLAG_TIMER_STOP from the idling
>> states because that flag actually doesn't have any negative effects,
>> but still is correct for the case of a local CPU timer on older Tegra
>> SoCs:
>>
>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from Tegra114/124 idle-state
>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from all states
>>
>> - The "Add unified driver for NVIDIA Tegra SoCs" patch got more polish.
>> Tegra30 and Terga114 states are now squashed into a single common C7
>> state (following Parker TRM terminology, see 17.2.2.2 Power Management
>> States), more comments added, etc minor changes.
>
> It would be useful to switch the power state terminology to the one used
> for later chips:
>
> LP0 becomes SC7
> LP1 becomes C1
> LP2 becomes CC7
>
> Meaning of these states is as follows
>
> C is a core state:
>
> C1 clock gating
> C2 not defined
> C3 not defined
> C4 not defined
> C5 not defined
> C6 not defined for ARM cores
> C7 power-gating
>
> CC is a CPU cluster C state:
>
> CC1 cluster clock gated
> CC2 not defined
> CC3 fmax@Vmin: not used prior to Tegra186
> CC4: cluster retention: no longer supported
> CC5: not defined
> CC6: cluster power gating
> CC7: cluster rail gating
>
> SC is a System C state:
>
> SC1: not defined
> SC2: not defined
> SC3: not defined
> SC4: not defined
> SC5: not defined
> SC6: not defined
> SC7: VDD_SOC off
Hello Peter,
But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
drivers/cpuidle/" and further patches. Am I missing something? Or do you
want the renaming to be a separate patch?
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-16 19:47 ` Dmitry Osipenko
@ 2019-10-16 20:14 ` Dmitry Osipenko
2019-10-28 14:04 ` Peter De Schrijver
0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-16 20:14 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
16.10.2019 22:47, Dmitry Osipenko пишет:
> 16.10.2019 22:21, Peter De Schrijver пишет:
>> On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
>>> Hello,
>>>
>>> This series does the following:
>>>
>>> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
>>> into common drivers/cpuidle/ directory.
>>>
>>> 2. Enables CPU cluster power-down idling state on Tegra30.
>>>
>>> In the end there is a quite nice clean up of the Tegra CPUIDLE drivers
>>> and of the Tegra's arch code in general. Please review, thanks!
>>>
>>> Changelog:
>>>
>>> v6: - Addressed request from Thierry Reding to change the way patches are
>>> organized by making changes in a more incremental manner.
>>>
>>> - tegra_sleep_cpu() now checks for the secondary CPUs to be offline
>>> in the "Make outer_disable() open-coded" patch.
>>>
>>> v5: - Rebased on a recent linux-next, fixed one minor conflict in Kconfig.
>>>
>>> - Improved commit's message of the "Support CPU cluster power-down state
>>> on Tegra30" patch.
>>>
>>> - The "Support CPU cluster power-down state on Tegra30" patch is also
>>> got split and now there is additional "Make outer_disable() open-coded"
>>> patch.
>>>
>>> - Made minor cosmetic changes to the "Introduce unified driver for
>>> NVIDIA Tegra SoCs" patch by improving error message and renaming
>>> one variable.
>>>
>>> v4: - Fixed compilation with !CONFIG_CACHE_L2X0 (and tested that it still
>>> works).
>>>
>>> - Replaced ktime_compare() with ktime_before() in the new driver,
>>> for consistency.
>>>
>>> v3: - Addressed review comments that were made by Jon Hunter to v2 by
>>> splitting patches into smaller (and simpler) chunks, better
>>> documenting changes in the commit messages and using proper error
>>> codes in the code.
>>>
>>> Warnings are replaced with a useful error messages in the code of
>>> "Introduce unified driver for NVIDIA Tegra SoCs" patch.
>>>
>>> Secondary CPUs parking timeout increased to 100ms because I found
>>> that it actually may happen to take more than 1ms if CPU is running
>>> on a *very* low frequency.
>>>
>>> Added diagnostic messages that are reporting Flow Controller state
>>> when CPU parking fails.
>>>
>>> Further polished cpuidle driver's code.
>>>
>>> The coupled state entering is now aborted if there is a pending SGI
>>> (Software Generated Interrupt) because it will be lost after GIC's
>>> power-cycling. Like it was done by the old Tegra20 CPUIDLE driver.
>>>
>>> v2: - Added patches to enable the new cpuidle driver in the defconfigs:
>>>
>>> ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
>>> ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
>>>
>>> - Dropped patches that removed CPUIDLE_FLAG_TIMER_STOP from the idling
>>> states because that flag actually doesn't have any negative effects,
>>> but still is correct for the case of a local CPU timer on older Tegra
>>> SoCs:
>>>
>>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from Tegra114/124 idle-state
>>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from all states
>>>
>>> - The "Add unified driver for NVIDIA Tegra SoCs" patch got more polish.
>>> Tegra30 and Terga114 states are now squashed into a single common C7
>>> state (following Parker TRM terminology, see 17.2.2.2 Power Management
>>> States), more comments added, etc minor changes.
>>
>> It would be useful to switch the power state terminology to the one used
>> for later chips:
>>
>> LP0 becomes SC7
>> LP1 becomes C1
>> LP2 becomes CC7
>>
>> Meaning of these states is as follows
>>
>> C is a core state:
>>
>> C1 clock gating
>> C2 not defined
>> C3 not defined
>> C4 not defined
>> C5 not defined
>> C6 not defined for ARM cores
>> C7 power-gating
>>
>> CC is a CPU cluster C state:
>>
>> CC1 cluster clock gated
>> CC2 not defined
>> CC3 fmax@Vmin: not used prior to Tegra186
>> CC4: cluster retention: no longer supported
>> CC5: not defined
>> CC6: cluster power gating
>> CC7: cluster rail gating
>>
>> SC is a System C state:
>>
>> SC1: not defined
>> SC2: not defined
>> SC3: not defined
>> SC4: not defined
>> SC5: not defined
>> SC6: not defined
>> SC7: VDD_SOC off
>
> Hello Peter,
>
> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
> drivers/cpuidle/" and further patches. Am I missing something? Or do you
> want the renaming to be a separate patch?
>
Or maybe you're suggesting to change the names everywhere and not only
in the cpuidle driver? Please clarify :)
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-16 20:14 ` Dmitry Osipenko
@ 2019-10-28 14:04 ` Peter De Schrijver
2019-10-29 0:47 ` Dmitry Osipenko
0 siblings, 1 reply; 28+ messages in thread
From: Peter De Schrijver @ 2019-10-28 14:04 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
On Wed, Oct 16, 2019 at 11:14:07PM +0300, Dmitry Osipenko wrote:
> 16.10.2019 22:47, Dmitry Osipenko пишет:
> > 16.10.2019 22:21, Peter De Schrijver пишет:
> >> On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
> >>> Hello,
> >>>
> >>> This series does the following:
> >>>
> >>> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
> >>> into common drivers/cpuidle/ directory.
> >>>
> >>> 2. Enables CPU cluster power-down idling state on Tegra30.
> >>>
> >>> In the end there is a quite nice clean up of the Tegra CPUIDLE drivers
> >>> and of the Tegra's arch code in general. Please review, thanks!
> >>>
> >>> Changelog:
> >>>
> >>> v6: - Addressed request from Thierry Reding to change the way patches are
> >>> organized by making changes in a more incremental manner.
> >>>
> >>> - tegra_sleep_cpu() now checks for the secondary CPUs to be offline
> >>> in the "Make outer_disable() open-coded" patch.
> >>>
> >>> v5: - Rebased on a recent linux-next, fixed one minor conflict in Kconfig.
> >>>
> >>> - Improved commit's message of the "Support CPU cluster power-down state
> >>> on Tegra30" patch.
> >>>
> >>> - The "Support CPU cluster power-down state on Tegra30" patch is also
> >>> got split and now there is additional "Make outer_disable() open-coded"
> >>> patch.
> >>>
> >>> - Made minor cosmetic changes to the "Introduce unified driver for
> >>> NVIDIA Tegra SoCs" patch by improving error message and renaming
> >>> one variable.
> >>>
> >>> v4: - Fixed compilation with !CONFIG_CACHE_L2X0 (and tested that it still
> >>> works).
> >>>
> >>> - Replaced ktime_compare() with ktime_before() in the new driver,
> >>> for consistency.
> >>>
> >>> v3: - Addressed review comments that were made by Jon Hunter to v2 by
> >>> splitting patches into smaller (and simpler) chunks, better
> >>> documenting changes in the commit messages and using proper error
> >>> codes in the code.
> >>>
> >>> Warnings are replaced with a useful error messages in the code of
> >>> "Introduce unified driver for NVIDIA Tegra SoCs" patch.
> >>>
> >>> Secondary CPUs parking timeout increased to 100ms because I found
> >>> that it actually may happen to take more than 1ms if CPU is running
> >>> on a *very* low frequency.
> >>>
> >>> Added diagnostic messages that are reporting Flow Controller state
> >>> when CPU parking fails.
> >>>
> >>> Further polished cpuidle driver's code.
> >>>
> >>> The coupled state entering is now aborted if there is a pending SGI
> >>> (Software Generated Interrupt) because it will be lost after GIC's
> >>> power-cycling. Like it was done by the old Tegra20 CPUIDLE driver.
> >>>
> >>> v2: - Added patches to enable the new cpuidle driver in the defconfigs:
> >>>
> >>> ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
> >>> ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
> >>>
> >>> - Dropped patches that removed CPUIDLE_FLAG_TIMER_STOP from the idling
> >>> states because that flag actually doesn't have any negative effects,
> >>> but still is correct for the case of a local CPU timer on older Tegra
> >>> SoCs:
> >>>
> >>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from Tegra114/124 idle-state
> >>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from all states
> >>>
> >>> - The "Add unified driver for NVIDIA Tegra SoCs" patch got more polish.
> >>> Tegra30 and Terga114 states are now squashed into a single common C7
> >>> state (following Parker TRM terminology, see 17.2.2.2 Power Management
> >>> States), more comments added, etc minor changes.
> >>
> >> It would be useful to switch the power state terminology to the one used
> >> for later chips:
> >>
> >> LP0 becomes SC7
> >> LP1 becomes C1
> >> LP2 becomes CC7
> >>
> >> Meaning of these states is as follows
> >>
> >> C is a core state:
> >>
> >> C1 clock gating
> >> C2 not defined
> >> C3 not defined
> >> C4 not defined
> >> C5 not defined
> >> C6 not defined for ARM cores
> >> C7 power-gating
> >>
> >> CC is a CPU cluster C state:
> >>
> >> CC1 cluster clock gated
> >> CC2 not defined
> >> CC3 fmax@Vmin: not used prior to Tegra186
> >> CC4: cluster retention: no longer supported
> >> CC5: not defined
> >> CC6: cluster power gating
> >> CC7: cluster rail gating
> >>
> >> SC is a System C state:
> >>
> >> SC1: not defined
> >> SC2: not defined
> >> SC3: not defined
> >> SC4: not defined
> >> SC5: not defined
> >> SC6: not defined
> >> SC7: VDD_SOC off
> >
> > Hello Peter,
> >
> > But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
> > please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
> > drivers/cpuidle/" and further patches. Am I missing something? Or do you
> > want the renaming to be a separate patch?
> >
>
> Or maybe you're suggesting to change the names everywhere and not only
> in the cpuidle driver? Please clarify :)
At least some of the variable and function names still say lp2?
Peter.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-28 14:04 ` Peter De Schrijver
@ 2019-10-29 0:47 ` Dmitry Osipenko
2019-11-01 12:33 ` Peter De Schrijver
0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Osipenko @ 2019-10-29 0:47 UTC (permalink / raw)
To: Peter De Schrijver, Thierry Reding, Jonathan Hunter
Cc: Rafael J. Wysocki, Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
28.10.2019 17:04, Peter De Schrijver пишет:
> On Wed, Oct 16, 2019 at 11:14:07PM +0300, Dmitry Osipenko wrote:
>> 16.10.2019 22:47, Dmitry Osipenko пишет:
>>> 16.10.2019 22:21, Peter De Schrijver пишет:
>>>> On Tue, Oct 15, 2019 at 07:59:57PM +0300, Dmitry Osipenko wrote:
>>>>> Hello,
>>>>>
>>>>> This series does the following:
>>>>>
>>>>> 1. Unifies Tegra20/30/114 drivers into a single driver and moves it out
>>>>> into common drivers/cpuidle/ directory.
>>>>>
>>>>> 2. Enables CPU cluster power-down idling state on Tegra30.
>>>>>
>>>>> In the end there is a quite nice clean up of the Tegra CPUIDLE drivers
>>>>> and of the Tegra's arch code in general. Please review, thanks!
>>>>>
>>>>> Changelog:
>>>>>
>>>>> v6: - Addressed request from Thierry Reding to change the way patches are
>>>>> organized by making changes in a more incremental manner.
>>>>>
>>>>> - tegra_sleep_cpu() now checks for the secondary CPUs to be offline
>>>>> in the "Make outer_disable() open-coded" patch.
>>>>>
>>>>> v5: - Rebased on a recent linux-next, fixed one minor conflict in Kconfig.
>>>>>
>>>>> - Improved commit's message of the "Support CPU cluster power-down state
>>>>> on Tegra30" patch.
>>>>>
>>>>> - The "Support CPU cluster power-down state on Tegra30" patch is also
>>>>> got split and now there is additional "Make outer_disable() open-coded"
>>>>> patch.
>>>>>
>>>>> - Made minor cosmetic changes to the "Introduce unified driver for
>>>>> NVIDIA Tegra SoCs" patch by improving error message and renaming
>>>>> one variable.
>>>>>
>>>>> v4: - Fixed compilation with !CONFIG_CACHE_L2X0 (and tested that it still
>>>>> works).
>>>>>
>>>>> - Replaced ktime_compare() with ktime_before() in the new driver,
>>>>> for consistency.
>>>>>
>>>>> v3: - Addressed review comments that were made by Jon Hunter to v2 by
>>>>> splitting patches into smaller (and simpler) chunks, better
>>>>> documenting changes in the commit messages and using proper error
>>>>> codes in the code.
>>>>>
>>>>> Warnings are replaced with a useful error messages in the code of
>>>>> "Introduce unified driver for NVIDIA Tegra SoCs" patch.
>>>>>
>>>>> Secondary CPUs parking timeout increased to 100ms because I found
>>>>> that it actually may happen to take more than 1ms if CPU is running
>>>>> on a *very* low frequency.
>>>>>
>>>>> Added diagnostic messages that are reporting Flow Controller state
>>>>> when CPU parking fails.
>>>>>
>>>>> Further polished cpuidle driver's code.
>>>>>
>>>>> The coupled state entering is now aborted if there is a pending SGI
>>>>> (Software Generated Interrupt) because it will be lost after GIC's
>>>>> power-cycling. Like it was done by the old Tegra20 CPUIDLE driver.
>>>>>
>>>>> v2: - Added patches to enable the new cpuidle driver in the defconfigs:
>>>>>
>>>>> ARM: multi_v7_defconfig: Enable Tegra cpuidle driver
>>>>> ARM: tegra: Enable Tegra cpuidle driver in tegra_defconfig
>>>>>
>>>>> - Dropped patches that removed CPUIDLE_FLAG_TIMER_STOP from the idling
>>>>> states because that flag actually doesn't have any negative effects,
>>>>> but still is correct for the case of a local CPU timer on older Tegra
>>>>> SoCs:
>>>>>
>>>>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from Tegra114/124 idle-state
>>>>> cpuidle: tegra: Remove CPUIDLE_FLAG_TIMER_STOP from all states
>>>>>
>>>>> - The "Add unified driver for NVIDIA Tegra SoCs" patch got more polish.
>>>>> Tegra30 and Terga114 states are now squashed into a single common C7
>>>>> state (following Parker TRM terminology, see 17.2.2.2 Power Management
>>>>> States), more comments added, etc minor changes.
>>>>
>>>> It would be useful to switch the power state terminology to the one used
>>>> for later chips:
>>>>
>>>> LP0 becomes SC7
>>>> LP1 becomes C1
>>>> LP2 becomes CC7
>>>>
>>>> Meaning of these states is as follows
>>>>
>>>> C is a core state:
>>>>
>>>> C1 clock gating
>>>> C2 not defined
>>>> C3 not defined
>>>> C4 not defined
>>>> C5 not defined
>>>> C6 not defined for ARM cores
>>>> C7 power-gating
>>>>
>>>> CC is a CPU cluster C state:
>>>>
>>>> CC1 cluster clock gated
>>>> CC2 not defined
>>>> CC3 fmax@Vmin: not used prior to Tegra186
>>>> CC4: cluster retention: no longer supported
>>>> CC5: not defined
>>>> CC6: cluster power gating
>>>> CC7: cluster rail gating
>>>>
>>>> SC is a System C state:
>>>>
>>>> SC1: not defined
>>>> SC2: not defined
>>>> SC3: not defined
>>>> SC4: not defined
>>>> SC5: not defined
>>>> SC6: not defined
>>>> SC7: VDD_SOC off
>>>
>>> Hello Peter,
>>>
>>> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
>>> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
>>> drivers/cpuidle/" and further patches. Am I missing something? Or do you
>>> want the renaming to be a separate patch?
>>>
>>
>> Or maybe you're suggesting to change the names everywhere and not only
>> in the cpuidle driver? Please clarify :)
>
> At least some of the variable and function names still say lp2?
The cpuidle driver uses LP2 terminology for everything that comes from
the external arch / firmware includes. But it says CC6 for everything
that is internal to the driver. So yes, there is a bit of new/old
terminology mixing in the code.
The arch code / PMC driver / TF firmware are all saying LP2. The LP2
naming is also a part of the device-tree binding.
It will be a lot of mess to rename the mach-tegra/pm.c code. I guess
eventually it could be moved to drivers/soc/, so maybe it will be better
to postpone the renaming until then?
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-10-29 0:47 ` Dmitry Osipenko
@ 2019-11-01 12:33 ` Peter De Schrijver
2019-11-01 13:22 ` Dmitry Osipenko
0 siblings, 1 reply; 28+ messages in thread
From: Peter De Schrijver @ 2019-11-01 12:33 UTC (permalink / raw)
To: Dmitry Osipenko
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
On Tue, Oct 29, 2019 at 03:47:56AM +0300, Dmitry Osipenko wrote:
..
> >>>> It would be useful to switch the power state terminology to the one used
> >>>> for later chips:
> >>>>
> >>>> LP0 becomes SC7
> >>>> LP1 becomes C1
> >>>> LP2 becomes CC7
> >>>>
> >>>> Meaning of these states is as follows
> >>>>
> >>>> C is a core state:
> >>>>
> >>>> C1 clock gating
> >>>> C2 not defined
> >>>> C3 not defined
> >>>> C4 not defined
> >>>> C5 not defined
> >>>> C6 not defined for ARM cores
> >>>> C7 power-gating
> >>>>
> >>>> CC is a CPU cluster C state:
> >>>>
> >>>> CC1 cluster clock gated
> >>>> CC2 not defined
> >>>> CC3 fmax@Vmin: not used prior to Tegra186
> >>>> CC4: cluster retention: no longer supported
> >>>> CC5: not defined
> >>>> CC6: cluster power gating
> >>>> CC7: cluster rail gating
> >>>>
> >>>> SC is a System C state:
> >>>>
> >>>> SC1: not defined
> >>>> SC2: not defined
> >>>> SC3: not defined
> >>>> SC4: not defined
> >>>> SC5: not defined
> >>>> SC6: not defined
> >>>> SC7: VDD_SOC off
> >>>
> >>> Hello Peter,
> >>>
> >>> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
> >>> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
> >>> drivers/cpuidle/" and further patches. Am I missing something? Or do you
> >>> want the renaming to be a separate patch?
> >>>
> >>
> >> Or maybe you're suggesting to change the names everywhere and not only
> >> in the cpuidle driver? Please clarify :)
> >
> > At least some of the variable and function names still say lp2?
>
> The cpuidle driver uses LP2 terminology for everything that comes from
> the external arch / firmware includes. But it says CC6 for everything
> that is internal to the driver. So yes, there is a bit of new/old
> terminology mixing in the code.
>
> The arch code / PMC driver / TF firmware are all saying LP2. The LP2
> naming is also a part of the device-tree binding.
>
> It will be a lot of mess to rename the mach-tegra/pm.c code. I guess
> eventually it could be moved to drivers/soc/, so maybe it will be better
> to postpone the renaming until then?
Or maybe add a comment somewhere indicating:
LP2 = CC6
LP1 = C1
LP0 = SC7
TF predates the new naming, so that may make some sense.
Peter.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-11-01 12:33 ` Peter De Schrijver
@ 2019-11-01 13:22 ` Dmitry Osipenko
2019-11-01 21:30 ` Dmitry Osipenko
0 siblings, 1 reply; 28+ messages in thread
From: Dmitry Osipenko @ 2019-11-01 13:22 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
01.11.2019 15:33, Peter De Schrijver пишет:
> On Tue, Oct 29, 2019 at 03:47:56AM +0300, Dmitry Osipenko wrote:
> ..
>
>>>>>> It would be useful to switch the power state terminology to the one used
>>>>>> for later chips:
>>>>>>
>>>>>> LP0 becomes SC7
>>>>>> LP1 becomes C1
>>>>>> LP2 becomes CC7
>>>>>>
>>>>>> Meaning of these states is as follows
>>>>>>
>>>>>> C is a core state:
>>>>>>
>>>>>> C1 clock gating
>>>>>> C2 not defined
>>>>>> C3 not defined
>>>>>> C4 not defined
>>>>>> C5 not defined
>>>>>> C6 not defined for ARM cores
>>>>>> C7 power-gating
>>>>>>
>>>>>> CC is a CPU cluster C state:
>>>>>>
>>>>>> CC1 cluster clock gated
>>>>>> CC2 not defined
>>>>>> CC3 fmax@Vmin: not used prior to Tegra186
>>>>>> CC4: cluster retention: no longer supported
>>>>>> CC5: not defined
>>>>>> CC6: cluster power gating
>>>>>> CC7: cluster rail gating
>>>>>>
>>>>>> SC is a System C state:
>>>>>>
>>>>>> SC1: not defined
>>>>>> SC2: not defined
>>>>>> SC3: not defined
>>>>>> SC4: not defined
>>>>>> SC5: not defined
>>>>>> SC6: not defined
>>>>>> SC7: VDD_SOC off
>>>>>
>>>>> Hello Peter,
>>>>>
>>>>> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
>>>>> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
>>>>> drivers/cpuidle/" and further patches. Am I missing something? Or do you
>>>>> want the renaming to be a separate patch?
>>>>>
>>>>
>>>> Or maybe you're suggesting to change the names everywhere and not only
>>>> in the cpuidle driver? Please clarify :)
>>>
>>> At least some of the variable and function names still say lp2?
>>
>> The cpuidle driver uses LP2 terminology for everything that comes from
>> the external arch / firmware includes. But it says CC6 for everything
>> that is internal to the driver. So yes, there is a bit of new/old
>> terminology mixing in the code.
>>
>> The arch code / PMC driver / TF firmware are all saying LP2. The LP2
>> naming is also a part of the device-tree binding.
>>
>> It will be a lot of mess to rename the mach-tegra/pm.c code. I guess
>> eventually it could be moved to drivers/soc/, so maybe it will be better
>> to postpone the renaming until then?
>
> Or maybe add a comment somewhere indicating:
>
> LP2 = CC6
> LP1 = C1
> LP0 = SC7
>
> TF predates the new naming, so that may make some sense.
Today it should make more sense just to add an explicit comment to the
cpuidle driver that clarifies the new naming (IMHO). I'll prepare v7
with that change.
Maybe later on, once more code will be consolidated in
drivers/soc/tegra/, it will become useful to duplicate the clarification
there as well.
Please let me know if you disagree or think that something better could
be done.
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v6 00/18] Consolidate and improve NVIDIA Tegra CPUIDLE driver(s)
2019-11-01 13:22 ` Dmitry Osipenko
@ 2019-11-01 21:30 ` Dmitry Osipenko
0 siblings, 0 replies; 28+ messages in thread
From: Dmitry Osipenko @ 2019-11-01 21:30 UTC (permalink / raw)
To: Peter De Schrijver
Cc: Thierry Reding, Jonathan Hunter, Rafael J. Wysocki,
Daniel Lezcano, linux-pm, linux-tegra, linux-kernel
01.11.2019 16:22, Dmitry Osipenko пишет:
> 01.11.2019 15:33, Peter De Schrijver пишет:
>> On Tue, Oct 29, 2019 at 03:47:56AM +0300, Dmitry Osipenko wrote:
>> ..
>>
>>>>>>> It would be useful to switch the power state terminology to the one used
>>>>>>> for later chips:
>>>>>>>
>>>>>>> LP0 becomes SC7
>>>>>>> LP1 becomes C1
>>>>>>> LP2 becomes CC7
>>>>>>>
>>>>>>> Meaning of these states is as follows
>>>>>>>
>>>>>>> C is a core state:
>>>>>>>
>>>>>>> C1 clock gating
>>>>>>> C2 not defined
>>>>>>> C3 not defined
>>>>>>> C4 not defined
>>>>>>> C5 not defined
>>>>>>> C6 not defined for ARM cores
>>>>>>> C7 power-gating
>>>>>>>
>>>>>>> CC is a CPU cluster C state:
>>>>>>>
>>>>>>> CC1 cluster clock gated
>>>>>>> CC2 not defined
>>>>>>> CC3 fmax@Vmin: not used prior to Tegra186
>>>>>>> CC4: cluster retention: no longer supported
>>>>>>> CC5: not defined
>>>>>>> CC6: cluster power gating
>>>>>>> CC7: cluster rail gating
>>>>>>>
>>>>>>> SC is a System C state:
>>>>>>>
>>>>>>> SC1: not defined
>>>>>>> SC2: not defined
>>>>>>> SC3: not defined
>>>>>>> SC4: not defined
>>>>>>> SC5: not defined
>>>>>>> SC6: not defined
>>>>>>> SC7: VDD_SOC off
>>>>>>
>>>>>> Hello Peter,
>>>>>>
>>>>>> But new "drivers/cpuidle/cpuidle-tegra.c" uses exactly that terminology,
>>>>>> please see "cpuidle: Refactor and move NVIDIA Tegra20 driver into
>>>>>> drivers/cpuidle/" and further patches. Am I missing something? Or do you
>>>>>> want the renaming to be a separate patch?
>>>>>>
>>>>>
>>>>> Or maybe you're suggesting to change the names everywhere and not only
>>>>> in the cpuidle driver? Please clarify :)
>>>>
>>>> At least some of the variable and function names still say lp2?
>>>
>>> The cpuidle driver uses LP2 terminology for everything that comes from
>>> the external arch / firmware includes. But it says CC6 for everything
>>> that is internal to the driver. So yes, there is a bit of new/old
>>> terminology mixing in the code.
>>>
>>> The arch code / PMC driver / TF firmware are all saying LP2. The LP2
>>> naming is also a part of the device-tree binding.
>>>
>>> It will be a lot of mess to rename the mach-tegra/pm.c code. I guess
>>> eventually it could be moved to drivers/soc/, so maybe it will be better
>>> to postpone the renaming until then?
>>
>> Or maybe add a comment somewhere indicating:
>>
>> LP2 = CC6
>> LP1 = C1
>> LP0 = SC7
>>
>> TF predates the new naming, so that may make some sense.
>
> Today it should make more sense just to add an explicit comment to the
> cpuidle driver that clarifies the new naming (IMHO). I'll prepare v7
> with that change.
>
> Maybe later on, once more code will be consolidated in
> drivers/soc/tegra/, it will become useful to duplicate the clarification
> there as well.
>
> Please let me know if you disagree or think that something better could
> be done.
BTW, LP3 = C1.
I don't think that the new terminology has equivalent to LP1 (CPU
cluster power gating + DRAM in self-refresh).
^ permalink raw reply [flat|nested] 28+ messages in thread