* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 13:42 Harry Pan
0 siblings, 0 replies; 4+ messages in thread
From: Harry Pan @ 2020-04-02 13:42 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 14:49 Harry Pan
0 siblings, 0 replies; 4+ messages in thread
From: Harry Pan @ 2020-04-02 14:49 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 14:48 Harry Pan
0 siblings, 0 replies; 4+ messages in thread
From: Harry Pan @ 2020-04-02 14:48 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH] perf/x86/cstate: Add Jasper Lake CPU support
@ 2020-04-02 11:07 Harry Pan
0 siblings, 0 replies; 4+ messages in thread
From: Harry Pan @ 2020-04-02 11:07 UTC (permalink / raw)
To: LKML
Cc: gs0622, Harry Pan, Alexander Shishkin, Arnaldo Carvalho de Melo,
Borislav Petkov, H. Peter Anvin, Ingo Molnar, Jiri Olsa,
Mark Rutland, Namhyung Kim, Peter Zijlstra, Thomas Gleixner, x86
Jasper Lake processor is Tremont microarchitecture, we can
reuse the glm_cstates table of Goldmont and Goldmont Plus
to enable the C-states residency profiling.
Signed-off-by: Harry Pan <harry.pan@intel.com>
---
arch/x86/events/intel/cstate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/events/intel/cstate.c b/arch/x86/events/intel/cstate.c
index e4aa20c0426f..442e1ed4acd4 100644
--- a/arch/x86/events/intel/cstate.c
+++ b/arch/x86/events/intel/cstate.c
@@ -643,6 +643,7 @@ static const struct x86_cpu_id intel_cstates_match[] __initconst = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT, &glm_cstates),
+ X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &glm_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_L, &icl_cstates),
X86_MATCH_INTEL_FAM6_MODEL(ICELAKE, &icl_cstates),
--
2.24.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
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