* [PATCH v6 1/5] cpufreq: blacklist SDM845 in cpufreq-dt-platdev
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
@ 2020-06-22 8:16 ` Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 2/5] cpufreq: blacklist SC7180 " Sibi Sankar
` (4 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Sibi Sankar @ 2020-06-22 8:16 UTC (permalink / raw)
To: viresh.kumar, sboyd, georgi.djakov, saravanak, mka
Cc: nm, bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty, Sibi Sankar
Add SDM845 to cpufreq-dt-platdev blacklist since the actual scaling is
handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v6/v7:
* No change
v5:
* Picked up R-b from Amit
v4:
* Updated commit message [Matthias]
* Picked up R-b from Matthias
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index e8e20fef400b0..be85eb494a6b3 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -132,6 +132,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "qcom,apq8096", },
{ .compatible = "qcom,msm8996", },
{ .compatible = "qcom,qcs404", },
+ { .compatible = "qcom,sdm845", },
{ .compatible = "st,stih407", },
{ .compatible = "st,stih410", },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 2/5] cpufreq: blacklist SC7180 in cpufreq-dt-platdev
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 1/5] cpufreq: blacklist SDM845 in cpufreq-dt-platdev Sibi Sankar
@ 2020-06-22 8:16 ` Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 3/5] OPP: Add and export helper to set bandwidth Sibi Sankar
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Sibi Sankar @ 2020-06-22 8:16 UTC (permalink / raw)
To: viresh.kumar, sboyd, georgi.djakov, saravanak, mka
Cc: nm, bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty, Sibi Sankar
Add SC7180 to cpufreq-dt-platdev blacklist since the actual scaling is
handled by the 'qcom-cpufreq-hw' driver.
Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v6/v7:
* No change
v5:
* Picked up R-b from Amit
v4:
* Updated commit message [Matthias]
* Picked up R-b from Matthias
drivers/cpufreq/cpufreq-dt-platdev.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index be85eb494a6b3..7d01df7bfa6cd 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -132,6 +132,7 @@ static const struct of_device_id blacklist[] __initconst = {
{ .compatible = "qcom,apq8096", },
{ .compatible = "qcom,msm8996", },
{ .compatible = "qcom,qcs404", },
+ { .compatible = "qcom,sc7180", },
{ .compatible = "qcom,sdm845", },
{ .compatible = "st,stih407", },
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 3/5] OPP: Add and export helper to set bandwidth
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 1/5] cpufreq: blacklist SDM845 in cpufreq-dt-platdev Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 2/5] cpufreq: blacklist SC7180 " Sibi Sankar
@ 2020-06-22 8:16 ` Sibi Sankar
2020-06-22 8:16 ` [PATCH v6 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change Sibi Sankar
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Sibi Sankar @ 2020-06-22 8:16 UTC (permalink / raw)
To: viresh.kumar, sboyd, georgi.djakov, saravanak, mka
Cc: nm, bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty, Sibi Sankar
Add and export 'dev_pm_opp_set_bw' to set the bandwidth
levels associated with an OPP.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v7:
* Picked up R-b from Matthias
v6:
* Pass NULL to _set_opp_bw
v5:
https://lkml.org/lkml/2020/5/27/7
* Rework the patch based on ^^
v4:
https://patchwork.kernel.org/patch/11019737/
* Pass device opp to set bw levels [Bjorn]
drivers/opp/core.c | 31 +++++++++++++++++++++++++++++++
include/linux/pm_opp.h | 6 ++++++
2 files changed, 37 insertions(+)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index 864cf4c65fff3..c9336aac74e91 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -831,6 +831,37 @@ static int _set_required_opps(struct device *dev,
return ret;
}
+/**
+ * dev_pm_opp_set_bw() - sets bandwidth levels corresponding to an opp
+ * @dev: device for which we do this operation
+ * @opp: opp based on which the bandwidth levels are to be configured
+ *
+ * This configures the bandwidth to the levels specified by the OPP. However
+ * if the OPP specified is NULL the bandwidth levels are cleared out.
+ *
+ * Return: 0 on success or a negative error value.
+ */
+int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp)
+{
+ struct opp_table *opp_table;
+ int ret;
+
+ opp_table = _find_opp_table(dev);
+ if (IS_ERR(opp_table)) {
+ dev_err(dev, "%s: device opp table doesn't exist\n", __func__);
+ return PTR_ERR(opp_table);
+ }
+
+ if (opp)
+ ret = _set_opp_bw(opp_table, opp, dev, false);
+ else
+ ret = _set_opp_bw(opp_table, NULL, dev, true);
+
+ dev_pm_opp_put_opp_table(opp_table);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(dev_pm_opp_set_bw);
+
/**
* dev_pm_opp_set_rate() - Configure new OPP based on frequency
* @dev: device for which we do this operation
diff --git a/include/linux/pm_opp.h b/include/linux/pm_opp.h
index d5c4a329321dd..ae68417c0ae00 100644
--- a/include/linux/pm_opp.h
+++ b/include/linux/pm_opp.h
@@ -151,6 +151,7 @@ struct opp_table *dev_pm_opp_attach_genpd(struct device *dev, const char **names
void dev_pm_opp_detach_genpd(struct opp_table *opp_table);
int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate);
int dev_pm_opp_set_rate(struct device *dev, unsigned long target_freq);
+int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp);
int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask);
int dev_pm_opp_get_sharing_cpus(struct device *cpu_dev, struct cpumask *cpumask);
void dev_pm_opp_remove_table(struct device *dev);
@@ -342,6 +343,11 @@ static inline int dev_pm_opp_set_rate(struct device *dev, unsigned long target_f
return -ENOTSUPP;
}
+static inline int dev_pm_opp_set_bw(struct device *dev, struct dev_pm_opp *opp)
+{
+ return -EOPNOTSUPP;
+}
+
static inline int dev_pm_opp_set_sharing_cpus(struct device *cpu_dev, const struct cpumask *cpumask)
{
return -ENOTSUPP;
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH v6 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
` (2 preceding siblings ...)
2020-06-22 8:16 ` [PATCH v6 3/5] OPP: Add and export helper to set bandwidth Sibi Sankar
@ 2020-06-22 8:16 ` Sibi Sankar
2020-06-22 15:58 ` Matthias Kaehlcke
2020-06-22 8:16 ` [PATCH v6 5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3 Sibi Sankar
2020-06-23 10:44 ` [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Viresh Kumar
5 siblings, 1 reply; 10+ messages in thread
From: Sibi Sankar @ 2020-06-22 8:16 UTC (permalink / raw)
To: viresh.kumar, sboyd, georgi.djakov, saravanak, mka
Cc: nm, bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty, Sibi Sankar
Add support to parse optional OPP table attached to the cpu node when
the OPP bandwidth values are populated. This allows for scaling of
DDR/L3 bandwidth levels with frequency change.
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v7:
* Fixup comments for correctness [Matthias]
* Initialize icc_scaling_enabled to false [Matthias]
* Make use of the increased per line character limit [Matthias]
v6:
* Add global flag to distinguish between voltage update and opp add.
Use the same flag before trying to scale ddr/l3 bw [Viresh]
* Use dev_pm_opp_find_freq_ceil to grab all opps [Viresh]
* Move dev_pm_opp_of_find_icc_paths into probe [Viresh]
v5:
* Use dev_pm_opp_adjust_voltage instead [Viresh]
* Misc cleanup
v4:
* Split fast switch disable into another patch [Lukasz]
drivers/cpufreq/qcom-cpufreq-hw.c | 83 ++++++++++++++++++++++++++++++-
1 file changed, 81 insertions(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index fc92a8842e252..aaf98333d37da 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -6,6 +6,7 @@
#include <linux/bitfield.h>
#include <linux/cpufreq.h>
#include <linux/init.h>
+#include <linux/interconnect.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/of_address.h>
@@ -30,6 +31,48 @@
static unsigned long cpu_hw_rate, xo_rate;
static struct platform_device *global_pdev;
+static bool icc_scaling_enabled;
+
+static int qcom_cpufreq_set_bw(struct cpufreq_policy *policy,
+ unsigned long freq_khz)
+{
+ unsigned long freq_hz = freq_khz * 1000;
+ struct dev_pm_opp *opp;
+ struct device *dev;
+ int ret;
+
+ dev = get_cpu_device(policy->cpu);
+ if (!dev)
+ return -ENODEV;
+
+ opp = dev_pm_opp_find_freq_exact(dev, freq_hz, true);
+ if (IS_ERR(opp))
+ return PTR_ERR(opp);
+
+ ret = dev_pm_opp_set_bw(dev, opp);
+ dev_pm_opp_put(opp);
+ return ret;
+}
+
+static int qcom_cpufreq_update_opp(struct device *cpu_dev,
+ unsigned long freq_khz,
+ unsigned long volt)
+{
+ unsigned long freq_hz = freq_khz * 1000;
+ int ret;
+
+ /* Skip voltage update if the opp table is not available */
+ if (!icc_scaling_enabled)
+ return dev_pm_opp_add(cpu_dev, freq_hz, volt);
+
+ ret = dev_pm_opp_adjust_voltage(cpu_dev, freq_hz, volt, volt, volt);
+ if (ret) {
+ dev_err(cpu_dev, "Voltage update failed freq=%ld\n", freq_khz);
+ return ret;
+ }
+
+ return dev_pm_opp_enable(cpu_dev, freq_hz);
+}
static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
unsigned int index)
@@ -39,6 +82,9 @@ static int qcom_cpufreq_hw_target_index(struct cpufreq_policy *policy,
writel_relaxed(index, perf_state_reg);
+ if (icc_scaling_enabled)
+ qcom_cpufreq_set_bw(policy, freq);
+
arch_set_freq_scale(policy->related_cpus, freq,
policy->cpuinfo.max_freq);
return 0;
@@ -89,11 +135,33 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
u32 data, src, lval, i, core_count, prev_freq = 0, freq;
u32 volt;
struct cpufreq_frequency_table *table;
+ struct dev_pm_opp *opp;
+ unsigned long rate;
+ int ret;
table = kcalloc(LUT_MAX_ENTRIES + 1, sizeof(*table), GFP_KERNEL);
if (!table)
return -ENOMEM;
+ ret = dev_pm_opp_of_add_table(cpu_dev);
+ if (!ret) {
+ /* Disable all opps and cross-validate against LUT later */
+ icc_scaling_enabled = true;
+ for (rate = 0; ; rate++) {
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, &rate);
+ if (IS_ERR(opp))
+ break;
+
+ dev_pm_opp_put(opp);
+ dev_pm_opp_disable(cpu_dev, rate);
+ }
+ } else if (ret != -ENODEV) {
+ dev_err(cpu_dev, "Invalid opp table in device tree\n");
+ return ret;
+ } else {
+ icc_scaling_enabled = false;
+ }
+
for (i = 0; i < LUT_MAX_ENTRIES; i++) {
data = readl_relaxed(base + REG_FREQ_LUT +
i * LUT_ROW_SIZE);
@@ -112,7 +180,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
if (freq != prev_freq && core_count != LUT_TURBO_IND) {
table[i].frequency = freq;
- dev_pm_opp_add(cpu_dev, freq * 1000, volt);
+ qcom_cpufreq_update_opp(cpu_dev, freq, volt);
dev_dbg(cpu_dev, "index=%d freq=%d, core_count %d\n", i,
freq, core_count);
} else if (core_count == LUT_TURBO_IND) {
@@ -133,7 +201,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
if (prev->frequency == CPUFREQ_ENTRY_INVALID) {
prev->frequency = prev_freq;
prev->flags = CPUFREQ_BOOST_FREQ;
- dev_pm_opp_add(cpu_dev, prev_freq * 1000, volt);
+ qcom_cpufreq_update_opp(cpu_dev, prev_freq, volt);
}
break;
@@ -254,6 +322,7 @@ static int qcom_cpufreq_hw_cpu_exit(struct cpufreq_policy *policy)
void __iomem *base = policy->driver_data - REG_PERF_STATE;
dev_pm_opp_remove_all_dynamic(cpu_dev);
+ dev_pm_opp_of_cpumask_remove_table(policy->related_cpus);
kfree(policy->freq_table);
devm_iounmap(&global_pdev->dev, base);
@@ -282,6 +351,7 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = {
static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
{
+ struct device *cpu_dev;
struct clk *clk;
int ret;
@@ -301,6 +371,15 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev)
global_pdev = pdev;
+ /* Check for optional interconnect paths on CPU0 */
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev)
+ return -EPROBE_DEFER;
+
+ ret = dev_pm_opp_of_find_icc_paths(cpu_dev, NULL);
+ if (ret)
+ return ret;
+
ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);
if (ret)
dev_err(&pdev->dev, "CPUFreq HW driver failed to register\n");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v6 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change
2020-06-22 8:16 ` [PATCH v6 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change Sibi Sankar
@ 2020-06-22 15:58 ` Matthias Kaehlcke
0 siblings, 0 replies; 10+ messages in thread
From: Matthias Kaehlcke @ 2020-06-22 15:58 UTC (permalink / raw)
To: Sibi Sankar
Cc: viresh.kumar, sboyd, georgi.djakov, saravanak, nm,
bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty
On Mon, Jun 22, 2020 at 01:46:48PM +0530, Sibi Sankar wrote:
> Add support to parse optional OPP table attached to the cpu node when
> the OPP bandwidth values are populated. This allows for scaling of
> DDR/L3 bandwidth levels with frequency change.
>
> Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v6 5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
` (3 preceding siblings ...)
2020-06-22 8:16 ` [PATCH v6 4/5] cpufreq: qcom: Update the bandwidth levels on frequency change Sibi Sankar
@ 2020-06-22 8:16 ` Sibi Sankar
2020-06-23 10:44 ` [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Viresh Kumar
5 siblings, 0 replies; 10+ messages in thread
From: Sibi Sankar @ 2020-06-22 8:16 UTC (permalink / raw)
To: viresh.kumar, sboyd, georgi.djakov, saravanak, mka
Cc: nm, bjorn.andersson, agross, rjw, linux-arm-msm, linux-kernel,
linux-pm, dianders, vincent.guittot, amit.kucheria, lukasz.luba,
sudeep.holla, smasetty, Sibi Sankar
Disable fast switch when the opp-tables required for scaling DDR/L3
are populated.
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
---
v7:
* Picked up R-b from Matthias
v6:
* No change
v5:
* Drop dev_pm_opp_get_path_count [Saravana]
drivers/cpufreq/qcom-cpufreq-hw.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c
index aaf98333d37da..fa68fa8ebd95e 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw.c
@@ -159,6 +159,7 @@ static int qcom_cpufreq_hw_read_lut(struct device *cpu_dev,
dev_err(cpu_dev, "Invalid opp table in device tree\n");
return ret;
} else {
+ policy->fast_switch_possible = true;
icc_scaling_enabled = false;
}
@@ -308,8 +309,6 @@ static int qcom_cpufreq_hw_cpu_init(struct cpufreq_policy *policy)
dev_pm_opp_of_register_em(policy->cpus);
- policy->fast_switch_possible = true;
-
return 0;
error:
devm_iounmap(dev, base);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs
2020-06-22 8:16 [PATCH v6 0/5] DDR/L3 Scaling support on SDM845 and SC7180 SoCs Sibi Sankar
` (4 preceding siblings ...)
2020-06-22 8:16 ` [PATCH v6 5/5] cpufreq: qcom: Disable fast switch when scaling DDR/L3 Sibi Sankar
@ 2020-06-23 10:44 ` Viresh Kumar
5 siblings, 0 replies; 10+ messages in thread
From: Viresh Kumar @ 2020-06-23 10:44 UTC (permalink / raw)
To: Sibi Sankar
Cc: sboyd, georgi.djakov, saravanak, mka, nm, bjorn.andersson,
agross, rjw, linux-arm-msm, linux-kernel, linux-pm, dianders,
vincent.guittot, amit.kucheria, lukasz.luba, sudeep.holla,
smasetty
On 22-06-20, 13:46, Sibi Sankar wrote:
> This patch series aims to extend cpu based scaling support to L3/DDR on
> SDM845 and SC7180 SoCs.
>
> Patches [1-2] - Blacklist SDM845 and SC7180 in cpufreq-dt-platdev
> Patches [3-5] - Update bw levels based on cpu frequency change
>
> V7:
> * Fixup comments for correctness [Matthias]
> * Initialize icc_scaling_enabled to false [Matthias]
> * Make use of the increased per line character limit [Matthias]
Applied. Thanks.
--
viresh
^ permalink raw reply [flat|nested] 10+ messages in thread