From: Vinod Koul <vkoul@kernel.org>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Cc: linux-kernel@vger.kernel.org,
Kishon Vijay Abraham I <kishon@ti.com>,
Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>,
Michal Simek <michal.simek@xilinx.com>
Subject: Re: [PATCH v8 2/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver
Date: Wed, 24 Jun 2020 20:41:21 +0530 [thread overview]
Message-ID: <20200624151121.GF2324254@vkoul-mobl> (raw)
In-Reply-To: <20200513172239.26444-3-laurent.pinchart@ideasonboard.com>
Hi Laurent,
Mostly this looks fine to me, some minor nitpicks below:
On 13-05-20, 20:22, Laurent Pinchart wrote:
> +config PHY_XILINX_ZYNQMP
> + tristate "Xilinx ZynqMP PHY driver"
> + depends on ARCH_ZYNQMP
Can we add COMPILE_TEST here so that this driver gets wider compile
coverage?
> +++ b/drivers/phy/xilinx/phy-zynqmp.c
> @@ -0,0 +1,995 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * phy-zynqmp.c - PHY driver for Xilinx ZynqMP GT.
> + *
> + * Copyright (C) 2018-20 Xilinx Inc.
2018-2020 please
> +/* Number of GT lanes */
> +#define NUM_LANES 4
Should this be coded in driver like this? Maybe future versions of
hardware will have more lanes..? Why not describe this in DT?
> +
> +/* SIOU SATA control register */
> +#define SATA_CONTROL_OFFSET 0x0100
> +
> +/* Total number of controllers */
> +#define CONTROLLERS_PER_LANE 5
Same question for this as well..
> +/*
> + * I/O Accessors
> + */
> +
> +static inline u32 xpsgtr_read(struct xpsgtr_dev *gtr_dev, u32 reg)
> +{
> + return readl(gtr_dev->serdes + reg);
> +}
> +
> +static inline void xpsgtr_write(struct xpsgtr_dev *gtr_dev, u32 reg, u32 value)
> +{
> + writel(value, gtr_dev->serdes + reg);
> +}
> +
> +static inline void xpsgtr_clr_set(struct xpsgtr_dev *gtr_dev, u32 reg,
> + u32 clr, u32 set)
wouldn't it be apt to rename this to xpsgtr_modify() and with args as
value and mask, somehow I find that more simpler...
Also, please align second line with opening brace of preceding line
--
~Vinod
next prev parent reply other threads:[~2020-06-24 15:11 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 17:22 [PATCH v8 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY Laurent Pinchart
2020-05-19 8:29 ` Kishon Vijay Abraham I
2020-05-26 18:32 ` Rob Herring
2020-05-28 1:55 ` Laurent Pinchart
2020-06-10 17:05 ` Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 2/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-06-24 15:11 ` Vinod Koul [this message]
2020-06-24 16:39 ` Laurent Pinchart
2020-06-24 17:26 ` Vinod Koul
2020-06-24 21:14 ` Laurent Pinchart
2020-06-25 6:39 ` Michal Simek
2020-06-24 16:44 ` [PATCH v8.1 " Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 3/3] arm64: dts: zynqmp: Add GTR transceivers Laurent Pinchart
2020-06-29 9:39 ` [PATCH v8 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Vinod Koul
2020-06-29 12:02 ` Laurent Pinchart
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