From: Kishon Vijay Abraham I <kishon@ti.com>
To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
<linux-kernel@vger.kernel.org>
Cc: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>,
Michal Simek <michal.simek@xilinx.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh@kernel.org>,
<devicetree@vger.kernel.org>
Subject: Re: [PATCH v8 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY
Date: Tue, 19 May 2020 13:59:05 +0530 [thread overview]
Message-ID: <eaeba80e-9082-2eeb-8c66-7ef28b7fb895@ti.com> (raw)
In-Reply-To: <20200513172239.26444-2-laurent.pinchart@ideasonboard.com>
On 5/13/2020 10:52 PM, Laurent Pinchart wrote:
> From: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
>
> Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed
> Processing System Gigabit Transceiver which provides PHY capabilities to
> USB, SATA, PCIE, Display Port and Ehernet SGMII controllers.
>
> Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com>
> Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Need RobH Ack for this to be merged.
Thanks
Kishon
> ---
> Changes since v7:
>
> - Switch to GPL-2.0-only OR BSD-2-Clause
>
> Changes since v6:
>
> - Fixed specification of compatible-dependent xlnx,tx-termination-fix
> property
> - Dropped status property from example
> - Use 4 spaces to indent example
>
> Changes since v5:
>
> - Document clocks and clock-names properties
> - Document resets and reset-names properties
> - Replace subnodes with an additional entry in the PHY cells
> - Drop lane frequency PHY cell, replaced by reference clock phandle
> - Convert bindings to YAML
> - Reword the subject line
> - Drop Rob's R-b as the bindings have significantly changed
> - Drop resets and reset-names properties
> ---
> .../bindings/phy/xlnx,zynqmp-psgtr.yaml | 105 ++++++++++++++++++
> include/dt-bindings/phy/phy.h | 1 +
> 2 files changed, 106 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> new file mode 100644
> index 000000000000..09e3cde7ebca
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/xlnx,zynqmp-psgtr.yaml
> @@ -0,0 +1,105 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
> +
> +maintainers:
> + - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> +
> +description: |
> + This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
> + GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
> + Ethernet SGMII controllers.
> +
> +properties:
> + "#phy-cells":
> + const: 4
> + description: |
> + The cells contain the following arguments.
> +
> + - description: The GTR lane
> + minimum: 0
> + maximum: 3
> + - description: The PHY type
> + enum:
> + - PHY_TYPE_DP
> + - PHY_TYPE_PCIE
> + - PHY_TYPE_SATA
> + - PHY_TYPE_SGMII
> + - PHY_TYPE_USB
> + - description: The PHY instance
> + minimum: 0
> + maximum: 1 # for DP, SATA or USB
> + maximum: 3 # for PCIE or SGMII
> + - description: The reference clock number
> + minimum: 0
> + maximum: 3
> +
> + compatible:
> + enum:
> + - xlnx,zynqmp-psgtr-v1.1
> + - xlnx,zynqmp-psgtr
> +
> + clocks:
> + minItems: 1
> + maxItems: 4
> + description: |
> + Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
> + inputs shall not have an entry.
> +
> + clock-names:
> + minItems: 1
> + maxItems: 4
> + items:
> + pattern: "^ref[0-3]$"
> +
> + reg:
> + items:
> + - description: SERDES registers block
> + - description: SIOU registers block
> +
> + reg-names:
> + items:
> + - const: serdes
> + - const: siou
> +
> + xlnx,tx-termination-fix:
> + description: |
> + Include this for fixing functional issue with the TX termination
> + resistance in GT, which can be out of spec for the XCZU9EG silicon
> + version.
> + type: boolean
> +
> +required:
> + - "#phy-cells"
> + - compatible
> + - reg
> + - reg-names
> +
> +if:
> + properties:
> + compatible:
> + const: xlnx,zynqmp-psgtr-v1.1
> +
> +then:
> + properties:
> + xlnx,tx-termination-fix: false
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + phy: phy@fd400000 {
> + compatible = "xlnx,zynqmp-psgtr-v1.1";
> + reg = <0x0 0xfd400000 0x0 0x40000>,
> + <0x0 0xfd3d0000 0x0 0x1000>;
> + reg-names = "serdes", "siou";
> + clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
> + clock-names = "ref1", "ref2", "ref3";
> + #phy-cells = <4>;
> + };
> +
> +...
> diff --git a/include/dt-bindings/phy/phy.h b/include/dt-bindings/phy/phy.h
> index 1f3f866fae7b..f6bc83b66ae9 100644
> --- a/include/dt-bindings/phy/phy.h
> +++ b/include/dt-bindings/phy/phy.h
> @@ -17,5 +17,6 @@
> #define PHY_TYPE_USB3 4
> #define PHY_TYPE_UFS 5
> #define PHY_TYPE_DP 6
> +#define PHY_TYPE_SGMII 7
>
> #endif /* _DT_BINDINGS_PHY */
>
next prev parent reply other threads:[~2020-05-19 8:29 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 17:22 [PATCH v8 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 1/3] dt-bindings: phy: Add DT bindings for Xilinx ZynqMP PSGTR PHY Laurent Pinchart
2020-05-19 8:29 ` Kishon Vijay Abraham I [this message]
2020-05-26 18:32 ` Rob Herring
2020-05-28 1:55 ` Laurent Pinchart
2020-06-10 17:05 ` Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 2/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Laurent Pinchart
2020-06-24 15:11 ` Vinod Koul
2020-06-24 16:39 ` Laurent Pinchart
2020-06-24 17:26 ` Vinod Koul
2020-06-24 21:14 ` Laurent Pinchart
2020-06-25 6:39 ` Michal Simek
2020-06-24 16:44 ` [PATCH v8.1 " Laurent Pinchart
2020-05-13 17:22 ` [PATCH v8 3/3] arm64: dts: zynqmp: Add GTR transceivers Laurent Pinchart
2020-06-29 9:39 ` [PATCH v8 0/3] phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver Vinod Koul
2020-06-29 12:02 ` Laurent Pinchart
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