* [PATCH] drm/msm/gpu: make ringbuffer readonly
@ 2020-08-17 16:23 Rob Clark
2020-08-17 17:10 ` Jordan Crouse
0 siblings, 1 reply; 2+ messages in thread
From: Rob Clark @ 2020-08-17 16:23 UTC (permalink / raw)
To: dri-devel
Cc: Jordan Crouse, Rob Clark, Rob Clark, Sean Paul, David Airlie,
Daniel Vetter, open list:DRM DRIVER FOR MSM ADRENO GPU,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list
From: Rob Clark <robdclark@chromium.org>
The GPU has no business writing into the ringbuffer, let's make it
readonly to the GPU.
Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support")
Signed-off-by: Rob Clark <robdclark@chromium.org>
---
drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
index e397c44cc011..39ecb5a18431 100644
--- a/drivers/gpu/drm/msm/msm_ringbuffer.c
+++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
@@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
ring->id = id;
ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
- MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova);
+ MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
+ &ring->iova);
if (IS_ERR(ring->start)) {
ret = PTR_ERR(ring->start);
--
2.26.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] drm/msm/gpu: make ringbuffer readonly
2020-08-17 16:23 [PATCH] drm/msm/gpu: make ringbuffer readonly Rob Clark
@ 2020-08-17 17:10 ` Jordan Crouse
0 siblings, 0 replies; 2+ messages in thread
From: Jordan Crouse @ 2020-08-17 17:10 UTC (permalink / raw)
To: Rob Clark
Cc: dri-devel, Rob Clark, Sean Paul, David Airlie, Daniel Vetter,
open list:DRM DRIVER FOR MSM ADRENO GPU,
open list:DRM DRIVER FOR MSM ADRENO GPU, open list
On Mon, Aug 17, 2020 at 09:23:09AM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
>
> The GPU has no business writing into the ringbuffer, let's make it
> readonly to the GPU.
Yep. There are some additional things we can do in the a6xx family to make this
even more robust but for the vast majority of targets out in this world this is
a good and necessary fix.
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
> Fixes: 7198e6b03155 ("drm/msm: add a3xx gpu support")
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
> drivers/gpu/drm/msm/msm_ringbuffer.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_ringbuffer.c b/drivers/gpu/drm/msm/msm_ringbuffer.c
> index e397c44cc011..39ecb5a18431 100644
> --- a/drivers/gpu/drm/msm/msm_ringbuffer.c
> +++ b/drivers/gpu/drm/msm/msm_ringbuffer.c
> @@ -27,7 +27,8 @@ struct msm_ringbuffer *msm_ringbuffer_new(struct msm_gpu *gpu, int id,
> ring->id = id;
>
> ring->start = msm_gem_kernel_new(gpu->dev, MSM_GPU_RINGBUFFER_SZ,
> - MSM_BO_WC, gpu->aspace, &ring->bo, &ring->iova);
> + MSM_BO_WC | MSM_BO_GPU_READONLY, gpu->aspace, &ring->bo,
> + &ring->iova);
>
> if (IS_ERR(ring->start)) {
> ret = PTR_ERR(ring->start);
> --
> 2.26.2
>
--
The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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