From: Joerg Roedel <joro@8bytes.org>
To: x86@kernel.org
Cc: Joerg Roedel <joro@8bytes.org>, Joerg Roedel <jroedel@suse.de>,
hpa@zytor.com, Andy Lutomirski <luto@kernel.org>,
Dave Hansen <dave.hansen@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Jiri Slaby <jslaby@suse.cz>,
Dan Williams <dan.j.williams@intel.com>,
Tom Lendacky <thomas.lendacky@amd.com>,
Juergen Gross <jgross@suse.com>,
Kees Cook <keescook@chromium.org>,
David Rientjes <rientjes@google.com>,
Cfir Cohen <cfir@google.com>, Erdem Aktas <erdemaktas@google.com>,
Masami Hiramatsu <mhiramat@kernel.org>,
Mike Stunes <mstunes@vmware.com>,
Sean Christopherson <sean.j.christopherson@intel.com>,
Martin Radev <martin.b.radev@gmail.com>,
linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
virtualization@lists.linux-foundation.org
Subject: [PATCH v6 09/76] x86/umip: Factor out instruction decoding
Date: Mon, 24 Aug 2020 10:54:04 +0200 [thread overview]
Message-ID: <20200824085511.7553-10-joro@8bytes.org> (raw)
In-Reply-To: <20200824085511.7553-1-joro@8bytes.org>
From: Joerg Roedel <jroedel@suse.de>
Factor out the code used to decode an instruction with the correct
address and operand sizes to a helper function.
No functional changes.
Signed-off-by: Joerg Roedel <jroedel@suse.de>
Link: https://lore.kernel.org/r/20200724160336.5435-9-joro@8bytes.org
---
arch/x86/include/asm/insn-eval.h | 2 ++
arch/x86/kernel/umip.c | 23 +---------------
arch/x86/lib/insn-eval.c | 45 ++++++++++++++++++++++++++++++++
3 files changed, 48 insertions(+), 22 deletions(-)
diff --git a/arch/x86/include/asm/insn-eval.h b/arch/x86/include/asm/insn-eval.h
index b8b9ef1bbd06..392b4fe377f9 100644
--- a/arch/x86/include/asm/insn-eval.h
+++ b/arch/x86/include/asm/insn-eval.h
@@ -21,5 +21,7 @@ unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx);
int insn_get_code_seg_params(struct pt_regs *regs);
int insn_fetch_from_user(struct pt_regs *regs,
unsigned char buf[MAX_INSN_SIZE]);
+bool insn_decode(struct insn *insn, struct pt_regs *regs,
+ unsigned char buf[MAX_INSN_SIZE], int buf_size);
#endif /* _ASM_X86_INSN_EVAL_H */
diff --git a/arch/x86/kernel/umip.c b/arch/x86/kernel/umip.c
index ad135be4f1f0..f6225bf22c02 100644
--- a/arch/x86/kernel/umip.c
+++ b/arch/x86/kernel/umip.c
@@ -342,7 +342,6 @@ bool fixup_umip_exception(struct pt_regs *regs)
unsigned long *reg_addr;
void __user *uaddr;
struct insn insn;
- int seg_defs;
if (!regs)
return false;
@@ -357,27 +356,7 @@ bool fixup_umip_exception(struct pt_regs *regs)
if (!nr_copied)
return false;
- insn_init(&insn, buf, nr_copied, user_64bit_mode(regs));
-
- /*
- * Override the default operand and address sizes with what is specified
- * in the code segment descriptor. The instruction decoder only sets
- * the address size it to either 4 or 8 address bytes and does nothing
- * for the operand bytes. This OK for most of the cases, but we could
- * have special cases where, for instance, a 16-bit code segment
- * descriptor is used.
- * If there is an address override prefix, the instruction decoder
- * correctly updates these values, even for 16-bit defaults.
- */
- seg_defs = insn_get_code_seg_params(regs);
- if (seg_defs == -EINVAL)
- return false;
-
- insn.addr_bytes = INSN_CODE_SEG_ADDR_SZ(seg_defs);
- insn.opnd_bytes = INSN_CODE_SEG_OPND_SZ(seg_defs);
-
- insn_get_length(&insn);
- if (nr_copied < insn.length)
+ if (!insn_decode(&insn, regs, buf, nr_copied))
return false;
umip_inst = identify_insn(&insn);
diff --git a/arch/x86/lib/insn-eval.c b/arch/x86/lib/insn-eval.c
index 0c4f7ebc261b..f52046f90dd3 100644
--- a/arch/x86/lib/insn-eval.c
+++ b/arch/x86/lib/insn-eval.c
@@ -1407,3 +1407,48 @@ int insn_fetch_from_user(struct pt_regs *regs, unsigned char buf[MAX_INSN_SIZE])
return MAX_INSN_SIZE - not_copied;
}
+
+/**
+ * insn_decode() - Decode an instruction
+ * @insn: Structure to store decoded instruction
+ * @regs: Structure with register values as seen when entering kernel mode
+ * @buf: Buffer containing the instruction bytes
+ * @buf_size: Number of instruction bytes available in buf
+ *
+ * Decodes the instruction provided in buf and stores the decoding results in
+ * insn. Also determines the correct address and operand sizes.
+ *
+ * Returns:
+ *
+ * True if instruction was decoded, False otherwise.
+ */
+bool insn_decode(struct insn *insn, struct pt_regs *regs,
+ unsigned char buf[MAX_INSN_SIZE], int buf_size)
+{
+ int seg_defs;
+
+ insn_init(insn, buf, buf_size, user_64bit_mode(regs));
+
+ /*
+ * Override the default operand and address sizes with what is specified
+ * in the code segment descriptor. The instruction decoder only sets
+ * the address size it to either 4 or 8 address bytes and does nothing
+ * for the operand bytes. This OK for most of the cases, but we could
+ * have special cases where, for instance, a 16-bit code segment
+ * descriptor is used.
+ * If there is an address override prefix, the instruction decoder
+ * correctly updates these values, even for 16-bit defaults.
+ */
+ seg_defs = insn_get_code_seg_params(regs);
+ if (seg_defs == -EINVAL)
+ return false;
+
+ insn->addr_bytes = INSN_CODE_SEG_ADDR_SZ(seg_defs);
+ insn->opnd_bytes = INSN_CODE_SEG_OPND_SZ(seg_defs);
+
+ insn_get_length(insn);
+ if (buf_size < insn->length)
+ return false;
+
+ return true;
+}
--
2.28.0
next prev parent reply other threads:[~2020-08-24 9:17 UTC|newest]
Thread overview: 116+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-24 8:53 [PATCH v6 00/76] x86: SEV-ES Guest Support Joerg Roedel
2020-08-24 8:53 ` [PATCH v6 01/76] KVM: SVM: nested: Don't allocate VMCB structures on stack Joerg Roedel
2020-08-24 8:53 ` [PATCH v6 02/76] KVM: SVM: Add GHCB definitions Joerg Roedel
2020-08-24 10:44 ` Borislav Petkov
2020-08-25 9:22 ` Joerg Roedel
2020-08-25 11:04 ` Borislav Petkov
2020-08-27 16:01 ` Arvind Sankar
2020-08-28 11:54 ` Joerg Roedel
2020-08-24 8:53 ` [PATCH v6 03/76] KVM: SVM: Add GHCB Accessor functions Joerg Roedel
2020-08-24 8:53 ` [PATCH v6 04/76] KVM: SVM: Use __packed shorthand Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 05/76] x86/cpufeatures: Add SEV-ES CPU feature Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 06/76] x86/traps: Move pf error codes to <asm/trap_pf.h> Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 07/76] x86/insn: Make inat-tables.c suitable for pre-decompression code Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 08/76] x86/umip: Factor out instruction fetch Joerg Roedel
2020-08-24 8:54 ` Joerg Roedel [this message]
2020-08-24 8:54 ` [PATCH v6 10/76] x86/insn: Add insn_get_modrm_reg_off() Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 11/76] x86/insn: Add insn_has_rep_prefix() helper Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 12/76] x86/boot/compressed/64: Disable red-zone usage Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 13/76] x86/boot/compressed/64: Add IDT Infrastructure Joerg Roedel
2020-08-27 15:26 ` Arvind Sankar
2020-08-28 12:12 ` Joerg Roedel
2020-08-28 15:09 ` Arvind Sankar
2020-08-24 8:54 ` [PATCH v6 14/76] x86/boot/compressed/64: Rename kaslr_64.c to ident_map_64.c Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 15/76] x86/boot/compressed/64: Add page-fault handler Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 16/76] x86/boot/compressed/64: Always switch to own page-table Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 17/76] x86/boot/compressed/64: Don't pre-map memory in KASLR code Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 18/76] x86/boot/compressed/64: Change add_identity_map() to take start and end Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 19/76] x86/boot/compressed/64: Add stage1 #VC handler Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 20/76] x86/boot/compressed/64: Call set_sev_encryption_mask earlier Joerg Roedel
2020-08-27 9:36 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 21/76] x86/boot/compressed/64: Check return value of kernel_ident_mapping_init() Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 22/76] x86/boot/compressed/64: Add set_page_en/decrypted() helpers Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 23/76] x86/boot/compressed/64: Setup GHCB Based VC Exception handler Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 24/76] x86/boot/compressed/64: Unmap GHCB page before booting the kernel Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 25/76] x86/sev-es: Add support for handling IOIO exceptions Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 26/76] x86/fpu: Move xgetbv()/xsetbv() into separate header Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler Joerg Roedel
2020-08-27 22:48 ` Arvind Sankar
2020-08-28 12:33 ` Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 28/76] x86/idt: Move IDT to data segment Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 29/76] x86/idt: Split idt_data setup out of set_intr_gate() Joerg Roedel
2020-08-28 15:16 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 30/76] x86/head/64: Install startup GDT Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 31/76] x86/head/64: Setup MSR_GS_BASE before calling into C code Joerg Roedel
2020-08-28 18:13 ` Borislav Petkov
2020-09-01 12:09 ` Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 32/76] x86/head/64: Load GDT after switch to virtual addresses Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 33/76] x86/head/64: Load segment registers earlier Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 34/76] x86/head/64: Switch to initial stack earlier Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 35/76] x86/head/64: Make fixup_pointer() static inline Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 36/76] x86/head/64: Load IDT earlier Joerg Roedel
2020-08-29 10:24 ` Borislav Petkov
2020-09-01 12:13 ` Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 37/76] x86/head/64: Move early exception dispatch to C code Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early Joerg Roedel
2020-08-29 15:55 ` Borislav Petkov
2020-08-31 8:58 ` Joerg Roedel
2020-08-31 9:26 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 39/76] x86/sev-es: Add SEV-ES Feature Detection Joerg Roedel
2020-08-29 16:25 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 40/76] x86/sev-es: Print SEV-ES info into kernel log Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 41/76] x86/sev-es: Compile early handler code into kernel image Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 42/76] x86/sev-es: Setup early #VC handler Joerg Roedel
2020-08-31 9:45 ` Borislav Petkov
2020-09-01 12:59 ` Joerg Roedel
2020-09-01 13:35 ` Borislav Petkov
2021-09-04 9:39 ` Lai Jiangshan
2021-09-06 5:07 ` Juergen Gross
2020-08-24 8:54 ` [PATCH v6 43/76] x86/sev-es: Setup GHCB based boot " Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 44/76] x86/sev-es: Setup per-cpu GHCBs for the runtime handler Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 45/76] x86/sev-es: Allocate and Map IST stack for #VC handler Joerg Roedel
2020-08-31 10:27 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 46/76] x86/sev-es: Adjust #VC IST Stack on entering NMI handler Joerg Roedel
2020-08-31 11:05 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 47/76] x86/dumpstack/64: Add noinstr version of get_stack_info() Joerg Roedel
2020-08-31 11:11 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 48/76] x86/entry/64: Add entry code for #VC handler Joerg Roedel
2020-08-31 11:30 ` Borislav Petkov
2020-09-01 13:29 ` Joerg Roedel
2020-08-31 17:30 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 49/76] x86/sev-es: Add Runtime #VC Exception Handler Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 50/76] x86/sev-es: Wire up existing #VC exit-code handlers Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 51/76] x86/sev-es: Handle instruction fetches from user-space Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 52/76] x86/sev-es: Handle MMIO events Joerg Roedel
2020-08-31 15:47 ` Borislav Petkov
2020-08-24 8:54 ` [PATCH v6 53/76] x86/sev-es: Handle MMIO String Instructions Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 54/76] x86/sev-es: Handle MSR events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 55/76] x86/sev-es: Handle DR7 read/write events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 56/76] x86/sev-es: Handle WBINVD Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 57/76] x86/sev-es: Handle RDTSC(P) Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 58/76] x86/sev-es: Handle RDPMC Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 59/76] x86/sev-es: Handle INVD Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 60/76] x86/sev-es: Handle MONITOR/MONITORX Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 61/76] x86/sev-es: Handle MWAIT/MWAITX Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 62/76] x86/sev-es: Handle VMMCALL Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 63/76] x86/sev-es: Handle #AC Events Joerg Roedel
2020-08-24 8:54 ` [PATCH v6 64/76] x86/sev-es: Handle #DB Events Joerg Roedel
2020-08-31 16:19 ` Borislav Petkov
2020-08-24 8:55 ` [PATCH v6 65/76] x86/paravirt: Allow hypervisor specific VMMCALL handling under SEV-ES Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 66/76] x86/kvm: Add KVM " Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 67/76] x86/vmware: Add VMware specific handling for VMMCALL " Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 68/76] x86/realmode: Add SEV-ES specific trampoline entry point Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 69/76] x86/realmode: Setup AP jump table Joerg Roedel
2020-08-31 17:09 ` Borislav Petkov
2020-09-01 13:55 ` Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 70/76] x86/smpboot: Setup TSS for starting AP Joerg Roedel
2020-08-31 17:25 ` Borislav Petkov
2020-08-24 8:55 ` [PATCH v6 71/76] x86/head/64: Don't call verify_cpu() on starting APs Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 72/76] x86/head/64: Rename start_cpu0 Joerg Roedel
2020-08-31 17:29 ` Borislav Petkov
2020-08-24 8:55 ` [PATCH v6 73/76] x86/sev-es: Support CPU offline/online Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 74/76] x86/sev-es: Handle NMI State Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 75/76] x86/efi: Add GHCB mappings when SEV-ES is active Joerg Roedel
2020-08-24 8:55 ` [PATCH v6 76/76] x86/sev-es: Check required CPU features for SEV-ES Joerg Roedel
2020-08-25 0:21 ` [PATCH v6 00/76] x86: SEV-ES Guest Support Mike Stunes
2020-08-25 6:24 ` Joerg Roedel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200824085511.7553-10-joro@8bytes.org \
--to=joro@8bytes.org \
--cc=cfir@google.com \
--cc=dan.j.williams@intel.com \
--cc=dave.hansen@linux.intel.com \
--cc=erdemaktas@google.com \
--cc=hpa@zytor.com \
--cc=jgross@suse.com \
--cc=jroedel@suse.de \
--cc=jslaby@suse.cz \
--cc=keescook@chromium.org \
--cc=kvm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@kernel.org \
--cc=martin.b.radev@gmail.com \
--cc=mhiramat@kernel.org \
--cc=mstunes@vmware.com \
--cc=peterz@infradead.org \
--cc=rientjes@google.com \
--cc=sean.j.christopherson@intel.com \
--cc=thomas.lendacky@amd.com \
--cc=virtualization@lists.linux-foundation.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).