* [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-15 15:34 ` Rob Herring
2020-09-07 8:18 ` [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
` (4 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel, devicetree; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
The Amlogic AXG SoC family has a downgraded VPU supporting only MIPI-DSI output
after it's ENCL DPI encoder output.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../bindings/display/amlogic,meson-vpu.yaml | 36 +++++++++++++++++--
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
index a8d202c9d004..e2e7d99d8ace 100644
--- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
@@ -31,8 +31,10 @@ description: |
The Video Input Unit is in charge of the pixel scanout from the DDR memory.
It fetches the frames addresses, stride and parameters from the "Canvas" memory.
+ On the AXG family, the Video Input Unit direclty reads from DDR memory.
This part is also in charge of the CSC (Colorspace Conversion).
It can handle 2 OSD Planes and 2 Video Planes.
+ On the AXG family, only a single OSD plane without scalins is supported.
VPP: Video Post Processing
--------------------------
@@ -49,11 +51,13 @@ description: |
The VENC is composed of the multiple pixel encoders
- ENCI : Interlace Video encoder for CVBS and Interlace HDMI
- ENCP : Progressive Video Encoder for HDMI
- - ENCL : LCD LVDS Encoder
+ - ENCL : LCD DPI Encoder
The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
tree and provides the scanout clock to the VPP and VIU.
The ENCI is connected to a single VDAC for Composite Output.
The ENCI and ENCP are connected to an on-chip HDMI Transceiver.
+ On the AXG and G12A family, the ENCL is connected to a DPI-to-DSI
+ transceiver.
properties:
compatible:
@@ -65,6 +69,7 @@ properties:
- amlogic,meson-gxm-vpu # GXM (S912)
- const: amlogic,meson-gx-vpu
- enum:
+ - amlogic,meson-axg-vpu # AXG (A113D, A113X)
- amlogic,meson-g12a-vpu # G12A (S905X2, S905Y2, S905D2)
reg:
@@ -92,6 +97,11 @@ properties:
description:
A port node pointing to the HDMI-TX port node.
+ port@2:
+ type: object
+ description:
+ A port node pointing to the DPI port node.
+
"#address-cells":
const: 1
@@ -102,11 +112,31 @@ required:
- compatible
- reg
- interrupts
- - port@0
- - port@1
- "#address-cells"
- "#size-cells"
+allOf:
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-gx-vpu
+ - amlogic,meson-g12a-vpu
+
+ then:
+ required:
+ - port@0
+ - port@1
+ - if:
+ properties:
+ compatible:
+ enum:
+ - amlogic,meson-axg-vpu
+
+ then:
+ required:
+ - port@2
+
additionalProperties: false
examples:
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs
2020-09-07 8:18 ` [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs Neil Armstrong
@ 2020-09-15 15:34 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2020-09-15 15:34 UTC (permalink / raw)
To: Neil Armstrong; +Cc: daniel, devicetree, dri-devel, linux-amlogic, linux-kernel
On Mon, Sep 07, 2020 at 10:18:20AM +0200, Neil Armstrong wrote:
> The Amlogic AXG SoC family has a downgraded VPU supporting only MIPI-DSI output
> after it's ENCL DPI encoder output.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../bindings/display/amlogic,meson-vpu.yaml | 36 +++++++++++++++++--
> 1 file changed, 33 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> index a8d202c9d004..e2e7d99d8ace 100644
> --- a/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-vpu.yaml
> @@ -31,8 +31,10 @@ description: |
>
> The Video Input Unit is in charge of the pixel scanout from the DDR memory.
> It fetches the frames addresses, stride and parameters from the "Canvas" memory.
> + On the AXG family, the Video Input Unit direclty reads from DDR memory.
> This part is also in charge of the CSC (Colorspace Conversion).
> It can handle 2 OSD Planes and 2 Video Planes.
> + On the AXG family, only a single OSD plane without scalins is supported.
s/scalins/scaling/ ?
Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
2020-09-07 8:18 ` [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-15 15:41 ` Rob Herring
2020-09-07 8:18 ` [PATCH 3/6] drm/meson: add support for VPU found in AXG SoCs Neil Armstrong
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel, devicetree; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
Amlogic SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
.../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++++++++++++++++
1 file changed, 115 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
new file mode 100644
index 000000000000..6177f45ea1a6
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+# Copyright 2020 BayLibre, SAS
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
+
+maintainers:
+ - Neil Armstrong <narmstrong@baylibre.com>
+
+description: |
+ The Amlogic Meson Synopsys Designware Integration is composed of
+ - A Synopsys DesignWare MIPI DSI Host Controller IP
+ - A TOP control block controlling the Clocks & Resets of the IP
+
+allOf:
+ - $ref: dsi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - amlogic,meson-axg-dw-mipi-dsi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+
+ clock-names:
+ minItems: 2
+ items:
+ - const: pclk
+ - const: px_clk
+ - const: meas_clk
+
+ resets:
+ minItems: 1
+
+ reset-names:
+ items:
+ - const: top
+
+ phys:
+ minItems: 1
+
+ phy-names:
+ items:
+ - const: dphy
+
+ ports:
+ type: object
+
+ properties:
+ port@0:
+ type: object
+ description: Input node to receive pixel data.
+ port@1:
+ type: object
+ description: DSI output node to panel.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - phys
+ - phy-names
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ dsi@7000 {
+ compatible = "amlogic,meson-axg-dw-mipi-dsi";
+ reg = <0x6000 0x400>;
+ resets = <&reset_top>;
+ reset-names = "top";
+ clocks = <&clk_pclk>, <&clk_px>;
+ clock-names = "pclk", "px_clk";
+ phys = <&mipi_dphy>;
+ phy-names = "dphy";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VPU VENC Input */
+ mipi_dsi_venc_port: port@0 {
+ reg = <0>;
+
+ mipi_dsi_in: endpoint {
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ /* DSI Output */
+ mipi_dsi_panel_port: port@1 {
+ reg = <1>;
+
+ mipi_out_panel: endpoint {
+ remote-endpoint = <&mipi_in_panel>;
+ };
+ };
+ };
+ };
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
2020-09-07 8:18 ` [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
@ 2020-09-15 15:41 ` Rob Herring
2020-09-15 16:28 ` Neil Armstrong
0 siblings, 1 reply; 22+ messages in thread
From: Rob Herring @ 2020-09-15 15:41 UTC (permalink / raw)
To: Neil Armstrong; +Cc: daniel, devicetree, dri-devel, linux-amlogic, linux-kernel
On Mon, Sep 07, 2020 at 10:18:21AM +0200, Neil Armstrong wrote:
> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> Amlogic SoCs.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> .../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++++++++++++++++
> 1 file changed, 115 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
> new file mode 100644
> index 000000000000..6177f45ea1a6
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
> @@ -0,0 +1,115 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2020 BayLibre, SAS
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
> +
> +maintainers:
> + - Neil Armstrong <narmstrong@baylibre.com>
> +
> +description: |
> + The Amlogic Meson Synopsys Designware Integration is composed of
> + - A Synopsys DesignWare MIPI DSI Host Controller IP
> + - A TOP control block controlling the Clocks & Resets of the IP
> +
> +allOf:
> + - $ref: dsi-controller.yaml#
> +
> +properties:
> + compatible:
> + enum:
> + - amlogic,meson-axg-dw-mipi-dsi
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + minItems: 2
> +
> + clock-names:
> + minItems: 2
> + items:
> + - const: pclk
> + - const: px_clk
> + - const: meas_clk
> +
> + resets:
> + minItems: 1
> +
> + reset-names:
> + items:
> + - const: top
> +
> + phys:
> + minItems: 1
> +
> + phy-names:
> + items:
> + - const: dphy
> +
> + ports:
> + type: object
> +
> + properties:
> + port@0:
> + type: object
> + description: Input node to receive pixel data.
> + port@1:
> + type: object
> + description: DSI output node to panel.
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - phys
> + - phy-names
> + - ports
> +
> +additionalProperties: false
Presumably you may have panel/bridge child nodes, so this needs to be
'unevaluatedProperties: false'.
Rob
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
2020-09-15 15:41 ` Rob Herring
@ 2020-09-15 16:28 ` Neil Armstrong
0 siblings, 0 replies; 22+ messages in thread
From: Neil Armstrong @ 2020-09-15 16:28 UTC (permalink / raw)
To: Rob Herring; +Cc: daniel, devicetree, dri-devel, linux-amlogic, linux-kernel
On 15/09/2020 17:41, Rob Herring wrote:
> On Mon, Sep 07, 2020 at 10:18:21AM +0200, Neil Armstrong wrote:
>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>> Amlogic SoCs.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
>> .../display/amlogic,meson-dw-mipi-dsi.yaml | 115 ++++++++++++++++++
>> 1 file changed, 115 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
>> new file mode 100644
>> index 000000000000..6177f45ea1a6
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/amlogic,meson-dw-mipi-dsi.yaml
>> @@ -0,0 +1,115 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +# Copyright 2020 BayLibre, SAS
>> +%YAML 1.2
>> +---
>> +$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-mipi-dsi.yaml#"
>> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
>> +
>> +title: Amlogic specific extensions to the Synopsys Designware MIPI DSI Host Controller
>> +
>> +maintainers:
>> + - Neil Armstrong <narmstrong@baylibre.com>
>> +
>> +description: |
>> + The Amlogic Meson Synopsys Designware Integration is composed of
>> + - A Synopsys DesignWare MIPI DSI Host Controller IP
>> + - A TOP control block controlling the Clocks & Resets of the IP
>> +
>> +allOf:
>> + - $ref: dsi-controller.yaml#
>> +
>> +properties:
>> + compatible:
>> + enum:
>> + - amlogic,meson-axg-dw-mipi-dsi
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + minItems: 2
>> +
>> + clock-names:
>> + minItems: 2
>> + items:
>> + - const: pclk
>> + - const: px_clk
>> + - const: meas_clk
>> +
>> + resets:
>> + minItems: 1
>> +
>> + reset-names:
>> + items:
>> + - const: top
>> +
>> + phys:
>> + minItems: 1
>> +
>> + phy-names:
>> + items:
>> + - const: dphy
>> +
>> + ports:
>> + type: object
>> +
>> + properties:
>> + port@0:
>> + type: object
>> + description: Input node to receive pixel data.
>> + port@1:
>> + type: object
>> + description: DSI output node to panel.
>> +
>> + required:
>> + - port@0
>> + - port@1
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - resets
>> + - reset-names
>> + - phys
>> + - phy-names
>> + - ports
>> +
>> +additionalProperties: false
>
> Presumably you may have panel/bridge child nodes, so this needs to be
> 'unevaluatedProperties: false'.
OK,
Thanks.
Neil
>
> Rob
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH 3/6] drm/meson: add support for VPU found in AXG SoCs
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
2020-09-07 8:18 ` [PATCH 1/6] dt-bindings: display: amlogic,meson-vpu: add bindings for VPU found in AXG SoCs Neil Armstrong
2020-09-07 8:18 ` [PATCH 2/6] dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-07 8:18 ` [PATCH 4/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Neil Armstrong
` (2 subsequent siblings)
5 siblings, 0 replies; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
The Amlogic AXG SoC family has a downgraded VPU with the following
changes :
- Only a single OSD plane, no overlay video plane
- The primary plane doesn't support HW scaling
- The pixels are read directly from DDR without any Canvas module
- Doesn't support HDMI or CVBS
- Ouputs only with ENCL encoder to a DPI-to-DSI Synopsys DW-MIPI-DSI transceiver
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_crtc.c | 8 +-
drivers/gpu/drm/meson/meson_drv.c | 115 ++++++++++++++++--------
drivers/gpu/drm/meson/meson_drv.h | 10 ++-
drivers/gpu/drm/meson/meson_plane.c | 74 +++++++++++++--
drivers/gpu/drm/meson/meson_registers.h | 1 +
drivers/gpu/drm/meson/meson_viu.c | 50 ++++++++++-
drivers/gpu/drm/meson/meson_vpp.c | 6 +-
7 files changed, 215 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_crtc.c b/drivers/gpu/drm/meson/meson_crtc.c
index 2854272dc2d9..430599caa5a0 100644
--- a/drivers/gpu/drm/meson/meson_crtc.c
+++ b/drivers/gpu/drm/meson/meson_crtc.c
@@ -366,7 +366,13 @@ void meson_crtc_irq(struct meson_drm *priv)
writel_relaxed(priv->viu.osd_sc_v_ctrl0,
priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
- if (!priv->viu.osd1_afbcd)
+ /* AXG doesn't use CANVAS since it support a single plane */
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) {
+ writel_relaxed(priv->viu.osd1_addr,
+ priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4));
+ writel_relaxed(priv->viu.osd1_blk2_cfg4,
+ priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4));
+ } else if (!priv->viu.osd1_afbcd)
meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
priv->viu.osd1_addr,
priv->viu.osd1_stride,
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index 8b9c8dd788c4..92346653223f 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -223,6 +223,7 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
drm->dev_private = priv;
priv->drm = drm;
priv->dev = dev;
+ priv->data = match;
priv->compat = match->compat;
priv->afbcd.ops = match->afbcd_ops;
@@ -255,32 +256,34 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
goto free_drm;
}
- priv->canvas = meson_canvas_get(dev);
- if (IS_ERR(priv->canvas)) {
- ret = PTR_ERR(priv->canvas);
- goto free_drm;
- }
+ if (priv->data->requires_canvas) {
+ priv->canvas = meson_canvas_get(dev);
+ if (IS_ERR(priv->canvas)) {
+ ret = PTR_ERR(priv->canvas);
+ goto free_drm;
+ }
- ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
- if (ret)
- goto free_drm;
- ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
- if (ret) {
- meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
- goto free_drm;
- }
- ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
- if (ret) {
- meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
- meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
- goto free_drm;
- }
- ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
- if (ret) {
- meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
- meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
- meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
- goto free_drm;
+ ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1);
+ if (ret)
+ goto free_drm;
+ ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0);
+ if (ret) {
+ meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
+ goto free_drm;
+ }
+ ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1);
+ if (ret) {
+ meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
+ meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
+ goto free_drm;
+ }
+ ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2);
+ if (ret) {
+ meson_canvas_free(priv->canvas, priv->canvas_id_osd1);
+ meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0);
+ meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1);
+ goto free_drm;
+ }
}
priv->vsync_irq = platform_get_irq(pdev, 0);
@@ -303,8 +306,8 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
ret = drmm_mode_config_init(drm);
if (ret)
goto free_drm;
- drm->mode_config.max_width = 3840;
- drm->mode_config.max_height = 2160;
+ drm->mode_config.max_width = priv->data->max_width;
+ drm->mode_config.max_height = priv->data->max_height;
drm->mode_config.funcs = &meson_mode_config_funcs;
drm->mode_config.helper_private = &meson_mode_config_helpers;
@@ -322,9 +325,11 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
/* Encoder Initialization */
- ret = meson_venc_cvbs_create(priv);
- if (ret)
- goto free_drm;
+ if (priv->data->provides_cvbs) {
+ ret = meson_venc_cvbs_create(priv);
+ if (ret)
+ goto free_drm;
+ }
if (has_components) {
ret = component_bind_all(drm->dev, drm);
@@ -334,13 +339,17 @@ static int meson_drv_bind_master(struct device *dev, bool has_components)
}
}
- ret = meson_plane_create(priv);
- if (ret)
- goto free_drm;
+ if (priv->data->osd_count) {
+ ret = meson_plane_create(priv);
+ if (ret)
+ goto free_drm;
+ }
- ret = meson_overlay_create(priv);
- if (ret)
- goto free_drm;
+ if (priv->data->vd_count) {
+ ret = meson_overlay_create(priv);
+ if (ret)
+ goto free_drm;
+ }
ret = meson_crtc_create(priv);
if (ret)
@@ -516,20 +525,52 @@ static int meson_drv_probe(struct platform_device *pdev)
static struct meson_drm_match_data meson_drm_gxbb_data = {
.compat = VPU_COMPATIBLE_GXBB,
+ .requires_canvas = true,
+ .provides_cvbs = true,
+ .osd_count = 2,
+ .vd_count = 2,
+ .max_width = 3840,
+ .max_height = 2160,
};
static struct meson_drm_match_data meson_drm_gxl_data = {
.compat = VPU_COMPATIBLE_GXL,
+ .requires_canvas = true,
+ .provides_cvbs = true,
+ .osd_count = 2,
+ .vd_count = 2,
+ .max_width = 3840,
+ .max_height = 2160,
};
static struct meson_drm_match_data meson_drm_gxm_data = {
.compat = VPU_COMPATIBLE_GXM,
.afbcd_ops = &meson_afbcd_gxm_ops,
+ .requires_canvas = true,
+ .provides_cvbs = true,
+ .osd_count = 2,
+ .vd_count = 2,
+ .max_width = 3840,
+ .max_height = 2160,
+};
+
+static struct meson_drm_match_data meson_drm_axg_data = {
+ .compat = VPU_COMPATIBLE_AXG,
+ .osd_count = 1,
+ .vd_count = 0,
+ .max_width = 1920,
+ .max_height = 1080,
};
static struct meson_drm_match_data meson_drm_g12a_data = {
.compat = VPU_COMPATIBLE_G12A,
.afbcd_ops = &meson_afbcd_g12a_ops,
+ .requires_canvas = true,
+ .provides_cvbs = true,
+ .osd_count = 4,
+ .vd_count = 2,
+ .max_width = 3840,
+ .max_height = 2160,
};
static const struct of_device_id dt_match[] = {
@@ -539,6 +580,8 @@ static const struct of_device_id dt_match[] = {
.data = (void *)&meson_drm_gxl_data },
{ .compatible = "amlogic,meson-gxm-vpu",
.data = (void *)&meson_drm_gxm_data },
+ { .compatible = "amlogic,meson-axg-vpu",
+ .data = (void *)&meson_drm_axg_data },
{ .compatible = "amlogic,meson-g12a-vpu",
.data = (void *)&meson_drm_g12a_data },
{}
diff --git a/drivers/gpu/drm/meson/meson_drv.h b/drivers/gpu/drm/meson/meson_drv.h
index 177dac3ca3be..5d67f97ec298 100644
--- a/drivers/gpu/drm/meson/meson_drv.h
+++ b/drivers/gpu/drm/meson/meson_drv.h
@@ -22,12 +22,19 @@ enum vpu_compatible {
VPU_COMPATIBLE_GXBB = 0,
VPU_COMPATIBLE_GXL = 1,
VPU_COMPATIBLE_GXM = 2,
- VPU_COMPATIBLE_G12A = 3,
+ VPU_COMPATIBLE_AXG = 3,
+ VPU_COMPATIBLE_G12A = 4,
};
struct meson_drm_match_data {
enum vpu_compatible compat;
struct meson_afbcd_ops *afbcd_ops;
+ bool requires_canvas;
+ bool provides_cvbs;
+ unsigned int osd_count;
+ unsigned int vd_count;
+ unsigned int max_width;
+ unsigned int max_height;
};
struct meson_drm_soc_limits {
@@ -52,6 +59,7 @@ struct meson_drm {
struct drm_plane *primary_plane;
struct drm_plane *overlay_plane;
+ const struct meson_drm_match_data *data;
const struct meson_drm_soc_limits *limits;
/* Components Data */
diff --git a/drivers/gpu/drm/meson/meson_plane.c b/drivers/gpu/drm/meson/meson_plane.c
index 35338ed18209..9111b3540bdf 100644
--- a/drivers/gpu/drm/meson/meson_plane.c
+++ b/drivers/gpu/drm/meson/meson_plane.c
@@ -93,6 +93,25 @@ static int meson_plane_atomic_check(struct drm_plane *plane,
false, true);
}
+static int meson_plane_atomic_check_axg(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+
+ if (!state->crtc)
+ return 0;
+
+ crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ /* AXG VPU OSD plane doesn't support scaling */
+ return drm_atomic_helper_check_plane_state(state, crtc_state,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true, true);
+}
+
#define MESON_MOD_AFBC_VALID_BITS (AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 | \
AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 | \
AFBC_FORMAT_MOD_YTR | \
@@ -125,6 +144,29 @@ static u32 meson_g12a_afbcd_line_stride(struct meson_drm *priv)
return ((line_stride + 1) >> 1) << 1;
}
+static u32 meson_axg_line_stride(struct meson_drm *priv, u32 format)
+{
+ u32 line_stride = 0;
+ u32 bwidth;
+
+ switch (format) {
+ case DRM_FORMAT_RGB565:
+ bwidth = priv->viu.osd1_stride >> 1;
+ line_stride = ((bwidth << 4) + 127) >> 7;
+ break;
+ case DRM_FORMAT_RGB888:
+ case DRM_FORMAT_XRGB8888:
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ bwidth = priv->viu.osd1_stride >> 2;
+ line_stride = ((bwidth << 5) + 127) >> 7;
+ break;
+ }
+
+ return ((line_stride + 1) >> 1) << 1;
+}
+
static void meson_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
@@ -161,15 +203,20 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
else
priv->viu.osd1_afbcd = false;
- /* Enable OSD and BLK0, set max global alpha */
- priv->viu.osd1_ctrl_stat = OSD_ENABLE |
- (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
- OSD_BLK0_ENABLE;
+ priv->viu.osd1_ctrl_stat = OSD_ENABLE | OSD_BLK0_ENABLE;
+
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ priv->viu.osd1_ctrl_stat |= 0x100 << OSD_GLOBAL_ALPHA_SHIFT;
+ else
+ priv->viu.osd1_ctrl_stat |= 0xFF << OSD_GLOBAL_ALPHA_SHIFT;
priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
_REG(VIU_OSD1_CTRL_STAT2));
- canvas_id_osd1 = priv->canvas_id_osd1;
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ canvas_id_osd1 = 0x40;
+ else
+ canvas_id_osd1 = priv->canvas_id_osd1;
/* Set up BLK0 to point to the right canvas */
priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
@@ -366,7 +413,10 @@ static void meson_plane_atomic_update(struct drm_plane *plane,
priv->viu.osd1_height = fb->height;
priv->viu.osd1_width = fb->width;
- if (priv->viu.osd1_afbcd) {
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ priv->viu.osd1_blk2_cfg4 = meson_axg_line_stride(priv,
+ fb->format->format);
+ else if (priv->viu.osd1_afbcd) {
priv->afbcd.modifier = fb->modifier;
priv->afbcd.format = fb->format->format;
@@ -413,6 +463,13 @@ static void meson_plane_atomic_disable(struct drm_plane *plane,
priv->viu.osd1_enabled = false;
}
+static const struct drm_plane_helper_funcs meson_plane_helper_funcs_axg = {
+ .atomic_check = meson_plane_atomic_check_axg,
+ .atomic_disable = meson_plane_atomic_disable,
+ .atomic_update = meson_plane_atomic_update,
+ .prepare_fb = drm_gem_fb_prepare_fb,
+};
+
static const struct drm_plane_helper_funcs meson_plane_helper_funcs = {
.atomic_check = meson_plane_atomic_check,
.atomic_disable = meson_plane_atomic_disable,
@@ -550,7 +607,10 @@ int meson_plane_create(struct meson_drm *priv)
format_modifiers,
DRM_PLANE_TYPE_PRIMARY, "meson_primary_plane");
- drm_plane_helper_add(plane, &meson_plane_helper_funcs);
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ drm_plane_helper_add(plane, &meson_plane_helper_funcs_axg);
+ else
+ drm_plane_helper_add(plane, &meson_plane_helper_funcs);
/* For now, OSD Primary plane is always on the front */
drm_plane_create_zpos_immutable_property(plane, 1);
diff --git a/drivers/gpu/drm/meson/meson_registers.h b/drivers/gpu/drm/meson/meson_registers.h
index 446e7961da48..18396b59e6cb 100644
--- a/drivers/gpu/drm/meson/meson_registers.h
+++ b/drivers/gpu/drm/meson/meson_registers.h
@@ -588,6 +588,7 @@
#define VPP_OSD_SCALE_COEF_IDX 0x1dcc
#define VPP_OSD_SCALE_COEF 0x1dcd
#define VPP_INT_LINE_NUM 0x1dce
+#define VPP_MATRIX_CLIP 0x1dde
#define VPP_WRAP_OSD1_MATRIX_COEF00_01 0x3d60
#define VPP_WRAP_OSD1_MATRIX_COEF02_10 0x3d61
diff --git a/drivers/gpu/drm/meson/meson_viu.c b/drivers/gpu/drm/meson/meson_viu.c
index aede0c67a57f..9b644e598211 100644
--- a/drivers/gpu/drm/meson/meson_viu.c
+++ b/drivers/gpu/drm/meson/meson_viu.c
@@ -423,19 +423,63 @@ void meson_viu_init(struct meson_drm *priv)
/* On GXL/GXM, Use the 10bit HDR conversion matrix */
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
- meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
meson_viu_load_matrix(priv);
else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
meson_viu_set_g12a_osd1_matrix(priv, RGB709_to_YUV709l_coeff,
true);
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG)) {
+ writel_bits_relaxed(BIT(0), BIT(0),
+ priv->io_base + _REG(VPP_MATRIX_CTRL));
+ writel_bits_relaxed(0x3 << 8, 0,
+ priv->io_base + _REG(VPP_MATRIX_CTRL));
+
+ writel_relaxed(0x0fc00e00,
+ priv->io_base + _REG(VPP_MATRIX_PRE_OFFSET0_1));
+ writel_relaxed(0x00000e00,
+ priv->io_base + _REG(VPP_MATRIX_PRE_OFFSET2));
+
+ /*
+ * ycbcr limit range, 709 to RGB
+ * -16 1.164 0 1.793 0
+ * -128 1.164 -0.213 -0.534 0
+ * -128 1.164 2.115 0 0
+ */
+ writel_relaxed(0x04a80000,
+ priv->io_base + _REG(VPP_MATRIX_COEF00_01));
+ writel_relaxed(0x072c04a8,
+ priv->io_base + _REG(VPP_MATRIX_COEF02_10));
+ writel_relaxed(0x1f261ddd,
+ priv->io_base + _REG(VPP_MATRIX_COEF11_12));
+ writel_relaxed(0x04a80876,
+ priv->io_base + _REG(VPP_MATRIX_COEF20_21));
+ writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_COEF22));
+ writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_OFFSET0_1));
+ writel_relaxed(0x0, priv->io_base + _REG(VPP_MATRIX_OFFSET2));
+
+ writel_bits_relaxed(0x1f << 3, 0,
+ priv->io_base + _REG(VPP_MATRIX_CLIP));
+ }
+
/* Initialize OSD1 fifo control register */
reg = VIU_OSD_DDR_PRIORITY_URGENT |
- VIU_OSD_HOLD_FIFO_LINES(31) |
- VIU_OSD_FIFO_DEPTH_VAL(32) | /* fifo_depth_val: 32*8=256 */
VIU_OSD_WORDS_PER_BURST(4) | /* 4 words in 1 burst */
VIU_OSD_FIFO_LIMITS(2); /* fifo_lim: 2*16=32 */
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ reg |= VIU_OSD_HOLD_FIFO_LINES(24);
+ else
+ reg |= VIU_OSD_HOLD_FIFO_LINES(31);
+
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ reg |= VIU_OSD_FIFO_DEPTH_VAL(32); /* fifo_depth_val: 32*8=256 */
+ else
+ reg |= VIU_OSD_FIFO_DEPTH_VAL(64); /* fifo_depth_val: 64*8=512 */
+
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
reg |= VIU_OSD_BURST_LENGTH_32;
else
diff --git a/drivers/gpu/drm/meson/meson_vpp.c b/drivers/gpu/drm/meson/meson_vpp.c
index 154837688ab0..069f527d42c6 100644
--- a/drivers/gpu/drm/meson/meson_vpp.c
+++ b/drivers/gpu/drm/meson/meson_vpp.c
@@ -91,7 +91,8 @@ static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
void meson_vpp_init(struct meson_drm *priv)
{
/* set dummy data default YUV black */
- if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
+ if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL) ||
+ meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
writel_bits_relaxed(0xff << 16, 0xff << 16,
@@ -107,6 +108,9 @@ void meson_vpp_init(struct meson_drm *priv)
if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
writel_relaxed(VPP_OFIFO_SIZE_DEFAULT,
priv->io_base + _REG(VPP_OFIFO_SIZE));
+ else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_AXG))
+ writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x400,
+ priv->io_base + _REG(VPP_OFIFO_SIZE));
else
writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f,
priv->io_base + _REG(VPP_OFIFO_SIZE));
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 4/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
` (2 preceding siblings ...)
2020-09-07 8:18 ` [PATCH 3/6] drm/meson: add support for VPU found in AXG SoCs Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-07 8:18 ` [PATCH 5/6] drm/meson: remove useless recursive components matching Neil Armstrong
2020-09-07 8:18 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
5 siblings, 0 replies; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
This adds supports for the ENCL encoder connected to a MIPI-DSI transceiver on the
Amlogic AXG SoCs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_venc.c | 230 ++++++++++++++++++++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
3 files changed, 236 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_venc.c b/drivers/gpu/drm/meson/meson_venc.c
index f93c725b6f02..3090418deffb 100644
--- a/drivers/gpu/drm/meson/meson_venc.c
+++ b/drivers/gpu/drm/meson/meson_venc.c
@@ -6,6 +6,7 @@
*/
#include <linux/export.h>
+#include <linux/iopoll.h>
#include <drm/drm_modes.h>
@@ -1557,6 +1558,224 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
}
EXPORT_SYMBOL_GPL(meson_venc_hdmi_mode_set);
+static unsigned short meson_encl_gamma_table[256] = {
+ 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60,
+ 64, 68, 72, 76, 80, 84, 88, 92, 96, 100, 104, 108, 112, 116, 120, 124,
+ 128, 132, 136, 140, 144, 148, 152, 156, 160, 164, 168, 172, 176, 180, 184, 188,
+ 192, 196, 200, 204, 208, 212, 216, 220, 224, 228, 232, 236, 240, 244, 248, 252,
+ 256, 260, 264, 268, 272, 276, 280, 284, 288, 292, 296, 300, 304, 308, 312, 316,
+ 320, 324, 328, 332, 336, 340, 344, 348, 352, 356, 360, 364, 368, 372, 376, 380,
+ 384, 388, 392, 396, 400, 404, 408, 412, 416, 420, 424, 428, 432, 436, 440, 444,
+ 448, 452, 456, 460, 464, 468, 472, 476, 480, 484, 488, 492, 496, 500, 504, 508,
+ 512, 516, 520, 524, 528, 532, 536, 540, 544, 548, 552, 556, 560, 564, 568, 572,
+ 576, 580, 584, 588, 592, 596, 600, 604, 608, 612, 616, 620, 624, 628, 632, 636,
+ 640, 644, 648, 652, 656, 660, 664, 668, 672, 676, 680, 684, 688, 692, 696, 700,
+ 704, 708, 712, 716, 720, 724, 728, 732, 736, 740, 744, 748, 752, 756, 760, 764,
+ 768, 772, 776, 780, 784, 788, 792, 796, 800, 804, 808, 812, 816, 820, 824, 828,
+ 832, 836, 840, 844, 848, 852, 856, 860, 864, 868, 872, 876, 880, 884, 888, 892,
+ 896, 900, 904, 908, 912, 916, 920, 924, 928, 932, 936, 940, 944, 948, 952, 956,
+ 960, 964, 968, 972, 976, 980, 984, 988, 992, 996, 1000, 1004, 1008, 1012, 1016, 1020,
+};
+
+#define GAMMA_VCOM_POL 7 /* RW */
+#define GAMMA_RVS_OUT 6 /* RW */
+#define ADR_RDY 5 /* Read Only */
+#define WR_RDY 4 /* Read Only */
+#define RD_RDY 3 /* Read Only */
+#define GAMMA_TR 2 /* RW */
+#define GAMMA_SET 1 /* RW */
+#define GAMMA_EN 0 /* RW */
+
+#define H_RD 12
+#define H_AUTO_INC 11
+#define H_SEL_R 10
+#define H_SEL_G 9
+#define H_SEL_B 8
+#define HADR_MSB 7 /* 7:0 */
+#define HADR 0 /* 7:0 */
+
+#define GAMMA_RETRY 1000
+
+static void meson_encl_set_gamma_table(struct meson_drm *priv, u16 *data,
+ u32 rgb_mask)
+{
+ int i, ret;
+ u32 reg;
+
+ writel_bits_relaxed(BIT(GAMMA_EN), 0,
+ priv->io_base + _REG(L_GAMMA_CNTL_PORT));
+
+ ret = readl_relaxed_poll_timeout(priv->io_base +
+ _REG(L_GAMMA_CNTL_PORT),
+ reg, reg & BIT(ADR_RDY), 10, 10000);
+ if (ret)
+ pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
+
+ writel_relaxed(BIT(H_AUTO_INC) |
+ BIT(rgb_mask) |
+ (0 << HADR),
+ priv->io_base + _REG(L_GAMMA_ADDR_PORT));
+
+ for (i = 0; i < 256; i++) {
+ ret = readl_relaxed_poll_timeout(priv->io_base +
+ _REG(L_GAMMA_CNTL_PORT),
+ reg, reg & BIT(WR_RDY),
+ 10, 10000);
+ if (ret)
+ pr_warn_once("%s: GAMMA WR_RDY timeout\n", __func__);
+
+ writel_relaxed(data[i],
+ priv->io_base + _REG(L_GAMMA_DATA_PORT));
+ }
+
+ ret = readl_relaxed_poll_timeout(priv->io_base +
+ _REG(L_GAMMA_CNTL_PORT),
+ reg, reg & BIT(ADR_RDY), 10, 10000);
+ if (ret)
+ pr_warn("%s: GAMMA ADR_RDY timeout\n", __func__);
+
+ writel_relaxed(BIT(H_AUTO_INC) |
+ BIT(rgb_mask) |
+ (0x23 << HADR),
+ priv->io_base + _REG(L_GAMMA_ADDR_PORT));
+}
+
+void meson_encl_load_gamma(struct meson_drm *priv)
+{
+ meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_R);
+ meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_G);
+ meson_encl_set_gamma_table(priv, meson_encl_gamma_table, H_SEL_B);
+
+ writel_bits_relaxed(BIT(GAMMA_EN), BIT(GAMMA_EN),
+ priv->io_base + _REG(L_GAMMA_CNTL_PORT));
+}
+
+void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
+ struct drm_display_mode *mode)
+{
+ unsigned int max_pxcnt;
+ unsigned int max_lncnt;
+ unsigned int havon_begin;
+ unsigned int havon_end;
+ unsigned int vavon_bline;
+ unsigned int vavon_eline;
+ unsigned int hso_begin;
+ unsigned int hso_end;
+ unsigned int vso_begin;
+ unsigned int vso_end;
+ unsigned int vso_bline;
+ unsigned int vso_eline;
+
+ max_pxcnt = mode->htotal - 1;
+ max_lncnt = mode->vtotal - 1;
+ havon_begin = mode->htotal - mode->hsync_start;
+ havon_end = havon_begin + mode->hdisplay - 1;
+ vavon_bline = mode->vtotal - mode->vsync_start;
+ vavon_eline = vavon_bline + mode->vdisplay - 1;
+ hso_begin = 0;
+ hso_end = mode->hsync_end - mode->hsync_start;
+ vso_begin = 0;
+ vso_end = 0;
+ vso_bline = 0;
+ vso_eline = mode->vsync_end - mode->vsync_start;
+
+ meson_vpp_setup_mux(priv, MESON_VIU_VPP_MUX_ENCL);
+
+ writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
+
+ writel_relaxed(0x8000, priv->io_base + _REG(ENCL_VIDEO_MODE));
+ writel_relaxed(0x0418, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
+
+ writel_relaxed(0x1000, priv->io_base + _REG(ENCL_VIDEO_FILT_CTRL));
+ writel_relaxed(max_pxcnt, priv->io_base + _REG(ENCL_VIDEO_MAX_PXCNT));
+ writel_relaxed(max_lncnt, priv->io_base + _REG(ENCL_VIDEO_MAX_LNCNT));
+ writel_relaxed(havon_begin, priv->io_base + _REG(ENCL_VIDEO_HAVON_BEGIN));
+ writel_relaxed(havon_end, priv->io_base + _REG(ENCL_VIDEO_HAVON_END));
+ writel_relaxed(vavon_bline, priv->io_base + _REG(ENCL_VIDEO_VAVON_BLINE));
+ writel_relaxed(vavon_eline, priv->io_base + _REG(ENCL_VIDEO_VAVON_ELINE));
+
+ writel_relaxed(hso_begin, priv->io_base + _REG(ENCL_VIDEO_HSO_BEGIN));
+ writel_relaxed(hso_end, priv->io_base + _REG(ENCL_VIDEO_HSO_END));
+ writel_relaxed(vso_begin, priv->io_base + _REG(ENCL_VIDEO_VSO_BEGIN));
+ writel_relaxed(vso_end, priv->io_base + _REG(ENCL_VIDEO_VSO_END));
+ writel_relaxed(vso_bline, priv->io_base + _REG(ENCL_VIDEO_VSO_BLINE));
+ writel_relaxed(vso_eline, priv->io_base + _REG(ENCL_VIDEO_VSO_ELINE));
+ writel_relaxed(3, priv->io_base + _REG(ENCL_VIDEO_RGBIN_CTRL));
+
+ /* default black pattern */
+ writel_relaxed(0, priv->io_base + _REG(ENCL_TST_MDSEL));
+ writel_relaxed(0, priv->io_base + _REG(ENCL_TST_Y));
+ writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CB));
+ writel_relaxed(0, priv->io_base + _REG(ENCL_TST_CR));
+ writel_relaxed(1, priv->io_base + _REG(ENCL_TST_EN));
+ writel_bits_relaxed(BIT(3), 0, priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
+
+ writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
+
+ writel_relaxed(0, priv->io_base + _REG(L_RGB_BASE_ADDR));
+ writel_relaxed(0x400, priv->io_base + _REG(L_RGB_COEFF_ADDR));
+ writel_relaxed(0x400, priv->io_base + _REG(L_DITH_CNTL_ADDR));
+
+ /* DE signal for TTL */
+ writel_relaxed(havon_begin, priv->io_base + _REG(L_OEH_HS_ADDR));
+ writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEH_HE_ADDR));
+ writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEH_VS_ADDR));
+ writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEH_VE_ADDR));
+
+ /* DE signal for TTL */
+ writel_relaxed(havon_begin, priv->io_base + _REG(L_OEV1_HS_ADDR));
+ writel_relaxed(havon_end + 1, priv->io_base + _REG(L_OEV1_HE_ADDR));
+ writel_relaxed(vavon_bline, priv->io_base + _REG(L_OEV1_VS_ADDR));
+ writel_relaxed(vavon_eline, priv->io_base + _REG(L_OEV1_VE_ADDR));
+
+ /* Hsync signal for TTL */
+ if (mode->flags & DRM_MODE_FLAG_PHSYNC) {
+ writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HS_ADDR));
+ writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HE_ADDR));
+ } else {
+ writel_relaxed(hso_begin, priv->io_base + _REG(L_STH1_HS_ADDR));
+ writel_relaxed(hso_end, priv->io_base + _REG(L_STH1_HE_ADDR));
+ }
+ writel_relaxed(0, priv->io_base + _REG(L_STH1_VS_ADDR));
+ writel_relaxed(max_lncnt, priv->io_base + _REG(L_STH1_VE_ADDR));
+
+ /* Vsync signal for TTL */
+ writel_relaxed(vso_begin, priv->io_base + _REG(L_STV1_HS_ADDR));
+ writel_relaxed(vso_end, priv->io_base + _REG(L_STV1_HE_ADDR));
+ if (mode->flags & DRM_MODE_FLAG_PVSYNC) {
+ writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VS_ADDR));
+ writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VE_ADDR));
+ } else {
+ writel_relaxed(vso_bline, priv->io_base + _REG(L_STV1_VS_ADDR));
+ writel_relaxed(vso_eline, priv->io_base + _REG(L_STV1_VE_ADDR));
+ }
+
+ /* DE signal */
+ writel_relaxed(havon_begin, priv->io_base + _REG(L_DE_HS_ADDR));
+ writel_relaxed(havon_end + 1, priv->io_base + _REG(L_DE_HE_ADDR));
+ writel_relaxed(vavon_bline, priv->io_base + _REG(L_DE_VS_ADDR));
+ writel_relaxed(vavon_eline, priv->io_base + _REG(L_DE_VE_ADDR));
+
+ /* Hsync signal */
+ writel_relaxed(hso_begin, priv->io_base + _REG(L_HSYNC_HS_ADDR));
+ writel_relaxed(hso_end, priv->io_base + _REG(L_HSYNC_HE_ADDR));
+ writel_relaxed(0, priv->io_base + _REG(L_HSYNC_VS_ADDR));
+ writel_relaxed(max_lncnt, priv->io_base + _REG(L_HSYNC_VE_ADDR));
+
+ /* Vsync signal */
+ writel_relaxed(vso_begin, priv->io_base + _REG(L_VSYNC_HS_ADDR));
+ writel_relaxed(vso_end, priv->io_base + _REG(L_VSYNC_HE_ADDR));
+ writel_relaxed(vso_bline, priv->io_base + _REG(L_VSYNC_VS_ADDR));
+ writel_relaxed(vso_eline, priv->io_base + _REG(L_VSYNC_VE_ADDR));
+
+ writel_relaxed(0, priv->io_base + _REG(L_INV_CNT_ADDR));
+ writel_relaxed(BIT(4) | BIT(5),
+ priv->io_base + _REG(L_TCON_MISC_SEL_ADDR));
+
+ priv->venc.current_mode = MESON_VENC_MODE_MIPI_DSI;
+}
+EXPORT_SYMBOL_GPL(meson_venc_mipi_dsi_mode_set);
+
void meson_venci_cvbs_mode_set(struct meson_drm *priv,
struct meson_cvbs_enci_mode *mode)
{
@@ -1747,8 +1966,15 @@ unsigned int meson_venci_get_field(struct meson_drm *priv)
void meson_venc_enable_vsync(struct meson_drm *priv)
{
- writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
- priv->io_base + _REG(VENC_INTCTRL));
+ switch (priv->venc.current_mode) {
+ case MESON_VENC_MODE_MIPI_DSI:
+ writel_relaxed(0x200,
+ priv->io_base + _REG(VENC_INTCTRL));
+ break;
+ default:
+ writel_relaxed(VENC_INTCTRL_ENCI_LNRST_INT_EN,
+ priv->io_base + _REG(VENC_INTCTRL));
+ }
regmap_update_bits(priv->hhi, HHI_GCLK_MPEG2, BIT(25), BIT(25));
}
diff --git a/drivers/gpu/drm/meson/meson_venc.h b/drivers/gpu/drm/meson/meson_venc.h
index 9138255ffc9e..15f9a5effb40 100644
--- a/drivers/gpu/drm/meson/meson_venc.h
+++ b/drivers/gpu/drm/meson/meson_venc.h
@@ -21,6 +21,7 @@ enum {
MESON_VENC_MODE_CVBS_PAL,
MESON_VENC_MODE_CVBS_NTSC,
MESON_VENC_MODE_HDMI,
+ MESON_VENC_MODE_MIPI_DSI,
};
struct meson_cvbs_enci_mode {
@@ -47,6 +48,9 @@ struct meson_cvbs_enci_mode {
unsigned int analog_sync_adj;
};
+/* LCD Encoder gamma setup */
+void meson_encl_load_gamma(struct meson_drm *priv);
+
/* HDMI Clock parameters */
enum drm_mode_status
meson_venc_hdmi_supported_mode(const struct drm_display_mode *mode);
@@ -63,6 +67,8 @@ void meson_venc_hdmi_mode_set(struct meson_drm *priv, int vic,
unsigned int ycrcb_map,
bool yuv420_mode,
const struct drm_display_mode *mode);
+void meson_venc_mipi_dsi_mode_set(struct meson_drm *priv,
+ struct drm_display_mode *mode);
unsigned int meson_venci_get_field(struct meson_drm *priv);
void meson_venc_enable_vsync(struct meson_drm *priv);
diff --git a/drivers/gpu/drm/meson/meson_vpp.h b/drivers/gpu/drm/meson/meson_vpp.h
index afc9553ed8d3..b790042a1650 100644
--- a/drivers/gpu/drm/meson/meson_vpp.h
+++ b/drivers/gpu/drm/meson/meson_vpp.h
@@ -12,6 +12,8 @@
struct drm_rect;
struct meson_drm;
+/* Mux VIU/VPP to ENCL */
+#define MESON_VIU_VPP_MUX_ENCL 0x0
/* Mux VIU/VPP to ENCI */
#define MESON_VIU_VPP_MUX_ENCI 0x5
/* Mux VIU/VPP to ENCP */
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 5/6] drm/meson: remove useless recursive components matching
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
` (3 preceding siblings ...)
2020-09-07 8:18 ` [PATCH 4/6] drm/meson: venc: add ENCL encoder setup for MIPI-DSI output Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-07 8:18 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
5 siblings, 0 replies; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
The initial design was recursive to cover all port/endpoints, but only the first layer
of endpoints should be covered by the components list.
This also breaks the MIPI-DSI init/bridge attach sequence, thus only parse the
first endpoints instead of recursing.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/meson_drv.c | 48 +++++--------------------------
1 file changed, 7 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/meson/meson_drv.c b/drivers/gpu/drm/meson/meson_drv.c
index 92346653223f..1a4cf910c6a0 100644
--- a/drivers/gpu/drm/meson/meson_drv.c
+++ b/drivers/gpu/drm/meson/meson_drv.c
@@ -449,46 +449,6 @@ static int compare_of(struct device *dev, void *data)
return dev->of_node == data;
}
-/* Possible connectors nodes to ignore */
-static const struct of_device_id connectors_match[] = {
- { .compatible = "composite-video-connector" },
- { .compatible = "svideo-connector" },
- { .compatible = "hdmi-connector" },
- { .compatible = "dvi-connector" },
- {}
-};
-
-static int meson_probe_remote(struct platform_device *pdev,
- struct component_match **match,
- struct device_node *parent,
- struct device_node *remote)
-{
- struct device_node *ep, *remote_node;
- int count = 1;
-
- /* If node is a connector, return and do not add to match table */
- if (of_match_node(connectors_match, remote))
- return 1;
-
- component_match_add(&pdev->dev, match, compare_of, remote);
-
- for_each_endpoint_of_node(remote, ep) {
- remote_node = of_graph_get_remote_port_parent(ep);
- if (!remote_node ||
- remote_node == parent || /* Ignore parent endpoint */
- !of_device_is_available(remote_node)) {
- of_node_put(remote_node);
- continue;
- }
-
- count += meson_probe_remote(pdev, match, remote, remote_node);
-
- of_node_put(remote_node);
- }
-
- return count;
-}
-
static int meson_drv_probe(struct platform_device *pdev)
{
struct component_match *match = NULL;
@@ -503,8 +463,14 @@ static int meson_drv_probe(struct platform_device *pdev)
continue;
}
- count += meson_probe_remote(pdev, &match, np, remote);
+ DRM_DEBUG_DRIVER("parent %pOF remote %pOF\n", np, remote);
+
+ DRM_DEBUG_DRIVER("match add %pOF parent %s\n", remote, dev_name(&pdev->dev));
+ component_match_add(&pdev->dev, &match, compare_of, remote);
+
of_node_put(remote);
+
+ ++count;
}
if (count && !match)
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 8:18 [PATCH 0/6] drm/meson: add support for AXG & MIPI-DSI Neil Armstrong
` (4 preceding siblings ...)
2020-09-07 8:18 ` [PATCH 5/6] drm/meson: remove useless recursive components matching Neil Armstrong
@ 2020-09-07 8:18 ` Neil Armstrong
2020-09-07 8:43 ` Daniel Vetter
2022-01-12 7:24 ` Jagan Teki
5 siblings, 2 replies; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 8:18 UTC (permalink / raw)
To: daniel; +Cc: dri-devel, linux-amlogic, linux-kernel, Neil Armstrong
The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
Amlogic SoCs.
This adds support for the Glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
is derived and feeds the ENCL encoder and the VIU pixel reader.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 1 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
3 files changed, 570 insertions(+)
create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
index 9f9281dd49f8..385f6f23839b 100644
--- a/drivers/gpu/drm/meson/Kconfig
+++ b/drivers/gpu/drm/meson/Kconfig
@@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
default y if DRM_MESON
select DRM_DW_HDMI
imply DRM_DW_HDMI_I2S_AUDIO
+
+config DRM_MESON_DW_MIPI_DSI
+ tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
+ depends on DRM_MESON
+ default y if DRM_MESON
+ select DRM_DW_MIPI_DSI
+ select GENERIC_PHY_MIPI_DPHY
diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
index 28a519cdf66b..2cc870e91182 100644
--- a/drivers/gpu/drm/meson/Makefile
+++ b/drivers/gpu/drm/meson/Makefile
@@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
obj-$(CONFIG_DRM_MESON) += meson-drm.o
obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
+obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
new file mode 100644
index 000000000000..bbe1294fce7c
--- /dev/null
+++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
@@ -0,0 +1,562 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2016 BayLibre, SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_graph.h>
+#include <linux/reset.h>
+#include <linux/phy/phy.h>
+
+#include <video/mipi_display.h>
+
+#include <drm/bridge/dw_mipi_dsi.h>
+#include <drm/drm_mipi_dsi.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_device.h>
+#include <drm/drm_probe_helper.h>
+#include <drm/drm_print.h>
+
+#include "meson_drv.h"
+#include "meson_dw_mipi_dsi.h"
+#include "meson_registers.h"
+#include "meson_venc.h"
+
+#define DRIVER_NAME "meson-dw-mipi-dsi"
+#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
+
+/* MIPI DSI/VENC Color Format Definitions */
+#define MIPI_DSI_VENC_COLOR_30B 0x0
+#define MIPI_DSI_VENC_COLOR_24B 0x1
+#define MIPI_DSI_VENC_COLOR_18B 0x2
+#define MIPI_DSI_VENC_COLOR_16B 0x3
+
+#define COLOR_16BIT_CFG_1 0x0
+#define COLOR_16BIT_CFG_2 0x1
+#define COLOR_16BIT_CFG_3 0x2
+#define COLOR_18BIT_CFG_1 0x3
+#define COLOR_18BIT_CFG_2 0x4
+#define COLOR_24BIT 0x5
+#define COLOR_20BIT_LOOSE 0x6
+#define COLOR_24_BIT_YCBCR 0x7
+#define COLOR_16BIT_YCBCR 0x8
+#define COLOR_30BIT 0x9
+#define COLOR_36BIT 0xa
+#define COLOR_12BIT 0xb
+#define COLOR_RGB_111 0xc
+#define COLOR_RGB_332 0xd
+#define COLOR_RGB_444 0xe
+
+/* MIPI DSI Relative REGISTERs Definitions */
+/* For MIPI_DSI_TOP_CNTL */
+#define BIT_DPI_COLOR_MODE 20
+#define BIT_IN_COLOR_MODE 16
+#define BIT_CHROMA_SUBSAMPLE 14
+#define BIT_COMP2_SEL 12
+#define BIT_COMP1_SEL 10
+#define BIT_COMP0_SEL 8
+#define BIT_DE_POL 6
+#define BIT_HSYNC_POL 5
+#define BIT_VSYNC_POL 4
+#define BIT_DPICOLORM 3
+#define BIT_DPISHUTDN 2
+#define BIT_EDPITE_INTR_PULSE 1
+#define BIT_ERR_INTR_PULSE 0
+
+/* HHI Registers */
+#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
+#define VCLK2_DIV_MASK 0xff
+#define VCLK2_DIV_EN BIT(16)
+#define VCLK2_DIV_RESET BIT(17)
+#define CTS_ENCL_SEL_MASK (0xf << 12)
+#define CTS_ENCL_SEL_SHIFT 12
+#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
+#define VCLK2_EN BIT(19)
+#define VCLK2_SEL_MASK (0x7 << 16)
+#define VCLK2_SEL_SHIFT 16
+#define VCLK2_SOFT_RESET BIT(15)
+#define VCLK2_DIV1_EN BIT(0)
+#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
+#define CTS_ENCL_EN BIT(3)
+
+/**
+ * DOC: MIPI DSI
+ *
+ */
+
+struct meson_dw_mipi_dsi {
+ struct drm_encoder encoder;
+ struct meson_drm *priv;
+ struct device *dev;
+ void __iomem *base;
+ struct phy *phy;
+ union phy_configure_opts phy_opts;
+ struct dw_mipi_dsi *dmd;
+ struct dw_mipi_dsi_plat_data pdata;
+ struct mipi_dsi_device *dsi_device;
+ unsigned long mode_flags;
+ struct clk *px_clk;
+};
+#define encoder_to_meson_dw_mipi_dsi(x) \
+ container_of(x, struct meson_dw_mipi_dsi, encoder)
+
+static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
+ struct drm_display_mode *mode)
+{
+ struct meson_drm *priv = mipi_dsi->priv;
+ unsigned int vclk2_div;
+ unsigned int pll_rate;
+ int ret;
+
+ pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
+ vclk2_div = pll_rate / (mode->clock * 1000);
+
+ ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
+ if (ret) {
+ pr_err("Failed to set DSI PLL rate %lu\n",
+ mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
+
+ return;
+ }
+
+ /* Disable VCLK2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
+
+ /* Setup the VCLK2 divider value */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ VCLK2_DIV_MASK, (vclk2_div - 1));
+
+ /* select gp0 for vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
+
+ /* enable vclk2 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
+
+ /* select vclk2_div1 for encl */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
+
+ /* release vclk2_div_reset and enable vclk2_div */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
+ VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
+
+ /* enable vclk2_div1 gate */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_DIV1_EN, VCLK2_DIV1_EN);
+
+ /* reset vclk2 */
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
+ regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
+ VCLK2_SOFT_RESET, 0);
+
+ /* enable encl_clk */
+ regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
+ CTS_ENCL_EN, CTS_ENCL_EN);
+
+ usleep_range(10000, 11000);
+}
+
+static int dw_mipi_dsi_phy_init(void *priv_data)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
+ struct meson_drm *priv = mipi_dsi->priv;
+
+
+ phy_power_on(mipi_dsi->phy);
+
+ writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
+
+ return 0;
+}
+
+static void dw_mipi_dsi_phy_power_off(void *priv_data)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
+
+ phy_power_off(mipi_dsi->phy);
+}
+
+static int
+dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
+ unsigned long mode_flags, u32 lanes, u32 format,
+ unsigned int *lane_mbps)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
+
+ *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
+
+ return 0;
+}
+
+static int
+dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
+ struct dw_mipi_dsi_dphy_timing *timing)
+{
+ /* TOFIX handle other cases */
+
+ timing->clk_lp2hs = 37;
+ timing->clk_hs2lp = 135;
+ timing->data_lp2hs = 50;
+ timing->data_hs2lp = 3;
+
+ return 0;
+}
+
+static int
+dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
+{
+ *esc_clk_rate = 4; /* Mhz */
+
+ return 0;
+}
+
+static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
+ .init = dw_mipi_dsi_phy_init,
+ .power_off = dw_mipi_dsi_phy_power_off,
+ .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
+ .get_timing = dw_mipi_dsi_phy_get_timing,
+ .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
+};
+
+/* Encoder */
+
+static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+}
+
+static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
+ .destroy = meson_mipi_dsi_encoder_destroy,
+};
+
+static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
+ struct drm_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi =
+ encoder_to_meson_dw_mipi_dsi(encoder);
+
+ switch (mipi_dsi->dsi_device->format) {
+ case MIPI_DSI_FMT_RGB888:
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ case MIPI_DSI_FMT_RGB565:
+ default:
+ DRM_DEV_ERROR(mipi_dsi->dev,
+ "invalid pixel format %d\n",
+ mipi_dsi->dsi_device->format);
+ return -EINVAL;
+ };
+
+ return 0;
+}
+
+static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi =
+ encoder_to_meson_dw_mipi_dsi(encoder);
+ struct meson_drm *priv = mipi_dsi->priv;
+
+ writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
+}
+
+static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi =
+ encoder_to_meson_dw_mipi_dsi(encoder);
+ struct meson_drm *priv = mipi_dsi->priv;
+
+ writel_bits_relaxed(BIT(3), BIT(3),
+ priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
+ writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
+}
+
+static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
+{
+ writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
+ mipi_dsi->base + MIPI_DSI_TOP_CNTL);
+
+ writel_bits_relaxed(0xf, 0xf,
+ mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
+ writel_bits_relaxed(0xf, 0,
+ mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
+
+ writel_bits_relaxed(0x3, 0x3,
+ mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
+
+ writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
+}
+
+static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
+ unsigned int dpi_data_format, venc_data_width;
+ struct meson_drm *priv = mipi_dsi->priv;
+ int bpp;
+ u32 reg;
+
+ mipi_dsi->mode_flags = mode->flags;
+
+ bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
+
+ phy_mipi_dphy_get_default_config(mode->clock * 1000,
+ bpp, mipi_dsi->dsi_device->lanes,
+ &mipi_dsi->phy_opts.mipi_dphy);
+
+ phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
+
+ switch (mipi_dsi->dsi_device->format) {
+ case MIPI_DSI_FMT_RGB888:
+ dpi_data_format = COLOR_24BIT;
+ venc_data_width = MIPI_DSI_VENC_COLOR_24B;
+ break;
+ case MIPI_DSI_FMT_RGB666:
+ dpi_data_format = COLOR_18BIT_CFG_2;
+ venc_data_width = MIPI_DSI_VENC_COLOR_18B;
+ break;
+ case MIPI_DSI_FMT_RGB666_PACKED:
+ case MIPI_DSI_FMT_RGB565:
+ /* invalid */
+ break;
+ };
+
+ dw_mipi_dsi_set_vclk(mipi_dsi, mode);
+ meson_venc_mipi_dsi_mode_set(priv, mode);
+
+ meson_encl_load_gamma(priv);
+
+ writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
+
+ meson_dw_mipi_dsi_init(mipi_dsi);
+
+ /* Configure Set color format for DPI register */
+ reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
+ ~(0xf<<BIT_DPI_COLOR_MODE) &
+ ~(0x7<<BIT_IN_COLOR_MODE) &
+ ~(0x3<<BIT_CHROMA_SUBSAMPLE);
+
+ writel_relaxed(reg |
+ (dpi_data_format << BIT_DPI_COLOR_MODE) |
+ (venc_data_width << BIT_IN_COLOR_MODE) |
+ 0 << BIT_COMP0_SEL |
+ 1 << BIT_COMP1_SEL |
+ 2 << BIT_COMP2_SEL |
+ (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
+ (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
+ mipi_dsi->base + MIPI_DSI_TOP_CNTL);
+}
+
+static const struct drm_encoder_helper_funcs
+ meson_mipi_dsi_encoder_helper_funcs = {
+ .atomic_check = meson_mipi_dsi_encoder_atomic_check,
+ .disable = meson_mipi_dsi_encoder_disable,
+ .enable = meson_mipi_dsi_encoder_enable,
+ .mode_set = meson_mipi_dsi_encoder_mode_set,
+};
+
+static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
+ struct drm_device *drm = data;
+ struct meson_drm *priv = drm->dev_private;
+ struct drm_encoder *encoder;
+ int ret;
+
+ /* Check before if we are supposed to have a sub-device... */
+ if (!mipi_dsi->dsi_device)
+ return -EPROBE_DEFER;
+
+ encoder = &mipi_dsi->encoder;
+ mipi_dsi->priv = priv;
+
+ /* Encoder */
+ ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
+ DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
+ if (ret) {
+ dev_err(priv->dev, "Failed to init DSI encoder\n");
+ return ret;
+ }
+
+ drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
+
+ encoder->possible_crtcs = BIT(0);
+
+ ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
+ if (ret) {
+ DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
+ return ret;
+ }
+
+ phy_init(mipi_dsi->phy);
+
+ return 0;
+}
+
+static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
+
+ dw_mipi_dsi_remove(mipi_dsi->dmd);
+
+ phy_exit(mipi_dsi->phy);
+}
+
+static const struct component_ops meson_dw_mipi_dsi_ops = {
+ .bind = meson_dw_mipi_dsi_bind,
+ .unbind = meson_dw_mipi_dsi_unbind,
+};
+
+static int meson_dw_mipi_dsi_host_attach(void *priv_data,
+ struct mipi_dsi_device *device)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
+
+ mipi_dsi->dsi_device = device;
+
+ return 0;
+}
+
+static int meson_dw_mipi_dsi_host_detach(void *priv_data,
+ struct mipi_dsi_device *device)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
+
+ if (device == mipi_dsi->dsi_device)
+ mipi_dsi->dsi_device = NULL;
+ else
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
+ .attach = meson_dw_mipi_dsi_host_attach,
+ .detach = meson_dw_mipi_dsi_host_detach,
+};
+
+static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi;
+ struct reset_control *top_rst;
+ struct resource *res;
+ int ret;
+
+ mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
+ if (!mipi_dsi)
+ return -ENOMEM;
+
+ mipi_dsi->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mipi_dsi->base))
+ return PTR_ERR(mipi_dsi->base);
+
+ mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
+ if (IS_ERR(mipi_dsi->phy)) {
+ ret = PTR_ERR(mipi_dsi->phy);
+ dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
+ return ret;
+ }
+
+ mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
+ if (IS_ERR(mipi_dsi->px_clk)) {
+ dev_err(&pdev->dev, "Unable to get PLL clk\n");
+ return PTR_ERR(mipi_dsi->px_clk);
+ }
+
+ /*
+ * We use a TOP reset signal because the APB reset signal
+ * is handled by the TOP control registers.
+ */
+ top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
+ if (IS_ERR(top_rst)) {
+ ret = PTR_ERR(top_rst);
+
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
+
+ return ret;
+ }
+
+ ret = clk_prepare_enable(mipi_dsi->px_clk);
+ if (ret) {
+ dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
+ goto err_clkdisable;
+ }
+
+ reset_control_assert(top_rst);
+ usleep_range(10, 20);
+ reset_control_deassert(top_rst);
+
+ /* MIPI DSI Controller */
+
+ mipi_dsi->pdata.base = mipi_dsi->base;
+ mipi_dsi->pdata.max_data_lanes = 4;
+ mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
+ mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
+ mipi_dsi->pdata.priv_data = mipi_dsi;
+ platform_set_drvdata(pdev, mipi_dsi);
+
+ mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
+ if (IS_ERR(mipi_dsi->dmd)) {
+ ret = PTR_ERR(mipi_dsi->dmd);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev,
+ "Failed to probe dw_mipi_dsi: %d\n", ret);
+ goto err_clkdisable;
+ }
+
+ return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
+
+err_clkdisable:
+ clk_disable_unprepare(mipi_dsi->px_clk);
+
+ return ret;
+}
+
+static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
+{
+ struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
+
+ component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
+
+ clk_disable_unprepare(mipi_dsi->px_clk);
+
+ return 0;
+}
+
+static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
+ { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
+
+static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
+ .probe = meson_dw_mipi_dsi_probe,
+ .remove = meson_dw_mipi_dsi_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = meson_dw_mipi_dsi_of_table,
+ },
+};
+module_platform_driver(meson_dw_mipi_dsi_platform_driver);
+
+MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
--
2.22.0
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 8:18 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
@ 2020-09-07 8:43 ` Daniel Vetter
2020-09-07 8:44 ` Daniel Vetter
2022-01-12 7:24 ` Jagan Teki
1 sibling, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2020-09-07 8:43 UTC (permalink / raw)
To: Neil Armstrong; +Cc: daniel, dri-devel, linux-amlogic, linux-kernel
On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> Amlogic SoCs.
>
> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> Analog PHY in the proper way.
>
> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> is derived and feeds the ENCL encoder and the VIU pixel reader.
>
> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> DW-MIPI-DSI transceiver.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
More dw-hdmi drivers which aren't bridges but components, and the thing is
still midlayer-y as heck :-/
Can we try to fix this? There's a ton of this going on, and the more we
add the old fashioned way the harder this gets to fix up for real.
-Daniel
> ---
> drivers/gpu/drm/meson/Kconfig | 7 +
> drivers/gpu/drm/meson/Makefile | 1 +
> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> 3 files changed, 570 insertions(+)
> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>
> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> index 9f9281dd49f8..385f6f23839b 100644
> --- a/drivers/gpu/drm/meson/Kconfig
> +++ b/drivers/gpu/drm/meson/Kconfig
> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> default y if DRM_MESON
> select DRM_DW_HDMI
> imply DRM_DW_HDMI_I2S_AUDIO
> +
> +config DRM_MESON_DW_MIPI_DSI
> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> + depends on DRM_MESON
> + default y if DRM_MESON
> + select DRM_DW_MIPI_DSI
> + select GENERIC_PHY_MIPI_DPHY
> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> index 28a519cdf66b..2cc870e91182 100644
> --- a/drivers/gpu/drm/meson/Makefile
> +++ b/drivers/gpu/drm/meson/Makefile
> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
>
> obj-$(CONFIG_DRM_MESON) += meson-drm.o
> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> new file mode 100644
> index 000000000000..bbe1294fce7c
> --- /dev/null
> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> @@ -0,0 +1,562 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2016 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/reset.h>
> +#include <linux/phy/phy.h>
> +
> +#include <video/mipi_display.h>
> +
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <drm/drm_mipi_dsi.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_device.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/drm_print.h>
> +
> +#include "meson_drv.h"
> +#include "meson_dw_mipi_dsi.h"
> +#include "meson_registers.h"
> +#include "meson_venc.h"
> +
> +#define DRIVER_NAME "meson-dw-mipi-dsi"
> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> +
> +/* MIPI DSI/VENC Color Format Definitions */
> +#define MIPI_DSI_VENC_COLOR_30B 0x0
> +#define MIPI_DSI_VENC_COLOR_24B 0x1
> +#define MIPI_DSI_VENC_COLOR_18B 0x2
> +#define MIPI_DSI_VENC_COLOR_16B 0x3
> +
> +#define COLOR_16BIT_CFG_1 0x0
> +#define COLOR_16BIT_CFG_2 0x1
> +#define COLOR_16BIT_CFG_3 0x2
> +#define COLOR_18BIT_CFG_1 0x3
> +#define COLOR_18BIT_CFG_2 0x4
> +#define COLOR_24BIT 0x5
> +#define COLOR_20BIT_LOOSE 0x6
> +#define COLOR_24_BIT_YCBCR 0x7
> +#define COLOR_16BIT_YCBCR 0x8
> +#define COLOR_30BIT 0x9
> +#define COLOR_36BIT 0xa
> +#define COLOR_12BIT 0xb
> +#define COLOR_RGB_111 0xc
> +#define COLOR_RGB_332 0xd
> +#define COLOR_RGB_444 0xe
> +
> +/* MIPI DSI Relative REGISTERs Definitions */
> +/* For MIPI_DSI_TOP_CNTL */
> +#define BIT_DPI_COLOR_MODE 20
> +#define BIT_IN_COLOR_MODE 16
> +#define BIT_CHROMA_SUBSAMPLE 14
> +#define BIT_COMP2_SEL 12
> +#define BIT_COMP1_SEL 10
> +#define BIT_COMP0_SEL 8
> +#define BIT_DE_POL 6
> +#define BIT_HSYNC_POL 5
> +#define BIT_VSYNC_POL 4
> +#define BIT_DPICOLORM 3
> +#define BIT_DPISHUTDN 2
> +#define BIT_EDPITE_INTR_PULSE 1
> +#define BIT_ERR_INTR_PULSE 0
> +
> +/* HHI Registers */
> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> +#define VCLK2_DIV_MASK 0xff
> +#define VCLK2_DIV_EN BIT(16)
> +#define VCLK2_DIV_RESET BIT(17)
> +#define CTS_ENCL_SEL_MASK (0xf << 12)
> +#define CTS_ENCL_SEL_SHIFT 12
> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> +#define VCLK2_EN BIT(19)
> +#define VCLK2_SEL_MASK (0x7 << 16)
> +#define VCLK2_SEL_SHIFT 16
> +#define VCLK2_SOFT_RESET BIT(15)
> +#define VCLK2_DIV1_EN BIT(0)
> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> +#define CTS_ENCL_EN BIT(3)
> +
> +/**
> + * DOC: MIPI DSI
> + *
> + */
> +
> +struct meson_dw_mipi_dsi {
> + struct drm_encoder encoder;
> + struct meson_drm *priv;
> + struct device *dev;
> + void __iomem *base;
> + struct phy *phy;
> + union phy_configure_opts phy_opts;
> + struct dw_mipi_dsi *dmd;
> + struct dw_mipi_dsi_plat_data pdata;
> + struct mipi_dsi_device *dsi_device;
> + unsigned long mode_flags;
> + struct clk *px_clk;
> +};
> +#define encoder_to_meson_dw_mipi_dsi(x) \
> + container_of(x, struct meson_dw_mipi_dsi, encoder)
> +
> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> + struct drm_display_mode *mode)
> +{
> + struct meson_drm *priv = mipi_dsi->priv;
> + unsigned int vclk2_div;
> + unsigned int pll_rate;
> + int ret;
> +
> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> + vclk2_div = pll_rate / (mode->clock * 1000);
> +
> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> + if (ret) {
> + pr_err("Failed to set DSI PLL rate %lu\n",
> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> +
> + return;
> + }
> +
> + /* Disable VCLK2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> +
> + /* Setup the VCLK2 divider value */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + VCLK2_DIV_MASK, (vclk2_div - 1));
> +
> + /* select gp0 for vclk2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> +
> + /* enable vclk2 gate */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> +
> + /* select vclk2_div1 for encl */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> +
> + /* release vclk2_div_reset and enable vclk2_div */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> +
> + /* enable vclk2_div1 gate */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> +
> + /* reset vclk2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SOFT_RESET, 0);
> +
> + /* enable encl_clk */
> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> + CTS_ENCL_EN, CTS_ENCL_EN);
> +
> + usleep_range(10000, 11000);
> +}
> +
> +static int dw_mipi_dsi_phy_init(void *priv_data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> +
> + phy_power_on(mipi_dsi->phy);
> +
> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> +
> + return 0;
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + phy_power_off(mipi_dsi->phy);
> +}
> +
> +static int
> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> + unsigned long mode_flags, u32 lanes, u32 format,
> + unsigned int *lane_mbps)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> +
> + return 0;
> +}
> +
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> + struct dw_mipi_dsi_dphy_timing *timing)
> +{
> + /* TOFIX handle other cases */
> +
> + timing->clk_lp2hs = 37;
> + timing->clk_hs2lp = 135;
> + timing->data_lp2hs = 50;
> + timing->data_hs2lp = 3;
> +
> + return 0;
> +}
> +
> +static int
> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> +{
> + *esc_clk_rate = 4; /* Mhz */
> +
> + return 0;
> +}
> +
> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> + .init = dw_mipi_dsi_phy_init,
> + .power_off = dw_mipi_dsi_phy_power_off,
> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> + .get_timing = dw_mipi_dsi_phy_get_timing,
> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> +};
> +
> +/* Encoder */
> +
> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> +{
> + drm_encoder_cleanup(encoder);
> +}
> +
> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> + .destroy = meson_mipi_dsi_encoder_destroy,
> +};
> +
> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> +
> + switch (mipi_dsi->dsi_device->format) {
> + case MIPI_DSI_FMT_RGB888:
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + case MIPI_DSI_FMT_RGB565:
> + default:
> + DRM_DEV_ERROR(mipi_dsi->dev,
> + "invalid pixel format %d\n",
> + mipi_dsi->dsi_device->format);
> + return -EINVAL;
> + };
> +
> + return 0;
> +}
> +
> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> +}
> +
> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> + writel_bits_relaxed(BIT(3), BIT(3),
> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> +}
> +
> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> +{
> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> +
> + writel_bits_relaxed(0xf, 0xf,
> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> + writel_bits_relaxed(0xf, 0,
> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> +
> + writel_bits_relaxed(0x3, 0x3,
> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> +
> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> +}
> +
> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> + unsigned int dpi_data_format, venc_data_width;
> + struct meson_drm *priv = mipi_dsi->priv;
> + int bpp;
> + u32 reg;
> +
> + mipi_dsi->mode_flags = mode->flags;
> +
> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> +
> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> + bpp, mipi_dsi->dsi_device->lanes,
> + &mipi_dsi->phy_opts.mipi_dphy);
> +
> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> +
> + switch (mipi_dsi->dsi_device->format) {
> + case MIPI_DSI_FMT_RGB888:
> + dpi_data_format = COLOR_24BIT;
> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + dpi_data_format = COLOR_18BIT_CFG_2;
> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + case MIPI_DSI_FMT_RGB565:
> + /* invalid */
> + break;
> + };
> +
> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> + meson_venc_mipi_dsi_mode_set(priv, mode);
> +
> + meson_encl_load_gamma(priv);
> +
> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> +
> + meson_dw_mipi_dsi_init(mipi_dsi);
> +
> + /* Configure Set color format for DPI register */
> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> + ~(0xf<<BIT_DPI_COLOR_MODE) &
> + ~(0x7<<BIT_IN_COLOR_MODE) &
> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> +
> + writel_relaxed(reg |
> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> + (venc_data_width << BIT_IN_COLOR_MODE) |
> + 0 << BIT_COMP0_SEL |
> + 1 << BIT_COMP1_SEL |
> + 2 << BIT_COMP2_SEL |
> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> +}
> +
> +static const struct drm_encoder_helper_funcs
> + meson_mipi_dsi_encoder_helper_funcs = {
> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> + .disable = meson_mipi_dsi_encoder_disable,
> + .enable = meson_mipi_dsi_encoder_enable,
> + .mode_set = meson_mipi_dsi_encoder_mode_set,
> +};
> +
> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> + struct drm_device *drm = data;
> + struct meson_drm *priv = drm->dev_private;
> + struct drm_encoder *encoder;
> + int ret;
> +
> + /* Check before if we are supposed to have a sub-device... */
> + if (!mipi_dsi->dsi_device)
> + return -EPROBE_DEFER;
> +
> + encoder = &mipi_dsi->encoder;
> + mipi_dsi->priv = priv;
> +
> + /* Encoder */
> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> + if (ret) {
> + dev_err(priv->dev, "Failed to init DSI encoder\n");
> + return ret;
> + }
> +
> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> +
> + encoder->possible_crtcs = BIT(0);
> +
> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> + return ret;
> + }
> +
> + phy_init(mipi_dsi->phy);
> +
> + return 0;
> +}
> +
> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> +
> + dw_mipi_dsi_remove(mipi_dsi->dmd);
> +
> + phy_exit(mipi_dsi->phy);
> +}
> +
> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> + .bind = meson_dw_mipi_dsi_bind,
> + .unbind = meson_dw_mipi_dsi_unbind,
> +};
> +
> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
> + struct mipi_dsi_device *device)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + mipi_dsi->dsi_device = device;
> +
> + return 0;
> +}
> +
> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
> + struct mipi_dsi_device *device)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + if (device == mipi_dsi->dsi_device)
> + mipi_dsi->dsi_device = NULL;
> + else
> + return -EINVAL;
> +
> + return 0;
> +}
> +
> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
> + .attach = meson_dw_mipi_dsi_host_attach,
> + .detach = meson_dw_mipi_dsi_host_detach,
> +};
> +
> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi;
> + struct reset_control *top_rst;
> + struct resource *res;
> + int ret;
> +
> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
> + if (!mipi_dsi)
> + return -ENOMEM;
> +
> + mipi_dsi->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(mipi_dsi->base))
> + return PTR_ERR(mipi_dsi->base);
> +
> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
> + if (IS_ERR(mipi_dsi->phy)) {
> + ret = PTR_ERR(mipi_dsi->phy);
> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
> + return ret;
> + }
> +
> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
> + if (IS_ERR(mipi_dsi->px_clk)) {
> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
> + return PTR_ERR(mipi_dsi->px_clk);
> + }
> +
> + /*
> + * We use a TOP reset signal because the APB reset signal
> + * is handled by the TOP control registers.
> + */
> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
> + if (IS_ERR(top_rst)) {
> + ret = PTR_ERR(top_rst);
> +
> + if (ret != -EPROBE_DEFER)
> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
> +
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(mipi_dsi->px_clk);
> + if (ret) {
> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
> + goto err_clkdisable;
> + }
> +
> + reset_control_assert(top_rst);
> + usleep_range(10, 20);
> + reset_control_deassert(top_rst);
> +
> + /* MIPI DSI Controller */
> +
> + mipi_dsi->pdata.base = mipi_dsi->base;
> + mipi_dsi->pdata.max_data_lanes = 4;
> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
> + mipi_dsi->pdata.priv_data = mipi_dsi;
> + platform_set_drvdata(pdev, mipi_dsi);
> +
> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
> + if (IS_ERR(mipi_dsi->dmd)) {
> + ret = PTR_ERR(mipi_dsi->dmd);
> + if (ret != -EPROBE_DEFER)
> + dev_err(&pdev->dev,
> + "Failed to probe dw_mipi_dsi: %d\n", ret);
> + goto err_clkdisable;
> + }
> +
> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> +
> +err_clkdisable:
> + clk_disable_unprepare(mipi_dsi->px_clk);
> +
> + return ret;
> +}
> +
> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
> +
> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> +
> + clk_disable_unprepare(mipi_dsi->px_clk);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
> +
> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
> + .probe = meson_dw_mipi_dsi_probe,
> + .remove = meson_dw_mipi_dsi_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = meson_dw_mipi_dsi_of_table,
> + },
> +};
> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
> +
> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> +MODULE_DESCRIPTION(DRIVER_DESC);
> +MODULE_LICENSE("GPL");
> --
> 2.22.0
>
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 8:43 ` Daniel Vetter
@ 2020-09-07 8:44 ` Daniel Vetter
2020-09-07 9:03 ` Neil Armstrong
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2020-09-07 8:44 UTC (permalink / raw)
To: Neil Armstrong, dri-devel, linux-amlogic, linux-kernel
On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
> > The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> > glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> > Amlogic SoCs.
> >
> > This adds support for the Glue managing the transceiver, mimicing the init flow provided
> > by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> > Analog PHY in the proper way.
> >
> > The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> > is derived and feeds the ENCL encoder and the VIU pixel reader.
> >
> > An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> > DW-MIPI-DSI transceiver.
> >
> > Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>
> More dw-hdmi drivers which aren't bridges but components, and the thing is
> still midlayer-y as heck :-/
*dw-dsi, but really they both work the same way and should both be fixed
...
>
> Can we try to fix this? There's a ton of this going on, and the more we
> add the old fashioned way the harder this gets to fix up for real.
> -Daniel
>
> > ---
> > drivers/gpu/drm/meson/Kconfig | 7 +
> > drivers/gpu/drm/meson/Makefile | 1 +
> > drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> > 3 files changed, 570 insertions(+)
> > create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >
> > diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> > index 9f9281dd49f8..385f6f23839b 100644
> > --- a/drivers/gpu/drm/meson/Kconfig
> > +++ b/drivers/gpu/drm/meson/Kconfig
> > @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> > default y if DRM_MESON
> > select DRM_DW_HDMI
> > imply DRM_DW_HDMI_I2S_AUDIO
> > +
> > +config DRM_MESON_DW_MIPI_DSI
> > + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> > + depends on DRM_MESON
> > + default y if DRM_MESON
> > + select DRM_DW_MIPI_DSI
> > + select GENERIC_PHY_MIPI_DPHY
> > diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> > index 28a519cdf66b..2cc870e91182 100644
> > --- a/drivers/gpu/drm/meson/Makefile
> > +++ b/drivers/gpu/drm/meson/Makefile
> > @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
> >
> > obj-$(CONFIG_DRM_MESON) += meson-drm.o
> > obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> > +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> > diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> > new file mode 100644
> > index 000000000000..bbe1294fce7c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> > @@ -0,0 +1,562 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +/*
> > + * Copyright (C) 2016 BayLibre, SAS
> > + * Author: Neil Armstrong <narmstrong@baylibre.com>
> > + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/kernel.h>
> > +#include <linux/module.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_graph.h>
> > +#include <linux/reset.h>
> > +#include <linux/phy/phy.h>
> > +
> > +#include <video/mipi_display.h>
> > +
> > +#include <drm/bridge/dw_mipi_dsi.h>
> > +#include <drm/drm_mipi_dsi.h>
> > +
> > +#include <drm/drm_atomic_helper.h>
> > +#include <drm/drm_device.h>
> > +#include <drm/drm_probe_helper.h>
> > +#include <drm/drm_print.h>
> > +
> > +#include "meson_drv.h"
> > +#include "meson_dw_mipi_dsi.h"
> > +#include "meson_registers.h"
> > +#include "meson_venc.h"
> > +
> > +#define DRIVER_NAME "meson-dw-mipi-dsi"
> > +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> > +
> > +/* MIPI DSI/VENC Color Format Definitions */
> > +#define MIPI_DSI_VENC_COLOR_30B 0x0
> > +#define MIPI_DSI_VENC_COLOR_24B 0x1
> > +#define MIPI_DSI_VENC_COLOR_18B 0x2
> > +#define MIPI_DSI_VENC_COLOR_16B 0x3
> > +
> > +#define COLOR_16BIT_CFG_1 0x0
> > +#define COLOR_16BIT_CFG_2 0x1
> > +#define COLOR_16BIT_CFG_3 0x2
> > +#define COLOR_18BIT_CFG_1 0x3
> > +#define COLOR_18BIT_CFG_2 0x4
> > +#define COLOR_24BIT 0x5
> > +#define COLOR_20BIT_LOOSE 0x6
> > +#define COLOR_24_BIT_YCBCR 0x7
> > +#define COLOR_16BIT_YCBCR 0x8
> > +#define COLOR_30BIT 0x9
> > +#define COLOR_36BIT 0xa
> > +#define COLOR_12BIT 0xb
> > +#define COLOR_RGB_111 0xc
> > +#define COLOR_RGB_332 0xd
> > +#define COLOR_RGB_444 0xe
> > +
> > +/* MIPI DSI Relative REGISTERs Definitions */
> > +/* For MIPI_DSI_TOP_CNTL */
> > +#define BIT_DPI_COLOR_MODE 20
> > +#define BIT_IN_COLOR_MODE 16
> > +#define BIT_CHROMA_SUBSAMPLE 14
> > +#define BIT_COMP2_SEL 12
> > +#define BIT_COMP1_SEL 10
> > +#define BIT_COMP0_SEL 8
> > +#define BIT_DE_POL 6
> > +#define BIT_HSYNC_POL 5
> > +#define BIT_VSYNC_POL 4
> > +#define BIT_DPICOLORM 3
> > +#define BIT_DPISHUTDN 2
> > +#define BIT_EDPITE_INTR_PULSE 1
> > +#define BIT_ERR_INTR_PULSE 0
> > +
> > +/* HHI Registers */
> > +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> > +#define VCLK2_DIV_MASK 0xff
> > +#define VCLK2_DIV_EN BIT(16)
> > +#define VCLK2_DIV_RESET BIT(17)
> > +#define CTS_ENCL_SEL_MASK (0xf << 12)
> > +#define CTS_ENCL_SEL_SHIFT 12
> > +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> > +#define VCLK2_EN BIT(19)
> > +#define VCLK2_SEL_MASK (0x7 << 16)
> > +#define VCLK2_SEL_SHIFT 16
> > +#define VCLK2_SOFT_RESET BIT(15)
> > +#define VCLK2_DIV1_EN BIT(0)
> > +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> > +#define CTS_ENCL_EN BIT(3)
> > +
> > +/**
> > + * DOC: MIPI DSI
> > + *
> > + */
> > +
> > +struct meson_dw_mipi_dsi {
> > + struct drm_encoder encoder;
> > + struct meson_drm *priv;
> > + struct device *dev;
> > + void __iomem *base;
> > + struct phy *phy;
> > + union phy_configure_opts phy_opts;
> > + struct dw_mipi_dsi *dmd;
> > + struct dw_mipi_dsi_plat_data pdata;
> > + struct mipi_dsi_device *dsi_device;
> > + unsigned long mode_flags;
> > + struct clk *px_clk;
> > +};
> > +#define encoder_to_meson_dw_mipi_dsi(x) \
> > + container_of(x, struct meson_dw_mipi_dsi, encoder)
> > +
> > +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> > + struct drm_display_mode *mode)
> > +{
> > + struct meson_drm *priv = mipi_dsi->priv;
> > + unsigned int vclk2_div;
> > + unsigned int pll_rate;
> > + int ret;
> > +
> > + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> > + vclk2_div = pll_rate / (mode->clock * 1000);
> > +
> > + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> > + if (ret) {
> > + pr_err("Failed to set DSI PLL rate %lu\n",
> > + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> > +
> > + return;
> > + }
> > +
> > + /* Disable VCLK2 */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> > +
> > + /* Setup the VCLK2 divider value */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> > + VCLK2_DIV_MASK, (vclk2_div - 1));
> > +
> > + /* select gp0 for vclk2 */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> > + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> > +
> > + /* enable vclk2 gate */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> > +
> > + /* select vclk2_div1 for encl */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> > + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> > +
> > + /* release vclk2_div_reset and enable vclk2_div */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> > + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> > +
> > + /* enable vclk2_div1 gate */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> > + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> > +
> > + /* reset vclk2 */
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> > + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> > + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> > + VCLK2_SOFT_RESET, 0);
> > +
> > + /* enable encl_clk */
> > + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> > + CTS_ENCL_EN, CTS_ENCL_EN);
> > +
> > + usleep_range(10000, 11000);
> > +}
> > +
> > +static int dw_mipi_dsi_phy_init(void *priv_data)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> > + struct meson_drm *priv = mipi_dsi->priv;
> > +
> > +
> > + phy_power_on(mipi_dsi->phy);
> > +
> > + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> > +
> > + return 0;
> > +}
> > +
> > +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> > +
> > + phy_power_off(mipi_dsi->phy);
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> > + unsigned long mode_flags, u32 lanes, u32 format,
> > + unsigned int *lane_mbps)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> > +
> > + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> > + struct dw_mipi_dsi_dphy_timing *timing)
> > +{
> > + /* TOFIX handle other cases */
> > +
> > + timing->clk_lp2hs = 37;
> > + timing->clk_hs2lp = 135;
> > + timing->data_lp2hs = 50;
> > + timing->data_hs2lp = 3;
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> > +{
> > + *esc_clk_rate = 4; /* Mhz */
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> > + .init = dw_mipi_dsi_phy_init,
> > + .power_off = dw_mipi_dsi_phy_power_off,
> > + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> > + .get_timing = dw_mipi_dsi_phy_get_timing,
> > + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> > +};
> > +
> > +/* Encoder */
> > +
> > +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> > +{
> > + drm_encoder_cleanup(encoder);
> > +}
> > +
> > +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> > + .destroy = meson_mipi_dsi_encoder_destroy,
> > +};
> > +
> > +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> > + struct drm_crtc_state *crtc_state,
> > + struct drm_connector_state *conn_state)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi =
> > + encoder_to_meson_dw_mipi_dsi(encoder);
> > +
> > + switch (mipi_dsi->dsi_device->format) {
> > + case MIPI_DSI_FMT_RGB888:
> > + break;
> > + case MIPI_DSI_FMT_RGB666:
> > + break;
> > + case MIPI_DSI_FMT_RGB666_PACKED:
> > + case MIPI_DSI_FMT_RGB565:
> > + default:
> > + DRM_DEV_ERROR(mipi_dsi->dev,
> > + "invalid pixel format %d\n",
> > + mipi_dsi->dsi_device->format);
> > + return -EINVAL;
> > + };
> > +
> > + return 0;
> > +}
> > +
> > +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi =
> > + encoder_to_meson_dw_mipi_dsi(encoder);
> > + struct meson_drm *priv = mipi_dsi->priv;
> > +
> > + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> > +}
> > +
> > +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi =
> > + encoder_to_meson_dw_mipi_dsi(encoder);
> > + struct meson_drm *priv = mipi_dsi->priv;
> > +
> > + writel_bits_relaxed(BIT(3), BIT(3),
> > + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> > + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> > +}
> > +
> > +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> > +{
> > + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> > + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> > +
> > + writel_bits_relaxed(0xf, 0xf,
> > + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> > + writel_bits_relaxed(0xf, 0,
> > + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> > +
> > + writel_bits_relaxed(0x3, 0x3,
> > + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> > +
> > + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> > +}
> > +
> > +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> > + struct drm_display_mode *mode,
> > + struct drm_display_mode *adjusted_mode)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> > + unsigned int dpi_data_format, venc_data_width;
> > + struct meson_drm *priv = mipi_dsi->priv;
> > + int bpp;
> > + u32 reg;
> > +
> > + mipi_dsi->mode_flags = mode->flags;
> > +
> > + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> > +
> > + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> > + bpp, mipi_dsi->dsi_device->lanes,
> > + &mipi_dsi->phy_opts.mipi_dphy);
> > +
> > + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> > +
> > + switch (mipi_dsi->dsi_device->format) {
> > + case MIPI_DSI_FMT_RGB888:
> > + dpi_data_format = COLOR_24BIT;
> > + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> > + break;
> > + case MIPI_DSI_FMT_RGB666:
> > + dpi_data_format = COLOR_18BIT_CFG_2;
> > + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> > + break;
> > + case MIPI_DSI_FMT_RGB666_PACKED:
> > + case MIPI_DSI_FMT_RGB565:
> > + /* invalid */
> > + break;
> > + };
> > +
> > + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> > + meson_venc_mipi_dsi_mode_set(priv, mode);
> > +
> > + meson_encl_load_gamma(priv);
> > +
> > + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> > +
> > + meson_dw_mipi_dsi_init(mipi_dsi);
> > +
> > + /* Configure Set color format for DPI register */
> > + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> > + ~(0xf<<BIT_DPI_COLOR_MODE) &
> > + ~(0x7<<BIT_IN_COLOR_MODE) &
> > + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> > +
> > + writel_relaxed(reg |
> > + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> > + (venc_data_width << BIT_IN_COLOR_MODE) |
> > + 0 << BIT_COMP0_SEL |
> > + 1 << BIT_COMP1_SEL |
> > + 2 << BIT_COMP2_SEL |
> > + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> > + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> > + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> > +}
> > +
> > +static const struct drm_encoder_helper_funcs
> > + meson_mipi_dsi_encoder_helper_funcs = {
> > + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> > + .disable = meson_mipi_dsi_encoder_disable,
> > + .enable = meson_mipi_dsi_encoder_enable,
> > + .mode_set = meson_mipi_dsi_encoder_mode_set,
> > +};
> > +
> > +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> > + void *data)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> > + struct drm_device *drm = data;
> > + struct meson_drm *priv = drm->dev_private;
> > + struct drm_encoder *encoder;
> > + int ret;
> > +
> > + /* Check before if we are supposed to have a sub-device... */
> > + if (!mipi_dsi->dsi_device)
> > + return -EPROBE_DEFER;
> > +
> > + encoder = &mipi_dsi->encoder;
> > + mipi_dsi->priv = priv;
> > +
> > + /* Encoder */
> > + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> > + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> > + if (ret) {
> > + dev_err(priv->dev, "Failed to init DSI encoder\n");
> > + return ret;
> > + }
> > +
> > + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> > +
> > + encoder->possible_crtcs = BIT(0);
> > +
> > + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> > + if (ret) {
> > + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + phy_init(mipi_dsi->phy);
> > +
> > + return 0;
> > +}
> > +
> > +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> > + void *data)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> > +
> > + dw_mipi_dsi_remove(mipi_dsi->dmd);
> > +
> > + phy_exit(mipi_dsi->phy);
> > +}
> > +
> > +static const struct component_ops meson_dw_mipi_dsi_ops = {
> > + .bind = meson_dw_mipi_dsi_bind,
> > + .unbind = meson_dw_mipi_dsi_unbind,
> > +};
> > +
> > +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
> > + struct mipi_dsi_device *device)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> > +
> > + mipi_dsi->dsi_device = device;
> > +
> > + return 0;
> > +}
> > +
> > +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
> > + struct mipi_dsi_device *device)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> > +
> > + if (device == mipi_dsi->dsi_device)
> > + mipi_dsi->dsi_device = NULL;
> > + else
> > + return -EINVAL;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
> > + .attach = meson_dw_mipi_dsi_host_attach,
> > + .detach = meson_dw_mipi_dsi_host_detach,
> > +};
> > +
> > +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi;
> > + struct reset_control *top_rst;
> > + struct resource *res;
> > + int ret;
> > +
> > + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
> > + if (!mipi_dsi)
> > + return -ENOMEM;
> > +
> > + mipi_dsi->dev = &pdev->dev;
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
> > + if (IS_ERR(mipi_dsi->base))
> > + return PTR_ERR(mipi_dsi->base);
> > +
> > + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
> > + if (IS_ERR(mipi_dsi->phy)) {
> > + ret = PTR_ERR(mipi_dsi->phy);
> > + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
> > + return ret;
> > + }
> > +
> > + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
> > + if (IS_ERR(mipi_dsi->px_clk)) {
> > + dev_err(&pdev->dev, "Unable to get PLL clk\n");
> > + return PTR_ERR(mipi_dsi->px_clk);
> > + }
> > +
> > + /*
> > + * We use a TOP reset signal because the APB reset signal
> > + * is handled by the TOP control registers.
> > + */
> > + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
> > + if (IS_ERR(top_rst)) {
> > + ret = PTR_ERR(top_rst);
> > +
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
> > +
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(mipi_dsi->px_clk);
> > + if (ret) {
> > + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
> > + goto err_clkdisable;
> > + }
> > +
> > + reset_control_assert(top_rst);
> > + usleep_range(10, 20);
> > + reset_control_deassert(top_rst);
> > +
> > + /* MIPI DSI Controller */
> > +
> > + mipi_dsi->pdata.base = mipi_dsi->base;
> > + mipi_dsi->pdata.max_data_lanes = 4;
> > + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
> > + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
> > + mipi_dsi->pdata.priv_data = mipi_dsi;
> > + platform_set_drvdata(pdev, mipi_dsi);
> > +
> > + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
> > + if (IS_ERR(mipi_dsi->dmd)) {
> > + ret = PTR_ERR(mipi_dsi->dmd);
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(&pdev->dev,
> > + "Failed to probe dw_mipi_dsi: %d\n", ret);
> > + goto err_clkdisable;
> > + }
> > +
> > + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> > +
> > +err_clkdisable:
> > + clk_disable_unprepare(mipi_dsi->px_clk);
> > +
> > + return ret;
> > +}
> > +
> > +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
> > +{
> > + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
> > +
> > + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> > +
> > + clk_disable_unprepare(mipi_dsi->px_clk);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
> > + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
> > + { }
> > +};
> > +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
> > +
> > +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
> > + .probe = meson_dw_mipi_dsi_probe,
> > + .remove = meson_dw_mipi_dsi_remove,
> > + .driver = {
> > + .name = DRIVER_NAME,
> > + .of_match_table = meson_dw_mipi_dsi_of_table,
> > + },
> > +};
> > +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
> > +
> > +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> > +MODULE_DESCRIPTION(DRIVER_DESC);
> > +MODULE_LICENSE("GPL");
> > --
> > 2.22.0
> >
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 8:44 ` Daniel Vetter
@ 2020-09-07 9:03 ` Neil Armstrong
2020-09-07 18:03 ` Daniel Vetter
0 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2020-09-07 9:03 UTC (permalink / raw)
To: dri-devel, linux-amlogic, linux-kernel
On 07/09/2020 10:44, Daniel Vetter wrote:
> On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
>> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>>> Amlogic SoCs.
>>>
>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
>>> Analog PHY in the proper way.
>>>
>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
>>>
>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
>>> DW-MIPI-DSI transceiver.
>>>
>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>
>> More dw-hdmi drivers which aren't bridges but components, and the thing is
>> still midlayer-y as heck :-/
>
> *dw-dsi, but really they both work the same way and should both be fixed
> ...
They are bridges but since they have platform-dependent code due to theirs's generic IP
nature, they need to be intanciated by components to sync with the platform code.
Neil
>
>>
>> Can we try to fix this? There's a ton of this going on, and the more we
>> add the old fashioned way the harder this gets to fix up for real.
>> -Daniel
>>
>>> ---
>>> drivers/gpu/drm/meson/Kconfig | 7 +
>>> drivers/gpu/drm/meson/Makefile | 1 +
>>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
>>> 3 files changed, 570 insertions(+)
>>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>
>>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
>>> index 9f9281dd49f8..385f6f23839b 100644
>>> --- a/drivers/gpu/drm/meson/Kconfig
>>> +++ b/drivers/gpu/drm/meson/Kconfig
>>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
>>> default y if DRM_MESON
>>> select DRM_DW_HDMI
>>> imply DRM_DW_HDMI_I2S_AUDIO
>>> +
>>> +config DRM_MESON_DW_MIPI_DSI
>>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
>>> + depends on DRM_MESON
>>> + default y if DRM_MESON
>>> + select DRM_DW_MIPI_DSI
>>> + select GENERIC_PHY_MIPI_DPHY
>>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
>>> index 28a519cdf66b..2cc870e91182 100644
>>> --- a/drivers/gpu/drm/meson/Makefile
>>> +++ b/drivers/gpu/drm/meson/Makefile
>>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
>>>
>>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
>>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
>>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
>>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>> new file mode 100644
>>> index 000000000000..bbe1294fce7c
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>> @@ -0,0 +1,562 @@
>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>> +/*
>>> + * Copyright (C) 2016 BayLibre, SAS
>>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
>>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>>> + */
>>> +
>>> +#include <linux/clk.h>
>>> +#include <linux/component.h>
>>> +#include <linux/kernel.h>
>>> +#include <linux/module.h>
>>> +#include <linux/of_device.h>
>>> +#include <linux/of_graph.h>
>>> +#include <linux/reset.h>
>>> +#include <linux/phy/phy.h>
>>> +
>>> +#include <video/mipi_display.h>
>>> +
>>> +#include <drm/bridge/dw_mipi_dsi.h>
>>> +#include <drm/drm_mipi_dsi.h>
>>> +
>>> +#include <drm/drm_atomic_helper.h>
>>> +#include <drm/drm_device.h>
>>> +#include <drm/drm_probe_helper.h>
>>> +#include <drm/drm_print.h>
>>> +
>>> +#include "meson_drv.h"
>>> +#include "meson_dw_mipi_dsi.h"
>>> +#include "meson_registers.h"
>>> +#include "meson_venc.h"
>>> +
>>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
>>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
>>> +
>>> +/* MIPI DSI/VENC Color Format Definitions */
>>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
>>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
>>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
>>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
>>> +
>>> +#define COLOR_16BIT_CFG_1 0x0
>>> +#define COLOR_16BIT_CFG_2 0x1
>>> +#define COLOR_16BIT_CFG_3 0x2
>>> +#define COLOR_18BIT_CFG_1 0x3
>>> +#define COLOR_18BIT_CFG_2 0x4
>>> +#define COLOR_24BIT 0x5
>>> +#define COLOR_20BIT_LOOSE 0x6
>>> +#define COLOR_24_BIT_YCBCR 0x7
>>> +#define COLOR_16BIT_YCBCR 0x8
>>> +#define COLOR_30BIT 0x9
>>> +#define COLOR_36BIT 0xa
>>> +#define COLOR_12BIT 0xb
>>> +#define COLOR_RGB_111 0xc
>>> +#define COLOR_RGB_332 0xd
>>> +#define COLOR_RGB_444 0xe
>>> +
>>> +/* MIPI DSI Relative REGISTERs Definitions */
>>> +/* For MIPI_DSI_TOP_CNTL */
>>> +#define BIT_DPI_COLOR_MODE 20
>>> +#define BIT_IN_COLOR_MODE 16
>>> +#define BIT_CHROMA_SUBSAMPLE 14
>>> +#define BIT_COMP2_SEL 12
>>> +#define BIT_COMP1_SEL 10
>>> +#define BIT_COMP0_SEL 8
>>> +#define BIT_DE_POL 6
>>> +#define BIT_HSYNC_POL 5
>>> +#define BIT_VSYNC_POL 4
>>> +#define BIT_DPICOLORM 3
>>> +#define BIT_DPISHUTDN 2
>>> +#define BIT_EDPITE_INTR_PULSE 1
>>> +#define BIT_ERR_INTR_PULSE 0
>>> +
>>> +/* HHI Registers */
>>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
>>> +#define VCLK2_DIV_MASK 0xff
>>> +#define VCLK2_DIV_EN BIT(16)
>>> +#define VCLK2_DIV_RESET BIT(17)
>>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
>>> +#define CTS_ENCL_SEL_SHIFT 12
>>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
>>> +#define VCLK2_EN BIT(19)
>>> +#define VCLK2_SEL_MASK (0x7 << 16)
>>> +#define VCLK2_SEL_SHIFT 16
>>> +#define VCLK2_SOFT_RESET BIT(15)
>>> +#define VCLK2_DIV1_EN BIT(0)
>>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
>>> +#define CTS_ENCL_EN BIT(3)
>>> +
>>> +/**
>>> + * DOC: MIPI DSI
>>> + *
>>> + */
>>> +
>>> +struct meson_dw_mipi_dsi {
>>> + struct drm_encoder encoder;
>>> + struct meson_drm *priv;
>>> + struct device *dev;
>>> + void __iomem *base;
>>> + struct phy *phy;
>>> + union phy_configure_opts phy_opts;
>>> + struct dw_mipi_dsi *dmd;
>>> + struct dw_mipi_dsi_plat_data pdata;
>>> + struct mipi_dsi_device *dsi_device;
>>> + unsigned long mode_flags;
>>> + struct clk *px_clk;
>>> +};
>>> +#define encoder_to_meson_dw_mipi_dsi(x) \
>>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
>>> +
>>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
>>> + struct drm_display_mode *mode)
>>> +{
>>> + struct meson_drm *priv = mipi_dsi->priv;
>>> + unsigned int vclk2_div;
>>> + unsigned int pll_rate;
>>> + int ret;
>>> +
>>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
>>> + vclk2_div = pll_rate / (mode->clock * 1000);
>>> +
>>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
>>> + if (ret) {
>>> + pr_err("Failed to set DSI PLL rate %lu\n",
>>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
>>> +
>>> + return;
>>> + }
>>> +
>>> + /* Disable VCLK2 */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
>>> +
>>> + /* Setup the VCLK2 divider value */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>> + VCLK2_DIV_MASK, (vclk2_div - 1));
>>> +
>>> + /* select gp0 for vclk2 */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
>>> +
>>> + /* enable vclk2 gate */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
>>> +
>>> + /* select vclk2_div1 for encl */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
>>> +
>>> + /* release vclk2_div_reset and enable vclk2_div */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
>>> +
>>> + /* enable vclk2_div1 gate */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
>>> +
>>> + /* reset vclk2 */
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>> + VCLK2_SOFT_RESET, 0);
>>> +
>>> + /* enable encl_clk */
>>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
>>> + CTS_ENCL_EN, CTS_ENCL_EN);
>>> +
>>> + usleep_range(10000, 11000);
>>> +}
>>> +
>>> +static int dw_mipi_dsi_phy_init(void *priv_data)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>> + struct meson_drm *priv = mipi_dsi->priv;
>>> +
>>> +
>>> + phy_power_on(mipi_dsi->phy);
>>> +
>>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>> +
>>> + phy_power_off(mipi_dsi->phy);
>>> +}
>>> +
>>> +static int
>>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>>> + unsigned long mode_flags, u32 lanes, u32 format,
>>> + unsigned int *lane_mbps)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>> +
>>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int
>>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>>> + struct dw_mipi_dsi_dphy_timing *timing)
>>> +{
>>> + /* TOFIX handle other cases */
>>> +
>>> + timing->clk_lp2hs = 37;
>>> + timing->clk_hs2lp = 135;
>>> + timing->data_lp2hs = 50;
>>> + timing->data_hs2lp = 3;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int
>>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
>>> +{
>>> + *esc_clk_rate = 4; /* Mhz */
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
>>> + .init = dw_mipi_dsi_phy_init,
>>> + .power_off = dw_mipi_dsi_phy_power_off,
>>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
>>> + .get_timing = dw_mipi_dsi_phy_get_timing,
>>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
>>> +};
>>> +
>>> +/* Encoder */
>>> +
>>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
>>> +{
>>> + drm_encoder_cleanup(encoder);
>>> +}
>>> +
>>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
>>> + .destroy = meson_mipi_dsi_encoder_destroy,
>>> +};
>>> +
>>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
>>> + struct drm_crtc_state *crtc_state,
>>> + struct drm_connector_state *conn_state)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>> +
>>> + switch (mipi_dsi->dsi_device->format) {
>>> + case MIPI_DSI_FMT_RGB888:
>>> + break;
>>> + case MIPI_DSI_FMT_RGB666:
>>> + break;
>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>> + case MIPI_DSI_FMT_RGB565:
>>> + default:
>>> + DRM_DEV_ERROR(mipi_dsi->dev,
>>> + "invalid pixel format %d\n",
>>> + mipi_dsi->dsi_device->format);
>>> + return -EINVAL;
>>> + };
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>> + struct meson_drm *priv = mipi_dsi->priv;
>>> +
>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>> +}
>>> +
>>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>> + struct meson_drm *priv = mipi_dsi->priv;
>>> +
>>> + writel_bits_relaxed(BIT(3), BIT(3),
>>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
>>> +}
>>> +
>>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
>>> +{
>>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>> +
>>> + writel_bits_relaxed(0xf, 0xf,
>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>> + writel_bits_relaxed(0xf, 0,
>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>> +
>>> + writel_bits_relaxed(0x3, 0x3,
>>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
>>> +
>>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
>>> +}
>>> +
>>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
>>> + struct drm_display_mode *mode,
>>> + struct drm_display_mode *adjusted_mode)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
>>> + unsigned int dpi_data_format, venc_data_width;
>>> + struct meson_drm *priv = mipi_dsi->priv;
>>> + int bpp;
>>> + u32 reg;
>>> +
>>> + mipi_dsi->mode_flags = mode->flags;
>>> +
>>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
>>> +
>>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
>>> + bpp, mipi_dsi->dsi_device->lanes,
>>> + &mipi_dsi->phy_opts.mipi_dphy);
>>> +
>>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
>>> +
>>> + switch (mipi_dsi->dsi_device->format) {
>>> + case MIPI_DSI_FMT_RGB888:
>>> + dpi_data_format = COLOR_24BIT;
>>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
>>> + break;
>>> + case MIPI_DSI_FMT_RGB666:
>>> + dpi_data_format = COLOR_18BIT_CFG_2;
>>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
>>> + break;
>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>> + case MIPI_DSI_FMT_RGB565:
>>> + /* invalid */
>>> + break;
>>> + };
>>> +
>>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
>>> + meson_venc_mipi_dsi_mode_set(priv, mode);
>>> +
>>> + meson_encl_load_gamma(priv);
>>> +
>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>> +
>>> + meson_dw_mipi_dsi_init(mipi_dsi);
>>> +
>>> + /* Configure Set color format for DPI register */
>>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
>>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
>>> + ~(0x7<<BIT_IN_COLOR_MODE) &
>>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
>>> +
>>> + writel_relaxed(reg |
>>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
>>> + (venc_data_width << BIT_IN_COLOR_MODE) |
>>> + 0 << BIT_COMP0_SEL |
>>> + 1 << BIT_COMP1_SEL |
>>> + 2 << BIT_COMP2_SEL |
>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>> +}
>>> +
>>> +static const struct drm_encoder_helper_funcs
>>> + meson_mipi_dsi_encoder_helper_funcs = {
>>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
>>> + .disable = meson_mipi_dsi_encoder_disable,
>>> + .enable = meson_mipi_dsi_encoder_enable,
>>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
>>> +};
>>> +
>>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
>>> + void *data)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>> + struct drm_device *drm = data;
>>> + struct meson_drm *priv = drm->dev_private;
>>> + struct drm_encoder *encoder;
>>> + int ret;
>>> +
>>> + /* Check before if we are supposed to have a sub-device... */
>>> + if (!mipi_dsi->dsi_device)
>>> + return -EPROBE_DEFER;
>>> +
>>> + encoder = &mipi_dsi->encoder;
>>> + mipi_dsi->priv = priv;
>>> +
>>> + /* Encoder */
>>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
>>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
>>> + if (ret) {
>>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
>>> + return ret;
>>> + }
>>> +
>>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
>>> +
>>> + encoder->possible_crtcs = BIT(0);
>>> +
>>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
>>> + if (ret) {
>>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + phy_init(mipi_dsi->phy);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
>>> + void *data)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>> +
>>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
>>> +
>>> + phy_exit(mipi_dsi->phy);
>>> +}
>>> +
>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
>>> + .bind = meson_dw_mipi_dsi_bind,
>>> + .unbind = meson_dw_mipi_dsi_unbind,
>>> +};
>>> +
>>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
>>> + struct mipi_dsi_device *device)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>> +
>>> + mipi_dsi->dsi_device = device;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
>>> + struct mipi_dsi_device *device)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>> +
>>> + if (device == mipi_dsi->dsi_device)
>>> + mipi_dsi->dsi_device = NULL;
>>> + else
>>> + return -EINVAL;
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
>>> + .attach = meson_dw_mipi_dsi_host_attach,
>>> + .detach = meson_dw_mipi_dsi_host_detach,
>>> +};
>>> +
>>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi;
>>> + struct reset_control *top_rst;
>>> + struct resource *res;
>>> + int ret;
>>> +
>>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
>>> + if (!mipi_dsi)
>>> + return -ENOMEM;
>>> +
>>> + mipi_dsi->dev = &pdev->dev;
>>> +
>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
>>> + if (IS_ERR(mipi_dsi->base))
>>> + return PTR_ERR(mipi_dsi->base);
>>> +
>>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
>>> + if (IS_ERR(mipi_dsi->phy)) {
>>> + ret = PTR_ERR(mipi_dsi->phy);
>>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
>>> + return ret;
>>> + }
>>> +
>>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
>>> + if (IS_ERR(mipi_dsi->px_clk)) {
>>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
>>> + return PTR_ERR(mipi_dsi->px_clk);
>>> + }
>>> +
>>> + /*
>>> + * We use a TOP reset signal because the APB reset signal
>>> + * is handled by the TOP control registers.
>>> + */
>>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
>>> + if (IS_ERR(top_rst)) {
>>> + ret = PTR_ERR(top_rst);
>>> +
>>> + if (ret != -EPROBE_DEFER)
>>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
>>> +
>>> + return ret;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
>>> + if (ret) {
>>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
>>> + goto err_clkdisable;
>>> + }
>>> +
>>> + reset_control_assert(top_rst);
>>> + usleep_range(10, 20);
>>> + reset_control_deassert(top_rst);
>>> +
>>> + /* MIPI DSI Controller */
>>> +
>>> + mipi_dsi->pdata.base = mipi_dsi->base;
>>> + mipi_dsi->pdata.max_data_lanes = 4;
>>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
>>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
>>> + mipi_dsi->pdata.priv_data = mipi_dsi;
>>> + platform_set_drvdata(pdev, mipi_dsi);
>>> +
>>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
>>> + if (IS_ERR(mipi_dsi->dmd)) {
>>> + ret = PTR_ERR(mipi_dsi->dmd);
>>> + if (ret != -EPROBE_DEFER)
>>> + dev_err(&pdev->dev,
>>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
>>> + goto err_clkdisable;
>>> + }
>>> +
>>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>> +
>>> +err_clkdisable:
>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>> +
>>> + return ret;
>>> +}
>>> +
>>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
>>> +{
>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
>>> +
>>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>> +
>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>> +
>>> + return 0;
>>> +}
>>> +
>>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
>>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
>>> + { }
>>> +};
>>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
>>> +
>>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
>>> + .probe = meson_dw_mipi_dsi_probe,
>>> + .remove = meson_dw_mipi_dsi_remove,
>>> + .driver = {
>>> + .name = DRIVER_NAME,
>>> + .of_match_table = meson_dw_mipi_dsi_of_table,
>>> + },
>>> +};
>>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
>>> +
>>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
>>> +MODULE_DESCRIPTION(DRIVER_DESC);
>>> +MODULE_LICENSE("GPL");
>>> --
>>> 2.22.0
>>>
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 9:03 ` Neil Armstrong
@ 2020-09-07 18:03 ` Daniel Vetter
2020-09-08 8:06 ` Neil Armstrong
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2020-09-07 18:03 UTC (permalink / raw)
To: Neil Armstrong; +Cc: dri-devel, linux-amlogic, linux-kernel
On Mon, Sep 07, 2020 at 11:03:29AM +0200, Neil Armstrong wrote:
> On 07/09/2020 10:44, Daniel Vetter wrote:
> > On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
> >> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
> >>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> >>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> >>> Amlogic SoCs.
> >>>
> >>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> >>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> >>> Analog PHY in the proper way.
> >>>
> >>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> >>> is derived and feeds the ENCL encoder and the VIU pixel reader.
> >>>
> >>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> >>> DW-MIPI-DSI transceiver.
> >>>
> >>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >>
> >> More dw-hdmi drivers which aren't bridges but components, and the thing is
> >> still midlayer-y as heck :-/
> >
> > *dw-dsi, but really they both work the same way and should both be fixed
> > ...
>
> They are bridges but since they have platform-dependent code due to theirs's generic IP
> nature, they need to be intanciated by components to sync with the platform code.
Yeah that's how it currently works, but there's not much reason why it
needs to work like that. That platform glue code can also be put behind
the drm_bridge abstraction, and we could use the normal dt based bridge
lookup like for everything else.
Afaiui the only reason dw-* bridge drivers work like that is because for
historical reasons we only had component.c at first, and none of the more
fancy dynamic bridge lookup. So would be really good to switch this all
over to a proper&clean bridge abstraction, and not leak everything around.
I've typed up what I think should be the way forward a few times already,
but thus far not even the todo.rst entry materialized:
https://lore.kernel.org/dri-devel/20200430135841.GE10381@phenom.ffwll.local/
If everyone is always about "not in my patch series" it'll never happen.
Cheers, Daniel
>
> Neil
>
> >
> >>
> >> Can we try to fix this? There's a ton of this going on, and the more we
> >> add the old fashioned way the harder this gets to fix up for real.
> >> -Daniel
> >>
> >>> ---
> >>> drivers/gpu/drm/meson/Kconfig | 7 +
> >>> drivers/gpu/drm/meson/Makefile | 1 +
> >>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> >>> 3 files changed, 570 insertions(+)
> >>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>
> >>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> >>> index 9f9281dd49f8..385f6f23839b 100644
> >>> --- a/drivers/gpu/drm/meson/Kconfig
> >>> +++ b/drivers/gpu/drm/meson/Kconfig
> >>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> >>> default y if DRM_MESON
> >>> select DRM_DW_HDMI
> >>> imply DRM_DW_HDMI_I2S_AUDIO
> >>> +
> >>> +config DRM_MESON_DW_MIPI_DSI
> >>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> >>> + depends on DRM_MESON
> >>> + default y if DRM_MESON
> >>> + select DRM_DW_MIPI_DSI
> >>> + select GENERIC_PHY_MIPI_DPHY
> >>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> >>> index 28a519cdf66b..2cc870e91182 100644
> >>> --- a/drivers/gpu/drm/meson/Makefile
> >>> +++ b/drivers/gpu/drm/meson/Makefile
> >>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
> >>>
> >>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
> >>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> >>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> >>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>> new file mode 100644
> >>> index 000000000000..bbe1294fce7c
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>> @@ -0,0 +1,562 @@
> >>> +// SPDX-License-Identifier: GPL-2.0-or-later
> >>> +/*
> >>> + * Copyright (C) 2016 BayLibre, SAS
> >>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> >>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> >>> + */
> >>> +
> >>> +#include <linux/clk.h>
> >>> +#include <linux/component.h>
> >>> +#include <linux/kernel.h>
> >>> +#include <linux/module.h>
> >>> +#include <linux/of_device.h>
> >>> +#include <linux/of_graph.h>
> >>> +#include <linux/reset.h>
> >>> +#include <linux/phy/phy.h>
> >>> +
> >>> +#include <video/mipi_display.h>
> >>> +
> >>> +#include <drm/bridge/dw_mipi_dsi.h>
> >>> +#include <drm/drm_mipi_dsi.h>
> >>> +
> >>> +#include <drm/drm_atomic_helper.h>
> >>> +#include <drm/drm_device.h>
> >>> +#include <drm/drm_probe_helper.h>
> >>> +#include <drm/drm_print.h>
> >>> +
> >>> +#include "meson_drv.h"
> >>> +#include "meson_dw_mipi_dsi.h"
> >>> +#include "meson_registers.h"
> >>> +#include "meson_venc.h"
> >>> +
> >>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
> >>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> >>> +
> >>> +/* MIPI DSI/VENC Color Format Definitions */
> >>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
> >>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
> >>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
> >>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
> >>> +
> >>> +#define COLOR_16BIT_CFG_1 0x0
> >>> +#define COLOR_16BIT_CFG_2 0x1
> >>> +#define COLOR_16BIT_CFG_3 0x2
> >>> +#define COLOR_18BIT_CFG_1 0x3
> >>> +#define COLOR_18BIT_CFG_2 0x4
> >>> +#define COLOR_24BIT 0x5
> >>> +#define COLOR_20BIT_LOOSE 0x6
> >>> +#define COLOR_24_BIT_YCBCR 0x7
> >>> +#define COLOR_16BIT_YCBCR 0x8
> >>> +#define COLOR_30BIT 0x9
> >>> +#define COLOR_36BIT 0xa
> >>> +#define COLOR_12BIT 0xb
> >>> +#define COLOR_RGB_111 0xc
> >>> +#define COLOR_RGB_332 0xd
> >>> +#define COLOR_RGB_444 0xe
> >>> +
> >>> +/* MIPI DSI Relative REGISTERs Definitions */
> >>> +/* For MIPI_DSI_TOP_CNTL */
> >>> +#define BIT_DPI_COLOR_MODE 20
> >>> +#define BIT_IN_COLOR_MODE 16
> >>> +#define BIT_CHROMA_SUBSAMPLE 14
> >>> +#define BIT_COMP2_SEL 12
> >>> +#define BIT_COMP1_SEL 10
> >>> +#define BIT_COMP0_SEL 8
> >>> +#define BIT_DE_POL 6
> >>> +#define BIT_HSYNC_POL 5
> >>> +#define BIT_VSYNC_POL 4
> >>> +#define BIT_DPICOLORM 3
> >>> +#define BIT_DPISHUTDN 2
> >>> +#define BIT_EDPITE_INTR_PULSE 1
> >>> +#define BIT_ERR_INTR_PULSE 0
> >>> +
> >>> +/* HHI Registers */
> >>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> >>> +#define VCLK2_DIV_MASK 0xff
> >>> +#define VCLK2_DIV_EN BIT(16)
> >>> +#define VCLK2_DIV_RESET BIT(17)
> >>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
> >>> +#define CTS_ENCL_SEL_SHIFT 12
> >>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> >>> +#define VCLK2_EN BIT(19)
> >>> +#define VCLK2_SEL_MASK (0x7 << 16)
> >>> +#define VCLK2_SEL_SHIFT 16
> >>> +#define VCLK2_SOFT_RESET BIT(15)
> >>> +#define VCLK2_DIV1_EN BIT(0)
> >>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> >>> +#define CTS_ENCL_EN BIT(3)
> >>> +
> >>> +/**
> >>> + * DOC: MIPI DSI
> >>> + *
> >>> + */
> >>> +
> >>> +struct meson_dw_mipi_dsi {
> >>> + struct drm_encoder encoder;
> >>> + struct meson_drm *priv;
> >>> + struct device *dev;
> >>> + void __iomem *base;
> >>> + struct phy *phy;
> >>> + union phy_configure_opts phy_opts;
> >>> + struct dw_mipi_dsi *dmd;
> >>> + struct dw_mipi_dsi_plat_data pdata;
> >>> + struct mipi_dsi_device *dsi_device;
> >>> + unsigned long mode_flags;
> >>> + struct clk *px_clk;
> >>> +};
> >>> +#define encoder_to_meson_dw_mipi_dsi(x) \
> >>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
> >>> +
> >>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> >>> + struct drm_display_mode *mode)
> >>> +{
> >>> + struct meson_drm *priv = mipi_dsi->priv;
> >>> + unsigned int vclk2_div;
> >>> + unsigned int pll_rate;
> >>> + int ret;
> >>> +
> >>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> >>> + vclk2_div = pll_rate / (mode->clock * 1000);
> >>> +
> >>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> >>> + if (ret) {
> >>> + pr_err("Failed to set DSI PLL rate %lu\n",
> >>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> >>> +
> >>> + return;
> >>> + }
> >>> +
> >>> + /* Disable VCLK2 */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> >>> +
> >>> + /* Setup the VCLK2 divider value */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>> + VCLK2_DIV_MASK, (vclk2_div - 1));
> >>> +
> >>> + /* select gp0 for vclk2 */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> >>> +
> >>> + /* enable vclk2 gate */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> >>> +
> >>> + /* select vclk2_div1 for encl */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> >>> +
> >>> + /* release vclk2_div_reset and enable vclk2_div */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> >>> +
> >>> + /* enable vclk2_div1 gate */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> >>> +
> >>> + /* reset vclk2 */
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> >>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>> + VCLK2_SOFT_RESET, 0);
> >>> +
> >>> + /* enable encl_clk */
> >>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> >>> + CTS_ENCL_EN, CTS_ENCL_EN);
> >>> +
> >>> + usleep_range(10000, 11000);
> >>> +}
> >>> +
> >>> +static int dw_mipi_dsi_phy_init(void *priv_data)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>> + struct meson_drm *priv = mipi_dsi->priv;
> >>> +
> >>> +
> >>> + phy_power_on(mipi_dsi->phy);
> >>> +
> >>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>> +
> >>> + phy_power_off(mipi_dsi->phy);
> >>> +}
> >>> +
> >>> +static int
> >>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> >>> + unsigned long mode_flags, u32 lanes, u32 format,
> >>> + unsigned int *lane_mbps)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>> +
> >>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int
> >>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> >>> + struct dw_mipi_dsi_dphy_timing *timing)
> >>> +{
> >>> + /* TOFIX handle other cases */
> >>> +
> >>> + timing->clk_lp2hs = 37;
> >>> + timing->clk_hs2lp = 135;
> >>> + timing->data_lp2hs = 50;
> >>> + timing->data_hs2lp = 3;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int
> >>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> >>> +{
> >>> + *esc_clk_rate = 4; /* Mhz */
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> >>> + .init = dw_mipi_dsi_phy_init,
> >>> + .power_off = dw_mipi_dsi_phy_power_off,
> >>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> >>> + .get_timing = dw_mipi_dsi_phy_get_timing,
> >>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> >>> +};
> >>> +
> >>> +/* Encoder */
> >>> +
> >>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> >>> +{
> >>> + drm_encoder_cleanup(encoder);
> >>> +}
> >>> +
> >>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> >>> + .destroy = meson_mipi_dsi_encoder_destroy,
> >>> +};
> >>> +
> >>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> >>> + struct drm_crtc_state *crtc_state,
> >>> + struct drm_connector_state *conn_state)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>> +
> >>> + switch (mipi_dsi->dsi_device->format) {
> >>> + case MIPI_DSI_FMT_RGB888:
> >>> + break;
> >>> + case MIPI_DSI_FMT_RGB666:
> >>> + break;
> >>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>> + case MIPI_DSI_FMT_RGB565:
> >>> + default:
> >>> + DRM_DEV_ERROR(mipi_dsi->dev,
> >>> + "invalid pixel format %d\n",
> >>> + mipi_dsi->dsi_device->format);
> >>> + return -EINVAL;
> >>> + };
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>> + struct meson_drm *priv = mipi_dsi->priv;
> >>> +
> >>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>> +}
> >>> +
> >>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>> + struct meson_drm *priv = mipi_dsi->priv;
> >>> +
> >>> + writel_bits_relaxed(BIT(3), BIT(3),
> >>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> >>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> >>> +}
> >>> +
> >>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> >>> +{
> >>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> >>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>> +
> >>> + writel_bits_relaxed(0xf, 0xf,
> >>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>> + writel_bits_relaxed(0xf, 0,
> >>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>> +
> >>> + writel_bits_relaxed(0x3, 0x3,
> >>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> >>> +
> >>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> >>> +}
> >>> +
> >>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> >>> + struct drm_display_mode *mode,
> >>> + struct drm_display_mode *adjusted_mode)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> >>> + unsigned int dpi_data_format, venc_data_width;
> >>> + struct meson_drm *priv = mipi_dsi->priv;
> >>> + int bpp;
> >>> + u32 reg;
> >>> +
> >>> + mipi_dsi->mode_flags = mode->flags;
> >>> +
> >>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> >>> +
> >>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> >>> + bpp, mipi_dsi->dsi_device->lanes,
> >>> + &mipi_dsi->phy_opts.mipi_dphy);
> >>> +
> >>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> >>> +
> >>> + switch (mipi_dsi->dsi_device->format) {
> >>> + case MIPI_DSI_FMT_RGB888:
> >>> + dpi_data_format = COLOR_24BIT;
> >>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> >>> + break;
> >>> + case MIPI_DSI_FMT_RGB666:
> >>> + dpi_data_format = COLOR_18BIT_CFG_2;
> >>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> >>> + break;
> >>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>> + case MIPI_DSI_FMT_RGB565:
> >>> + /* invalid */
> >>> + break;
> >>> + };
> >>> +
> >>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> >>> + meson_venc_mipi_dsi_mode_set(priv, mode);
> >>> +
> >>> + meson_encl_load_gamma(priv);
> >>> +
> >>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>> +
> >>> + meson_dw_mipi_dsi_init(mipi_dsi);
> >>> +
> >>> + /* Configure Set color format for DPI register */
> >>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> >>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
> >>> + ~(0x7<<BIT_IN_COLOR_MODE) &
> >>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> >>> +
> >>> + writel_relaxed(reg |
> >>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> >>> + (venc_data_width << BIT_IN_COLOR_MODE) |
> >>> + 0 << BIT_COMP0_SEL |
> >>> + 1 << BIT_COMP1_SEL |
> >>> + 2 << BIT_COMP2_SEL |
> >>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> >>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> >>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>> +}
> >>> +
> >>> +static const struct drm_encoder_helper_funcs
> >>> + meson_mipi_dsi_encoder_helper_funcs = {
> >>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> >>> + .disable = meson_mipi_dsi_encoder_disable,
> >>> + .enable = meson_mipi_dsi_encoder_enable,
> >>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
> >>> +};
> >>> +
> >>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> >>> + void *data)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>> + struct drm_device *drm = data;
> >>> + struct meson_drm *priv = drm->dev_private;
> >>> + struct drm_encoder *encoder;
> >>> + int ret;
> >>> +
> >>> + /* Check before if we are supposed to have a sub-device... */
> >>> + if (!mipi_dsi->dsi_device)
> >>> + return -EPROBE_DEFER;
> >>> +
> >>> + encoder = &mipi_dsi->encoder;
> >>> + mipi_dsi->priv = priv;
> >>> +
> >>> + /* Encoder */
> >>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> >>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> >>> + if (ret) {
> >>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
> >>> + return ret;
> >>> + }
> >>> +
> >>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> >>> +
> >>> + encoder->possible_crtcs = BIT(0);
> >>> +
> >>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> >>> + if (ret) {
> >>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + phy_init(mipi_dsi->phy);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> >>> + void *data)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>> +
> >>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
> >>> +
> >>> + phy_exit(mipi_dsi->phy);
> >>> +}
> >>> +
> >>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> >>> + .bind = meson_dw_mipi_dsi_bind,
> >>> + .unbind = meson_dw_mipi_dsi_unbind,
> >>> +};
> >>> +
> >>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
> >>> + struct mipi_dsi_device *device)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>> +
> >>> + mipi_dsi->dsi_device = device;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
> >>> + struct mipi_dsi_device *device)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>> +
> >>> + if (device == mipi_dsi->dsi_device)
> >>> + mipi_dsi->dsi_device = NULL;
> >>> + else
> >>> + return -EINVAL;
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
> >>> + .attach = meson_dw_mipi_dsi_host_attach,
> >>> + .detach = meson_dw_mipi_dsi_host_detach,
> >>> +};
> >>> +
> >>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi;
> >>> + struct reset_control *top_rst;
> >>> + struct resource *res;
> >>> + int ret;
> >>> +
> >>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
> >>> + if (!mipi_dsi)
> >>> + return -ENOMEM;
> >>> +
> >>> + mipi_dsi->dev = &pdev->dev;
> >>> +
> >>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
> >>> + if (IS_ERR(mipi_dsi->base))
> >>> + return PTR_ERR(mipi_dsi->base);
> >>> +
> >>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
> >>> + if (IS_ERR(mipi_dsi->phy)) {
> >>> + ret = PTR_ERR(mipi_dsi->phy);
> >>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
> >>> + return ret;
> >>> + }
> >>> +
> >>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
> >>> + if (IS_ERR(mipi_dsi->px_clk)) {
> >>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
> >>> + return PTR_ERR(mipi_dsi->px_clk);
> >>> + }
> >>> +
> >>> + /*
> >>> + * We use a TOP reset signal because the APB reset signal
> >>> + * is handled by the TOP control registers.
> >>> + */
> >>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
> >>> + if (IS_ERR(top_rst)) {
> >>> + ret = PTR_ERR(top_rst);
> >>> +
> >>> + if (ret != -EPROBE_DEFER)
> >>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
> >>> +
> >>> + return ret;
> >>> + }
> >>> +
> >>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
> >>> + if (ret) {
> >>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
> >>> + goto err_clkdisable;
> >>> + }
> >>> +
> >>> + reset_control_assert(top_rst);
> >>> + usleep_range(10, 20);
> >>> + reset_control_deassert(top_rst);
> >>> +
> >>> + /* MIPI DSI Controller */
> >>> +
> >>> + mipi_dsi->pdata.base = mipi_dsi->base;
> >>> + mipi_dsi->pdata.max_data_lanes = 4;
> >>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
> >>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
> >>> + mipi_dsi->pdata.priv_data = mipi_dsi;
> >>> + platform_set_drvdata(pdev, mipi_dsi);
> >>> +
> >>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
> >>> + if (IS_ERR(mipi_dsi->dmd)) {
> >>> + ret = PTR_ERR(mipi_dsi->dmd);
> >>> + if (ret != -EPROBE_DEFER)
> >>> + dev_err(&pdev->dev,
> >>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
> >>> + goto err_clkdisable;
> >>> + }
> >>> +
> >>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>> +
> >>> +err_clkdisable:
> >>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>> +
> >>> + return ret;
> >>> +}
> >>> +
> >>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
> >>> +{
> >>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
> >>> +
> >>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>> +
> >>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>> +
> >>> + return 0;
> >>> +}
> >>> +
> >>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
> >>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
> >>> + { }
> >>> +};
> >>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
> >>> +
> >>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
> >>> + .probe = meson_dw_mipi_dsi_probe,
> >>> + .remove = meson_dw_mipi_dsi_remove,
> >>> + .driver = {
> >>> + .name = DRIVER_NAME,
> >>> + .of_match_table = meson_dw_mipi_dsi_of_table,
> >>> + },
> >>> +};
> >>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
> >>> +
> >>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> >>> +MODULE_DESCRIPTION(DRIVER_DESC);
> >>> +MODULE_LICENSE("GPL");
> >>> --
> >>> 2.22.0
> >>>
> >>
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> http://blog.ffwll.ch
> >
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 18:03 ` Daniel Vetter
@ 2020-09-08 8:06 ` Neil Armstrong
2020-09-08 8:46 ` Daniel Vetter
0 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2020-09-08 8:06 UTC (permalink / raw)
To: dri-devel, linux-amlogic, linux-kernel
Hi,
On 07/09/2020 20:03, Daniel Vetter wrote:
> On Mon, Sep 07, 2020 at 11:03:29AM +0200, Neil Armstrong wrote:
>> On 07/09/2020 10:44, Daniel Vetter wrote:
>>> On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
>>>> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
>>>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>>>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>>>>> Amlogic SoCs.
>>>>>
>>>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
>>>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
>>>>> Analog PHY in the proper way.
>>>>>
>>>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
>>>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
>>>>>
>>>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
>>>>> DW-MIPI-DSI transceiver.
>>>>>
>>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>>>
>>>> More dw-hdmi drivers which aren't bridges but components, and the thing is
>>>> still midlayer-y as heck :-/
>>>
>>> *dw-dsi, but really they both work the same way and should both be fixed
>>> ...
>>
>> They are bridges but since they have platform-dependent code due to theirs's generic IP
>> nature, they need to be intanciated by components to sync with the platform code.
>
> Yeah that's how it currently works, but there's not much reason why it
> needs to work like that. That platform glue code can also be put behind
> the drm_bridge abstraction, and we could use the normal dt based bridge
> lookup like for everything else.
>
> Afaiui the only reason dw-* bridge drivers work like that is because for
> historical reasons we only had component.c at first, and none of the more
> fancy dynamic bridge lookup. So would be really good to switch this all
> over to a proper&clean bridge abstraction, and not leak everything around.
Does it mean we should avoit using components, right ?
>
> I've typed up what I think should be the way forward a few times already,
> but thus far not even the todo.rst entry materialized:
>
> https://lore.kernel.org/dri-devel/20200430135841.GE10381@phenom.ffwll.local/
>
> If everyone is always about "not in my patch series" it'll never happen.
Today, the dw-mipi-dsi and dw-mipi-hdmi has mandatory callbacks to implement
vendor specific features, like :
- hdmi/dsi phy handling when mixed into the glue/custom/synopsys but with platform specific values
- platform specific mode validation
- hpd setup => could use laurent's work here with no_connector, but how do we handle rxsense ???
- dsi timings/lane mbps ? these are platform phy specific
For amlogic, I can split the "component" code handling venc/vclk into a primary bridge and add a
secondary driver only handling the glue around dw-mipi-dsi/dw-mipi-hdmi, would that be a good start ?
Neil
>
> Cheers, Daniel
>
>
>>
>> Neil
>>
>>>
>>>>
>>>> Can we try to fix this? There's a ton of this going on, and the more we
>>>> add the old fashioned way the harder this gets to fix up for real.
>>>> -Daniel
>>>>
>>>>> ---
>>>>> drivers/gpu/drm/meson/Kconfig | 7 +
>>>>> drivers/gpu/drm/meson/Makefile | 1 +
>>>>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
>>>>> 3 files changed, 570 insertions(+)
>>>>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>>
>>>>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
>>>>> index 9f9281dd49f8..385f6f23839b 100644
>>>>> --- a/drivers/gpu/drm/meson/Kconfig
>>>>> +++ b/drivers/gpu/drm/meson/Kconfig
>>>>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
>>>>> default y if DRM_MESON
>>>>> select DRM_DW_HDMI
>>>>> imply DRM_DW_HDMI_I2S_AUDIO
>>>>> +
>>>>> +config DRM_MESON_DW_MIPI_DSI
>>>>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
>>>>> + depends on DRM_MESON
>>>>> + default y if DRM_MESON
>>>>> + select DRM_DW_MIPI_DSI
>>>>> + select GENERIC_PHY_MIPI_DPHY
>>>>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
>>>>> index 28a519cdf66b..2cc870e91182 100644
>>>>> --- a/drivers/gpu/drm/meson/Makefile
>>>>> +++ b/drivers/gpu/drm/meson/Makefile
>>>>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
>>>>>
>>>>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
>>>>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
>>>>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
>>>>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>> new file mode 100644
>>>>> index 000000000000..bbe1294fce7c
>>>>> --- /dev/null
>>>>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>> @@ -0,0 +1,562 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>>>> +/*
>>>>> + * Copyright (C) 2016 BayLibre, SAS
>>>>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
>>>>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>>>>> + */
>>>>> +
>>>>> +#include <linux/clk.h>
>>>>> +#include <linux/component.h>
>>>>> +#include <linux/kernel.h>
>>>>> +#include <linux/module.h>
>>>>> +#include <linux/of_device.h>
>>>>> +#include <linux/of_graph.h>
>>>>> +#include <linux/reset.h>
>>>>> +#include <linux/phy/phy.h>
>>>>> +
>>>>> +#include <video/mipi_display.h>
>>>>> +
>>>>> +#include <drm/bridge/dw_mipi_dsi.h>
>>>>> +#include <drm/drm_mipi_dsi.h>
>>>>> +
>>>>> +#include <drm/drm_atomic_helper.h>
>>>>> +#include <drm/drm_device.h>
>>>>> +#include <drm/drm_probe_helper.h>
>>>>> +#include <drm/drm_print.h>
>>>>> +
>>>>> +#include "meson_drv.h"
>>>>> +#include "meson_dw_mipi_dsi.h"
>>>>> +#include "meson_registers.h"
>>>>> +#include "meson_venc.h"
>>>>> +
>>>>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
>>>>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
>>>>> +
>>>>> +/* MIPI DSI/VENC Color Format Definitions */
>>>>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
>>>>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
>>>>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
>>>>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
>>>>> +
>>>>> +#define COLOR_16BIT_CFG_1 0x0
>>>>> +#define COLOR_16BIT_CFG_2 0x1
>>>>> +#define COLOR_16BIT_CFG_3 0x2
>>>>> +#define COLOR_18BIT_CFG_1 0x3
>>>>> +#define COLOR_18BIT_CFG_2 0x4
>>>>> +#define COLOR_24BIT 0x5
>>>>> +#define COLOR_20BIT_LOOSE 0x6
>>>>> +#define COLOR_24_BIT_YCBCR 0x7
>>>>> +#define COLOR_16BIT_YCBCR 0x8
>>>>> +#define COLOR_30BIT 0x9
>>>>> +#define COLOR_36BIT 0xa
>>>>> +#define COLOR_12BIT 0xb
>>>>> +#define COLOR_RGB_111 0xc
>>>>> +#define COLOR_RGB_332 0xd
>>>>> +#define COLOR_RGB_444 0xe
>>>>> +
>>>>> +/* MIPI DSI Relative REGISTERs Definitions */
>>>>> +/* For MIPI_DSI_TOP_CNTL */
>>>>> +#define BIT_DPI_COLOR_MODE 20
>>>>> +#define BIT_IN_COLOR_MODE 16
>>>>> +#define BIT_CHROMA_SUBSAMPLE 14
>>>>> +#define BIT_COMP2_SEL 12
>>>>> +#define BIT_COMP1_SEL 10
>>>>> +#define BIT_COMP0_SEL 8
>>>>> +#define BIT_DE_POL 6
>>>>> +#define BIT_HSYNC_POL 5
>>>>> +#define BIT_VSYNC_POL 4
>>>>> +#define BIT_DPICOLORM 3
>>>>> +#define BIT_DPISHUTDN 2
>>>>> +#define BIT_EDPITE_INTR_PULSE 1
>>>>> +#define BIT_ERR_INTR_PULSE 0
>>>>> +
>>>>> +/* HHI Registers */
>>>>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
>>>>> +#define VCLK2_DIV_MASK 0xff
>>>>> +#define VCLK2_DIV_EN BIT(16)
>>>>> +#define VCLK2_DIV_RESET BIT(17)
>>>>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
>>>>> +#define CTS_ENCL_SEL_SHIFT 12
>>>>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
>>>>> +#define VCLK2_EN BIT(19)
>>>>> +#define VCLK2_SEL_MASK (0x7 << 16)
>>>>> +#define VCLK2_SEL_SHIFT 16
>>>>> +#define VCLK2_SOFT_RESET BIT(15)
>>>>> +#define VCLK2_DIV1_EN BIT(0)
>>>>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
>>>>> +#define CTS_ENCL_EN BIT(3)
>>>>> +
>>>>> +/**
>>>>> + * DOC: MIPI DSI
>>>>> + *
>>>>> + */
>>>>> +
>>>>> +struct meson_dw_mipi_dsi {
>>>>> + struct drm_encoder encoder;
>>>>> + struct meson_drm *priv;
>>>>> + struct device *dev;
>>>>> + void __iomem *base;
>>>>> + struct phy *phy;
>>>>> + union phy_configure_opts phy_opts;
>>>>> + struct dw_mipi_dsi *dmd;
>>>>> + struct dw_mipi_dsi_plat_data pdata;
>>>>> + struct mipi_dsi_device *dsi_device;
>>>>> + unsigned long mode_flags;
>>>>> + struct clk *px_clk;
>>>>> +};
>>>>> +#define encoder_to_meson_dw_mipi_dsi(x) \
>>>>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
>>>>> +
>>>>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
>>>>> + struct drm_display_mode *mode)
>>>>> +{
>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>> + unsigned int vclk2_div;
>>>>> + unsigned int pll_rate;
>>>>> + int ret;
>>>>> +
>>>>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
>>>>> + vclk2_div = pll_rate / (mode->clock * 1000);
>>>>> +
>>>>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
>>>>> + if (ret) {
>>>>> + pr_err("Failed to set DSI PLL rate %lu\n",
>>>>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
>>>>> +
>>>>> + return;
>>>>> + }
>>>>> +
>>>>> + /* Disable VCLK2 */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
>>>>> +
>>>>> + /* Setup the VCLK2 divider value */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>> + VCLK2_DIV_MASK, (vclk2_div - 1));
>>>>> +
>>>>> + /* select gp0 for vclk2 */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
>>>>> +
>>>>> + /* enable vclk2 gate */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
>>>>> +
>>>>> + /* select vclk2_div1 for encl */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
>>>>> +
>>>>> + /* release vclk2_div_reset and enable vclk2_div */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
>>>>> +
>>>>> + /* enable vclk2_div1 gate */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
>>>>> +
>>>>> + /* reset vclk2 */
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>> + VCLK2_SOFT_RESET, 0);
>>>>> +
>>>>> + /* enable encl_clk */
>>>>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
>>>>> + CTS_ENCL_EN, CTS_ENCL_EN);
>>>>> +
>>>>> + usleep_range(10000, 11000);
>>>>> +}
>>>>> +
>>>>> +static int dw_mipi_dsi_phy_init(void *priv_data)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>> +
>>>>> +
>>>>> + phy_power_on(mipi_dsi->phy);
>>>>> +
>>>>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>> +
>>>>> + phy_power_off(mipi_dsi->phy);
>>>>> +}
>>>>> +
>>>>> +static int
>>>>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>>>>> + unsigned long mode_flags, u32 lanes, u32 format,
>>>>> + unsigned int *lane_mbps)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>> +
>>>>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int
>>>>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>>>>> + struct dw_mipi_dsi_dphy_timing *timing)
>>>>> +{
>>>>> + /* TOFIX handle other cases */
>>>>> +
>>>>> + timing->clk_lp2hs = 37;
>>>>> + timing->clk_hs2lp = 135;
>>>>> + timing->data_lp2hs = 50;
>>>>> + timing->data_hs2lp = 3;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int
>>>>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
>>>>> +{
>>>>> + *esc_clk_rate = 4; /* Mhz */
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
>>>>> + .init = dw_mipi_dsi_phy_init,
>>>>> + .power_off = dw_mipi_dsi_phy_power_off,
>>>>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
>>>>> + .get_timing = dw_mipi_dsi_phy_get_timing,
>>>>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
>>>>> +};
>>>>> +
>>>>> +/* Encoder */
>>>>> +
>>>>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
>>>>> +{
>>>>> + drm_encoder_cleanup(encoder);
>>>>> +}
>>>>> +
>>>>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
>>>>> + .destroy = meson_mipi_dsi_encoder_destroy,
>>>>> +};
>>>>> +
>>>>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
>>>>> + struct drm_crtc_state *crtc_state,
>>>>> + struct drm_connector_state *conn_state)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>> +
>>>>> + switch (mipi_dsi->dsi_device->format) {
>>>>> + case MIPI_DSI_FMT_RGB888:
>>>>> + break;
>>>>> + case MIPI_DSI_FMT_RGB666:
>>>>> + break;
>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>>>> + case MIPI_DSI_FMT_RGB565:
>>>>> + default:
>>>>> + DRM_DEV_ERROR(mipi_dsi->dev,
>>>>> + "invalid pixel format %d\n",
>>>>> + mipi_dsi->dsi_device->format);
>>>>> + return -EINVAL;
>>>>> + };
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>> +
>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>> +}
>>>>> +
>>>>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>> +
>>>>> + writel_bits_relaxed(BIT(3), BIT(3),
>>>>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
>>>>> +}
>>>>> +
>>>>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
>>>>> +{
>>>>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>>>> +
>>>>> + writel_bits_relaxed(0xf, 0xf,
>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>>>> + writel_bits_relaxed(0xf, 0,
>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>>>> +
>>>>> + writel_bits_relaxed(0x3, 0x3,
>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
>>>>> +
>>>>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
>>>>> +}
>>>>> +
>>>>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
>>>>> + struct drm_display_mode *mode,
>>>>> + struct drm_display_mode *adjusted_mode)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
>>>>> + unsigned int dpi_data_format, venc_data_width;
>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>> + int bpp;
>>>>> + u32 reg;
>>>>> +
>>>>> + mipi_dsi->mode_flags = mode->flags;
>>>>> +
>>>>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
>>>>> +
>>>>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
>>>>> + bpp, mipi_dsi->dsi_device->lanes,
>>>>> + &mipi_dsi->phy_opts.mipi_dphy);
>>>>> +
>>>>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
>>>>> +
>>>>> + switch (mipi_dsi->dsi_device->format) {
>>>>> + case MIPI_DSI_FMT_RGB888:
>>>>> + dpi_data_format = COLOR_24BIT;
>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
>>>>> + break;
>>>>> + case MIPI_DSI_FMT_RGB666:
>>>>> + dpi_data_format = COLOR_18BIT_CFG_2;
>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
>>>>> + break;
>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>>>> + case MIPI_DSI_FMT_RGB565:
>>>>> + /* invalid */
>>>>> + break;
>>>>> + };
>>>>> +
>>>>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
>>>>> + meson_venc_mipi_dsi_mode_set(priv, mode);
>>>>> +
>>>>> + meson_encl_load_gamma(priv);
>>>>> +
>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>> +
>>>>> + meson_dw_mipi_dsi_init(mipi_dsi);
>>>>> +
>>>>> + /* Configure Set color format for DPI register */
>>>>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
>>>>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
>>>>> + ~(0x7<<BIT_IN_COLOR_MODE) &
>>>>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
>>>>> +
>>>>> + writel_relaxed(reg |
>>>>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
>>>>> + (venc_data_width << BIT_IN_COLOR_MODE) |
>>>>> + 0 << BIT_COMP0_SEL |
>>>>> + 1 << BIT_COMP1_SEL |
>>>>> + 2 << BIT_COMP2_SEL |
>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>>>> +}
>>>>> +
>>>>> +static const struct drm_encoder_helper_funcs
>>>>> + meson_mipi_dsi_encoder_helper_funcs = {
>>>>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
>>>>> + .disable = meson_mipi_dsi_encoder_disable,
>>>>> + .enable = meson_mipi_dsi_encoder_enable,
>>>>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
>>>>> +};
>>>>> +
>>>>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
>>>>> + void *data)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>>>> + struct drm_device *drm = data;
>>>>> + struct meson_drm *priv = drm->dev_private;
>>>>> + struct drm_encoder *encoder;
>>>>> + int ret;
>>>>> +
>>>>> + /* Check before if we are supposed to have a sub-device... */
>>>>> + if (!mipi_dsi->dsi_device)
>>>>> + return -EPROBE_DEFER;
>>>>> +
>>>>> + encoder = &mipi_dsi->encoder;
>>>>> + mipi_dsi->priv = priv;
>>>>> +
>>>>> + /* Encoder */
>>>>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
>>>>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
>>>>> + if (ret) {
>>>>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
>>>>> +
>>>>> + encoder->possible_crtcs = BIT(0);
>>>>> +
>>>>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
>>>>> + if (ret) {
>>>>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + phy_init(mipi_dsi->phy);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
>>>>> + void *data)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>>>> +
>>>>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
>>>>> +
>>>>> + phy_exit(mipi_dsi->phy);
>>>>> +}
>>>>> +
>>>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
>>>>> + .bind = meson_dw_mipi_dsi_bind,
>>>>> + .unbind = meson_dw_mipi_dsi_unbind,
>>>>> +};
>>>>> +
>>>>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
>>>>> + struct mipi_dsi_device *device)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>> +
>>>>> + mipi_dsi->dsi_device = device;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
>>>>> + struct mipi_dsi_device *device)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>> +
>>>>> + if (device == mipi_dsi->dsi_device)
>>>>> + mipi_dsi->dsi_device = NULL;
>>>>> + else
>>>>> + return -EINVAL;
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
>>>>> + .attach = meson_dw_mipi_dsi_host_attach,
>>>>> + .detach = meson_dw_mipi_dsi_host_detach,
>>>>> +};
>>>>> +
>>>>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi;
>>>>> + struct reset_control *top_rst;
>>>>> + struct resource *res;
>>>>> + int ret;
>>>>> +
>>>>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
>>>>> + if (!mipi_dsi)
>>>>> + return -ENOMEM;
>>>>> +
>>>>> + mipi_dsi->dev = &pdev->dev;
>>>>> +
>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
>>>>> + if (IS_ERR(mipi_dsi->base))
>>>>> + return PTR_ERR(mipi_dsi->base);
>>>>> +
>>>>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
>>>>> + if (IS_ERR(mipi_dsi->phy)) {
>>>>> + ret = PTR_ERR(mipi_dsi->phy);
>>>>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
>>>>> + if (IS_ERR(mipi_dsi->px_clk)) {
>>>>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
>>>>> + return PTR_ERR(mipi_dsi->px_clk);
>>>>> + }
>>>>> +
>>>>> + /*
>>>>> + * We use a TOP reset signal because the APB reset signal
>>>>> + * is handled by the TOP control registers.
>>>>> + */
>>>>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
>>>>> + if (IS_ERR(top_rst)) {
>>>>> + ret = PTR_ERR(top_rst);
>>>>> +
>>>>> + if (ret != -EPROBE_DEFER)
>>>>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
>>>>> +
>>>>> + return ret;
>>>>> + }
>>>>> +
>>>>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
>>>>> + if (ret) {
>>>>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
>>>>> + goto err_clkdisable;
>>>>> + }
>>>>> +
>>>>> + reset_control_assert(top_rst);
>>>>> + usleep_range(10, 20);
>>>>> + reset_control_deassert(top_rst);
>>>>> +
>>>>> + /* MIPI DSI Controller */
>>>>> +
>>>>> + mipi_dsi->pdata.base = mipi_dsi->base;
>>>>> + mipi_dsi->pdata.max_data_lanes = 4;
>>>>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
>>>>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
>>>>> + mipi_dsi->pdata.priv_data = mipi_dsi;
>>>>> + platform_set_drvdata(pdev, mipi_dsi);
>>>>> +
>>>>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
>>>>> + if (IS_ERR(mipi_dsi->dmd)) {
>>>>> + ret = PTR_ERR(mipi_dsi->dmd);
>>>>> + if (ret != -EPROBE_DEFER)
>>>>> + dev_err(&pdev->dev,
>>>>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
>>>>> + goto err_clkdisable;
>>>>> + }
>>>>> +
>>>>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>>>> +
>>>>> +err_clkdisable:
>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>>>> +
>>>>> + return ret;
>>>>> +}
>>>>> +
>>>>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
>>>>> +{
>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
>>>>> +
>>>>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>>>> +
>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>>>> +
>>>>> + return 0;
>>>>> +}
>>>>> +
>>>>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
>>>>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
>>>>> + { }
>>>>> +};
>>>>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
>>>>> +
>>>>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
>>>>> + .probe = meson_dw_mipi_dsi_probe,
>>>>> + .remove = meson_dw_mipi_dsi_remove,
>>>>> + .driver = {
>>>>> + .name = DRIVER_NAME,
>>>>> + .of_match_table = meson_dw_mipi_dsi_of_table,
>>>>> + },
>>>>> +};
>>>>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
>>>>> +
>>>>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
>>>>> +MODULE_DESCRIPTION(DRIVER_DESC);
>>>>> +MODULE_LICENSE("GPL");
>>>>> --
>>>>> 2.22.0
>>>>>
>>>>
>>>> --
>>>> Daniel Vetter
>>>> Software Engineer, Intel Corporation
>>>> http://blog.ffwll.ch
>>>
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-08 8:06 ` Neil Armstrong
@ 2020-09-08 8:46 ` Daniel Vetter
2020-09-17 7:14 ` Neil Armstrong
0 siblings, 1 reply; 22+ messages in thread
From: Daniel Vetter @ 2020-09-08 8:46 UTC (permalink / raw)
To: Neil Armstrong; +Cc: dri-devel, linux-amlogic, linux-kernel
On Tue, Sep 08, 2020 at 10:06:03AM +0200, Neil Armstrong wrote:
> Hi,
>
> On 07/09/2020 20:03, Daniel Vetter wrote:
> > On Mon, Sep 07, 2020 at 11:03:29AM +0200, Neil Armstrong wrote:
> >> On 07/09/2020 10:44, Daniel Vetter wrote:
> >>> On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
> >>>> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
> >>>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> >>>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> >>>>> Amlogic SoCs.
> >>>>>
> >>>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> >>>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> >>>>> Analog PHY in the proper way.
> >>>>>
> >>>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> >>>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
> >>>>>
> >>>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> >>>>> DW-MIPI-DSI transceiver.
> >>>>>
> >>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >>>>
> >>>> More dw-hdmi drivers which aren't bridges but components, and the thing is
> >>>> still midlayer-y as heck :-/
> >>>
> >>> *dw-dsi, but really they both work the same way and should both be fixed
> >>> ...
> >>
> >> They are bridges but since they have platform-dependent code due to theirs's generic IP
> >> nature, they need to be intanciated by components to sync with the platform code.
> >
> > Yeah that's how it currently works, but there's not much reason why it
> > needs to work like that. That platform glue code can also be put behind
> > the drm_bridge abstraction, and we could use the normal dt based bridge
> > lookup like for everything else.
> >
> > Afaiui the only reason dw-* bridge drivers work like that is because for
> > historical reasons we only had component.c at first, and none of the more
> > fancy dynamic bridge lookup. So would be really good to switch this all
> > over to a proper&clean bridge abstraction, and not leak everything around.
>
> Does it mean we should avoit using components, right ?
Yup, at least when there's an established specific mechanism to handle
cross-driver interactions/EPROBE_DEFER.
So if you want a drm_panel or drm_bridge or a clock or i2c or anything
else standardized like that, no component.c please. That's just for the
driver-specific glue when you have entirely IP-specific way of building up
a driver from components, which will never be reused outside of that
overall driver.
Hence why dw-* using components is rather uncool.
> > I've typed up what I think should be the way forward a few times already,
> > but thus far not even the todo.rst entry materialized:
> >
> > https://lore.kernel.org/dri-devel/20200430135841.GE10381@phenom.ffwll.local/
> >
> > If everyone is always about "not in my patch series" it'll never happen.
>
> Today, the dw-mipi-dsi and dw-mipi-hdmi has mandatory callbacks to implement
> vendor specific features, like :
> - hdmi/dsi phy handling when mixed into the glue/custom/synopsys but with platform specific values
> - platform specific mode validation
> - hpd setup => could use laurent's work here with no_connector, but how do we handle rxsense ???
> - dsi timings/lane mbps ? these are platform phy specific
>
> For amlogic, I can split the "component" code handling venc/vclk into a primary bridge and add a
> secondary driver only handling the glue around dw-mipi-dsi/dw-mipi-hdmi, would that be a good start ?
I think what we should do here:
- type up todo.rst with the overall structure we want to aim for, i.e.
where is the code, who sets up what, how are the bridges bound into the
overall driver.
- demidlayer dw-* enough so that the callbacks are gone, and it becomes
more a toolbox/library for building a dw-* driver. Maybe we're there
already.
- All new drivers then need to use the toolbox and have everything behind
a drm_bridge driver in drm/bridge/, with just default binding exposed to
drivers, no EXPORT_SYMBOL at all. Also no exported symbols used, this
should all be directly linked into the dw-*.ko imo and treated as
internals.
- We might need to split the header files to make that clean enough.
- Once all existing dw-* users are converted, we ditch the EXPORT_SYMBOL
stuff completely (since I expect we'll just have one overall dw-dsi.ko
module with all bridge driver variants).
Cheers, Daniel
>
> Neil
>
> >
> > Cheers, Daniel
> >
> >
> >>
> >> Neil
> >>
> >>>
> >>>>
> >>>> Can we try to fix this? There's a ton of this going on, and the more we
> >>>> add the old fashioned way the harder this gets to fix up for real.
> >>>> -Daniel
> >>>>
> >>>>> ---
> >>>>> drivers/gpu/drm/meson/Kconfig | 7 +
> >>>>> drivers/gpu/drm/meson/Makefile | 1 +
> >>>>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> >>>>> 3 files changed, 570 insertions(+)
> >>>>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> >>>>> index 9f9281dd49f8..385f6f23839b 100644
> >>>>> --- a/drivers/gpu/drm/meson/Kconfig
> >>>>> +++ b/drivers/gpu/drm/meson/Kconfig
> >>>>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> >>>>> default y if DRM_MESON
> >>>>> select DRM_DW_HDMI
> >>>>> imply DRM_DW_HDMI_I2S_AUDIO
> >>>>> +
> >>>>> +config DRM_MESON_DW_MIPI_DSI
> >>>>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> >>>>> + depends on DRM_MESON
> >>>>> + default y if DRM_MESON
> >>>>> + select DRM_DW_MIPI_DSI
> >>>>> + select GENERIC_PHY_MIPI_DPHY
> >>>>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> >>>>> index 28a519cdf66b..2cc870e91182 100644
> >>>>> --- a/drivers/gpu/drm/meson/Makefile
> >>>>> +++ b/drivers/gpu/drm/meson/Makefile
> >>>>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
> >>>>>
> >>>>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
> >>>>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> >>>>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> >>>>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>> new file mode 100644
> >>>>> index 000000000000..bbe1294fce7c
> >>>>> --- /dev/null
> >>>>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>> @@ -0,0 +1,562 @@
> >>>>> +// SPDX-License-Identifier: GPL-2.0-or-later
> >>>>> +/*
> >>>>> + * Copyright (C) 2016 BayLibre, SAS
> >>>>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> >>>>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> >>>>> + */
> >>>>> +
> >>>>> +#include <linux/clk.h>
> >>>>> +#include <linux/component.h>
> >>>>> +#include <linux/kernel.h>
> >>>>> +#include <linux/module.h>
> >>>>> +#include <linux/of_device.h>
> >>>>> +#include <linux/of_graph.h>
> >>>>> +#include <linux/reset.h>
> >>>>> +#include <linux/phy/phy.h>
> >>>>> +
> >>>>> +#include <video/mipi_display.h>
> >>>>> +
> >>>>> +#include <drm/bridge/dw_mipi_dsi.h>
> >>>>> +#include <drm/drm_mipi_dsi.h>
> >>>>> +
> >>>>> +#include <drm/drm_atomic_helper.h>
> >>>>> +#include <drm/drm_device.h>
> >>>>> +#include <drm/drm_probe_helper.h>
> >>>>> +#include <drm/drm_print.h>
> >>>>> +
> >>>>> +#include "meson_drv.h"
> >>>>> +#include "meson_dw_mipi_dsi.h"
> >>>>> +#include "meson_registers.h"
> >>>>> +#include "meson_venc.h"
> >>>>> +
> >>>>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
> >>>>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> >>>>> +
> >>>>> +/* MIPI DSI/VENC Color Format Definitions */
> >>>>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
> >>>>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
> >>>>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
> >>>>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
> >>>>> +
> >>>>> +#define COLOR_16BIT_CFG_1 0x0
> >>>>> +#define COLOR_16BIT_CFG_2 0x1
> >>>>> +#define COLOR_16BIT_CFG_3 0x2
> >>>>> +#define COLOR_18BIT_CFG_1 0x3
> >>>>> +#define COLOR_18BIT_CFG_2 0x4
> >>>>> +#define COLOR_24BIT 0x5
> >>>>> +#define COLOR_20BIT_LOOSE 0x6
> >>>>> +#define COLOR_24_BIT_YCBCR 0x7
> >>>>> +#define COLOR_16BIT_YCBCR 0x8
> >>>>> +#define COLOR_30BIT 0x9
> >>>>> +#define COLOR_36BIT 0xa
> >>>>> +#define COLOR_12BIT 0xb
> >>>>> +#define COLOR_RGB_111 0xc
> >>>>> +#define COLOR_RGB_332 0xd
> >>>>> +#define COLOR_RGB_444 0xe
> >>>>> +
> >>>>> +/* MIPI DSI Relative REGISTERs Definitions */
> >>>>> +/* For MIPI_DSI_TOP_CNTL */
> >>>>> +#define BIT_DPI_COLOR_MODE 20
> >>>>> +#define BIT_IN_COLOR_MODE 16
> >>>>> +#define BIT_CHROMA_SUBSAMPLE 14
> >>>>> +#define BIT_COMP2_SEL 12
> >>>>> +#define BIT_COMP1_SEL 10
> >>>>> +#define BIT_COMP0_SEL 8
> >>>>> +#define BIT_DE_POL 6
> >>>>> +#define BIT_HSYNC_POL 5
> >>>>> +#define BIT_VSYNC_POL 4
> >>>>> +#define BIT_DPICOLORM 3
> >>>>> +#define BIT_DPISHUTDN 2
> >>>>> +#define BIT_EDPITE_INTR_PULSE 1
> >>>>> +#define BIT_ERR_INTR_PULSE 0
> >>>>> +
> >>>>> +/* HHI Registers */
> >>>>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> >>>>> +#define VCLK2_DIV_MASK 0xff
> >>>>> +#define VCLK2_DIV_EN BIT(16)
> >>>>> +#define VCLK2_DIV_RESET BIT(17)
> >>>>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
> >>>>> +#define CTS_ENCL_SEL_SHIFT 12
> >>>>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> >>>>> +#define VCLK2_EN BIT(19)
> >>>>> +#define VCLK2_SEL_MASK (0x7 << 16)
> >>>>> +#define VCLK2_SEL_SHIFT 16
> >>>>> +#define VCLK2_SOFT_RESET BIT(15)
> >>>>> +#define VCLK2_DIV1_EN BIT(0)
> >>>>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> >>>>> +#define CTS_ENCL_EN BIT(3)
> >>>>> +
> >>>>> +/**
> >>>>> + * DOC: MIPI DSI
> >>>>> + *
> >>>>> + */
> >>>>> +
> >>>>> +struct meson_dw_mipi_dsi {
> >>>>> + struct drm_encoder encoder;
> >>>>> + struct meson_drm *priv;
> >>>>> + struct device *dev;
> >>>>> + void __iomem *base;
> >>>>> + struct phy *phy;
> >>>>> + union phy_configure_opts phy_opts;
> >>>>> + struct dw_mipi_dsi *dmd;
> >>>>> + struct dw_mipi_dsi_plat_data pdata;
> >>>>> + struct mipi_dsi_device *dsi_device;
> >>>>> + unsigned long mode_flags;
> >>>>> + struct clk *px_clk;
> >>>>> +};
> >>>>> +#define encoder_to_meson_dw_mipi_dsi(x) \
> >>>>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
> >>>>> +
> >>>>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> >>>>> + struct drm_display_mode *mode)
> >>>>> +{
> >>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>> + unsigned int vclk2_div;
> >>>>> + unsigned int pll_rate;
> >>>>> + int ret;
> >>>>> +
> >>>>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> >>>>> + vclk2_div = pll_rate / (mode->clock * 1000);
> >>>>> +
> >>>>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> >>>>> + if (ret) {
> >>>>> + pr_err("Failed to set DSI PLL rate %lu\n",
> >>>>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> >>>>> +
> >>>>> + return;
> >>>>> + }
> >>>>> +
> >>>>> + /* Disable VCLK2 */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> >>>>> +
> >>>>> + /* Setup the VCLK2 divider value */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>> + VCLK2_DIV_MASK, (vclk2_div - 1));
> >>>>> +
> >>>>> + /* select gp0 for vclk2 */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> >>>>> +
> >>>>> + /* enable vclk2 gate */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> >>>>> +
> >>>>> + /* select vclk2_div1 for encl */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> >>>>> +
> >>>>> + /* release vclk2_div_reset and enable vclk2_div */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> >>>>> +
> >>>>> + /* enable vclk2_div1 gate */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> >>>>> +
> >>>>> + /* reset vclk2 */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> >>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>> + VCLK2_SOFT_RESET, 0);
> >>>>> +
> >>>>> + /* enable encl_clk */
> >>>>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> >>>>> + CTS_ENCL_EN, CTS_ENCL_EN);
> >>>>> +
> >>>>> + usleep_range(10000, 11000);
> >>>>> +}
> >>>>> +
> >>>>> +static int dw_mipi_dsi_phy_init(void *priv_data)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>> +
> >>>>> +
> >>>>> + phy_power_on(mipi_dsi->phy);
> >>>>> +
> >>>>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>> +
> >>>>> + phy_power_off(mipi_dsi->phy);
> >>>>> +}
> >>>>> +
> >>>>> +static int
> >>>>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> >>>>> + unsigned long mode_flags, u32 lanes, u32 format,
> >>>>> + unsigned int *lane_mbps)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>> +
> >>>>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static int
> >>>>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> >>>>> + struct dw_mipi_dsi_dphy_timing *timing)
> >>>>> +{
> >>>>> + /* TOFIX handle other cases */
> >>>>> +
> >>>>> + timing->clk_lp2hs = 37;
> >>>>> + timing->clk_hs2lp = 135;
> >>>>> + timing->data_lp2hs = 50;
> >>>>> + timing->data_hs2lp = 3;
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static int
> >>>>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> >>>>> +{
> >>>>> + *esc_clk_rate = 4; /* Mhz */
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> >>>>> + .init = dw_mipi_dsi_phy_init,
> >>>>> + .power_off = dw_mipi_dsi_phy_power_off,
> >>>>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> >>>>> + .get_timing = dw_mipi_dsi_phy_get_timing,
> >>>>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> >>>>> +};
> >>>>> +
> >>>>> +/* Encoder */
> >>>>> +
> >>>>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> >>>>> +{
> >>>>> + drm_encoder_cleanup(encoder);
> >>>>> +}
> >>>>> +
> >>>>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> >>>>> + .destroy = meson_mipi_dsi_encoder_destroy,
> >>>>> +};
> >>>>> +
> >>>>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> >>>>> + struct drm_crtc_state *crtc_state,
> >>>>> + struct drm_connector_state *conn_state)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>> +
> >>>>> + switch (mipi_dsi->dsi_device->format) {
> >>>>> + case MIPI_DSI_FMT_RGB888:
> >>>>> + break;
> >>>>> + case MIPI_DSI_FMT_RGB666:
> >>>>> + break;
> >>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>>>> + case MIPI_DSI_FMT_RGB565:
> >>>>> + default:
> >>>>> + DRM_DEV_ERROR(mipi_dsi->dev,
> >>>>> + "invalid pixel format %d\n",
> >>>>> + mipi_dsi->dsi_device->format);
> >>>>> + return -EINVAL;
> >>>>> + };
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>> +
> >>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>> +}
> >>>>> +
> >>>>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>> +
> >>>>> + writel_bits_relaxed(BIT(3), BIT(3),
> >>>>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> >>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> >>>>> +}
> >>>>> +
> >>>>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> >>>>> +{
> >>>>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> >>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>>>> +
> >>>>> + writel_bits_relaxed(0xf, 0xf,
> >>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>>>> + writel_bits_relaxed(0xf, 0,
> >>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>>>> +
> >>>>> + writel_bits_relaxed(0x3, 0x3,
> >>>>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> >>>>> +
> >>>>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> >>>>> +}
> >>>>> +
> >>>>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> >>>>> + struct drm_display_mode *mode,
> >>>>> + struct drm_display_mode *adjusted_mode)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>> + unsigned int dpi_data_format, venc_data_width;
> >>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>> + int bpp;
> >>>>> + u32 reg;
> >>>>> +
> >>>>> + mipi_dsi->mode_flags = mode->flags;
> >>>>> +
> >>>>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> >>>>> +
> >>>>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> >>>>> + bpp, mipi_dsi->dsi_device->lanes,
> >>>>> + &mipi_dsi->phy_opts.mipi_dphy);
> >>>>> +
> >>>>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> >>>>> +
> >>>>> + switch (mipi_dsi->dsi_device->format) {
> >>>>> + case MIPI_DSI_FMT_RGB888:
> >>>>> + dpi_data_format = COLOR_24BIT;
> >>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> >>>>> + break;
> >>>>> + case MIPI_DSI_FMT_RGB666:
> >>>>> + dpi_data_format = COLOR_18BIT_CFG_2;
> >>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> >>>>> + break;
> >>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>>>> + case MIPI_DSI_FMT_RGB565:
> >>>>> + /* invalid */
> >>>>> + break;
> >>>>> + };
> >>>>> +
> >>>>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> >>>>> + meson_venc_mipi_dsi_mode_set(priv, mode);
> >>>>> +
> >>>>> + meson_encl_load_gamma(priv);
> >>>>> +
> >>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>> +
> >>>>> + meson_dw_mipi_dsi_init(mipi_dsi);
> >>>>> +
> >>>>> + /* Configure Set color format for DPI register */
> >>>>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> >>>>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
> >>>>> + ~(0x7<<BIT_IN_COLOR_MODE) &
> >>>>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> >>>>> +
> >>>>> + writel_relaxed(reg |
> >>>>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> >>>>> + (venc_data_width << BIT_IN_COLOR_MODE) |
> >>>>> + 0 << BIT_COMP0_SEL |
> >>>>> + 1 << BIT_COMP1_SEL |
> >>>>> + 2 << BIT_COMP2_SEL |
> >>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> >>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> >>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>>>> +}
> >>>>> +
> >>>>> +static const struct drm_encoder_helper_funcs
> >>>>> + meson_mipi_dsi_encoder_helper_funcs = {
> >>>>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> >>>>> + .disable = meson_mipi_dsi_encoder_disable,
> >>>>> + .enable = meson_mipi_dsi_encoder_enable,
> >>>>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
> >>>>> +};
> >>>>> +
> >>>>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> >>>>> + void *data)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>>>> + struct drm_device *drm = data;
> >>>>> + struct meson_drm *priv = drm->dev_private;
> >>>>> + struct drm_encoder *encoder;
> >>>>> + int ret;
> >>>>> +
> >>>>> + /* Check before if we are supposed to have a sub-device... */
> >>>>> + if (!mipi_dsi->dsi_device)
> >>>>> + return -EPROBE_DEFER;
> >>>>> +
> >>>>> + encoder = &mipi_dsi->encoder;
> >>>>> + mipi_dsi->priv = priv;
> >>>>> +
> >>>>> + /* Encoder */
> >>>>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> >>>>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> >>>>> + if (ret) {
> >>>>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
> >>>>> + return ret;
> >>>>> + }
> >>>>> +
> >>>>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> >>>>> +
> >>>>> + encoder->possible_crtcs = BIT(0);
> >>>>> +
> >>>>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> >>>>> + if (ret) {
> >>>>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> +
> >>>>> + phy_init(mipi_dsi->phy);
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> >>>>> + void *data)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>>>> +
> >>>>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
> >>>>> +
> >>>>> + phy_exit(mipi_dsi->phy);
> >>>>> +}
> >>>>> +
> >>>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> >>>>> + .bind = meson_dw_mipi_dsi_bind,
> >>>>> + .unbind = meson_dw_mipi_dsi_unbind,
> >>>>> +};
> >>>>> +
> >>>>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
> >>>>> + struct mipi_dsi_device *device)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>> +
> >>>>> + mipi_dsi->dsi_device = device;
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
> >>>>> + struct mipi_dsi_device *device)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>> +
> >>>>> + if (device == mipi_dsi->dsi_device)
> >>>>> + mipi_dsi->dsi_device = NULL;
> >>>>> + else
> >>>>> + return -EINVAL;
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
> >>>>> + .attach = meson_dw_mipi_dsi_host_attach,
> >>>>> + .detach = meson_dw_mipi_dsi_host_detach,
> >>>>> +};
> >>>>> +
> >>>>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi;
> >>>>> + struct reset_control *top_rst;
> >>>>> + struct resource *res;
> >>>>> + int ret;
> >>>>> +
> >>>>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
> >>>>> + if (!mipi_dsi)
> >>>>> + return -ENOMEM;
> >>>>> +
> >>>>> + mipi_dsi->dev = &pdev->dev;
> >>>>> +
> >>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>>>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
> >>>>> + if (IS_ERR(mipi_dsi->base))
> >>>>> + return PTR_ERR(mipi_dsi->base);
> >>>>> +
> >>>>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
> >>>>> + if (IS_ERR(mipi_dsi->phy)) {
> >>>>> + ret = PTR_ERR(mipi_dsi->phy);
> >>>>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
> >>>>> + return ret;
> >>>>> + }
> >>>>> +
> >>>>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
> >>>>> + if (IS_ERR(mipi_dsi->px_clk)) {
> >>>>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
> >>>>> + return PTR_ERR(mipi_dsi->px_clk);
> >>>>> + }
> >>>>> +
> >>>>> + /*
> >>>>> + * We use a TOP reset signal because the APB reset signal
> >>>>> + * is handled by the TOP control registers.
> >>>>> + */
> >>>>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
> >>>>> + if (IS_ERR(top_rst)) {
> >>>>> + ret = PTR_ERR(top_rst);
> >>>>> +
> >>>>> + if (ret != -EPROBE_DEFER)
> >>>>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
> >>>>> +
> >>>>> + return ret;
> >>>>> + }
> >>>>> +
> >>>>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
> >>>>> + if (ret) {
> >>>>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
> >>>>> + goto err_clkdisable;
> >>>>> + }
> >>>>> +
> >>>>> + reset_control_assert(top_rst);
> >>>>> + usleep_range(10, 20);
> >>>>> + reset_control_deassert(top_rst);
> >>>>> +
> >>>>> + /* MIPI DSI Controller */
> >>>>> +
> >>>>> + mipi_dsi->pdata.base = mipi_dsi->base;
> >>>>> + mipi_dsi->pdata.max_data_lanes = 4;
> >>>>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
> >>>>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
> >>>>> + mipi_dsi->pdata.priv_data = mipi_dsi;
> >>>>> + platform_set_drvdata(pdev, mipi_dsi);
> >>>>> +
> >>>>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
> >>>>> + if (IS_ERR(mipi_dsi->dmd)) {
> >>>>> + ret = PTR_ERR(mipi_dsi->dmd);
> >>>>> + if (ret != -EPROBE_DEFER)
> >>>>> + dev_err(&pdev->dev,
> >>>>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
> >>>>> + goto err_clkdisable;
> >>>>> + }
> >>>>> +
> >>>>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>>>> +
> >>>>> +err_clkdisable:
> >>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>>>> +
> >>>>> + return ret;
> >>>>> +}
> >>>>> +
> >>>>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
> >>>>> +{
> >>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
> >>>>> +
> >>>>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>>>> +
> >>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>>>> +
> >>>>> + return 0;
> >>>>> +}
> >>>>> +
> >>>>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
> >>>>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
> >>>>> + { }
> >>>>> +};
> >>>>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
> >>>>> +
> >>>>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
> >>>>> + .probe = meson_dw_mipi_dsi_probe,
> >>>>> + .remove = meson_dw_mipi_dsi_remove,
> >>>>> + .driver = {
> >>>>> + .name = DRIVER_NAME,
> >>>>> + .of_match_table = meson_dw_mipi_dsi_of_table,
> >>>>> + },
> >>>>> +};
> >>>>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
> >>>>> +
> >>>>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> >>>>> +MODULE_DESCRIPTION(DRIVER_DESC);
> >>>>> +MODULE_LICENSE("GPL");
> >>>>> --
> >>>>> 2.22.0
> >>>>>
> >>>>
> >>>> --
> >>>> Daniel Vetter
> >>>> Software Engineer, Intel Corporation
> >>>> http://blog.ffwll.ch
> >>>
> >>
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-08 8:46 ` Daniel Vetter
@ 2020-09-17 7:14 ` Neil Armstrong
2020-09-17 11:32 ` Daniel Vetter
0 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2020-09-17 7:14 UTC (permalink / raw)
To: dri-devel, linux-amlogic, linux-kernel
On 08/09/2020 10:46, Daniel Vetter wrote:
> On Tue, Sep 08, 2020 at 10:06:03AM +0200, Neil Armstrong wrote:
>> Hi,
>>
>> On 07/09/2020 20:03, Daniel Vetter wrote:
>>> On Mon, Sep 07, 2020 at 11:03:29AM +0200, Neil Armstrong wrote:
>>>> On 07/09/2020 10:44, Daniel Vetter wrote:
>>>>> On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
>>>>>> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
>>>>>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>>>>>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>>>>>>> Amlogic SoCs.
>>>>>>>
>>>>>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
>>>>>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
>>>>>>> Analog PHY in the proper way.
>>>>>>>
>>>>>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
>>>>>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
>>>>>>>
>>>>>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
>>>>>>> DW-MIPI-DSI transceiver.
>>>>>>>
>>>>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>>>>>
>>>>>> More dw-hdmi drivers which aren't bridges but components, and the thing is
>>>>>> still midlayer-y as heck :-/
>>>>>
>>>>> *dw-dsi, but really they both work the same way and should both be fixed
>>>>> ...
>>>>
>>>> They are bridges but since they have platform-dependent code due to theirs's generic IP
>>>> nature, they need to be intanciated by components to sync with the platform code.
>>>
>>> Yeah that's how it currently works, but there's not much reason why it
>>> needs to work like that. That platform glue code can also be put behind
>>> the drm_bridge abstraction, and we could use the normal dt based bridge
>>> lookup like for everything else.
>>>
>>> Afaiui the only reason dw-* bridge drivers work like that is because for
>>> historical reasons we only had component.c at first, and none of the more
>>> fancy dynamic bridge lookup. So would be really good to switch this all
>>> over to a proper&clean bridge abstraction, and not leak everything around.
>>
>> Does it mean we should avoit using components, right ?
>
> Yup, at least when there's an established specific mechanism to handle
> cross-driver interactions/EPROBE_DEFER.
>
> So if you want a drm_panel or drm_bridge or a clock or i2c or anything
> else standardized like that, no component.c please. That's just for the
> driver-specific glue when you have entirely IP-specific way of building up
> a driver from components, which will never be reused outside of that
> overall driver.
>
> Hence why dw-* using components is rather uncool.
>
>>> I've typed up what I think should be the way forward a few times already,
>>> but thus far not even the todo.rst entry materialized:
>>>
>>> https://lore.kernel.org/dri-devel/20200430135841.GE10381@phenom.ffwll.local/
>>>
>>> If everyone is always about "not in my patch series" it'll never happen.
>>
>> Today, the dw-mipi-dsi and dw-mipi-hdmi has mandatory callbacks to implement
>> vendor specific features, like :
>> - hdmi/dsi phy handling when mixed into the glue/custom/synopsys but with platform specific values
>> - platform specific mode validation
>> - hpd setup => could use laurent's work here with no_connector, but how do we handle rxsense ???
>> - dsi timings/lane mbps ? these are platform phy specific
>>
>> For amlogic, I can split the "component" code handling venc/vclk into a primary bridge and add a
>> secondary driver only handling the glue around dw-mipi-dsi/dw-mipi-hdmi, would that be a good start ?
>
> I think what we should do here:
>
> - type up todo.rst with the overall structure we want to aim for, i.e.
> where is the code, who sets up what, how are the bridges bound into the
> overall driver.
OK, sure, this can be a good start, but first I would like all the other bridge
maintainers & reviewers to agree on the the wanted structure.
>
> - demidlayer dw-* enough so that the callbacks are gone, and it becomes
> more a toolbox/library for building a dw-* driver. Maybe we're there
> already.
This is not really wanted, otherwise we would duplicate a large amount of code
over all the platform glues, is this really wanted ?
Today, they already are a toolbox, with different levels of callback neded
depending on how deep the integration is.
>
> - All new drivers then need to use the toolbox and have everything behind
> a drm_bridge driver in drm/bridge/, with just default binding exposed to
> drivers, no EXPORT_SYMBOL at all. Also no exported symbols used, this
> should all be directly linked into the dw-*.ko imo and treated as
> internals.
In theory this is cool, in practice, this is impossible for meson_dw_hdmi,
the first reason is how the registers are accessed for GX family, we need to
define custom regmap read/write functions.
For dw-mipi-dsi, it may be feasible, but again I don't see why vendor glue code
should live in drm/bridge/ ?
The last point, this will impact multiple platforms support in a single patchset,
I do not have enough time available to make such changes and check for non-regression.
>
> - We might need to split the header files to make that clean enough.
>
> - Once all existing dw-* users are converted, we ditch the EXPORT_SYMBOL
> stuff completely (since I expect we'll just have one overall dw-dsi.ko
> module with all bridge driver variants).
?
why ? why load & add multiple vendor adaptation in a single module ?
this sounds like a bad idea, sorry.
In the meantime, I'd really like to have this upstream, should this really wait for
multiple months for tractations and rework ?
I can rework a little to only have the dw-mipi-dsi glue and the encoder stuff in an
another file, is this fine for a first step ?
Neil
>
> Cheers, Daniel
>
>
>
>>
>> Neil
>>
>>>
>>> Cheers, Daniel
>>>
>>>
>>>>
>>>> Neil
>>>>
>>>>>
>>>>>>
>>>>>> Can we try to fix this? There's a ton of this going on, and the more we
>>>>>> add the old fashioned way the harder this gets to fix up for real.
>>>>>> -Daniel
>>>>>>
>>>>>>> ---
>>>>>>> drivers/gpu/drm/meson/Kconfig | 7 +
>>>>>>> drivers/gpu/drm/meson/Makefile | 1 +
>>>>>>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
>>>>>>> 3 files changed, 570 insertions(+)
>>>>>>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
>>>>>>> index 9f9281dd49f8..385f6f23839b 100644
>>>>>>> --- a/drivers/gpu/drm/meson/Kconfig
>>>>>>> +++ b/drivers/gpu/drm/meson/Kconfig
>>>>>>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
>>>>>>> default y if DRM_MESON
>>>>>>> select DRM_DW_HDMI
>>>>>>> imply DRM_DW_HDMI_I2S_AUDIO
>>>>>>> +
>>>>>>> +config DRM_MESON_DW_MIPI_DSI
>>>>>>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
>>>>>>> + depends on DRM_MESON
>>>>>>> + default y if DRM_MESON
>>>>>>> + select DRM_DW_MIPI_DSI
>>>>>>> + select GENERIC_PHY_MIPI_DPHY
>>>>>>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
>>>>>>> index 28a519cdf66b..2cc870e91182 100644
>>>>>>> --- a/drivers/gpu/drm/meson/Makefile
>>>>>>> +++ b/drivers/gpu/drm/meson/Makefile
>>>>>>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
>>>>>>>
>>>>>>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
>>>>>>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
>>>>>>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
>>>>>>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>>>> new file mode 100644
>>>>>>> index 000000000000..bbe1294fce7c
>>>>>>> --- /dev/null
>>>>>>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>>>>>>> @@ -0,0 +1,562 @@
>>>>>>> +// SPDX-License-Identifier: GPL-2.0-or-later
>>>>>>> +/*
>>>>>>> + * Copyright (C) 2016 BayLibre, SAS
>>>>>>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
>>>>>>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
>>>>>>> + */
>>>>>>> +
>>>>>>> +#include <linux/clk.h>
>>>>>>> +#include <linux/component.h>
>>>>>>> +#include <linux/kernel.h>
>>>>>>> +#include <linux/module.h>
>>>>>>> +#include <linux/of_device.h>
>>>>>>> +#include <linux/of_graph.h>
>>>>>>> +#include <linux/reset.h>
>>>>>>> +#include <linux/phy/phy.h>
>>>>>>> +
>>>>>>> +#include <video/mipi_display.h>
>>>>>>> +
>>>>>>> +#include <drm/bridge/dw_mipi_dsi.h>
>>>>>>> +#include <drm/drm_mipi_dsi.h>
>>>>>>> +
>>>>>>> +#include <drm/drm_atomic_helper.h>
>>>>>>> +#include <drm/drm_device.h>
>>>>>>> +#include <drm/drm_probe_helper.h>
>>>>>>> +#include <drm/drm_print.h>
>>>>>>> +
>>>>>>> +#include "meson_drv.h"
>>>>>>> +#include "meson_dw_mipi_dsi.h"
>>>>>>> +#include "meson_registers.h"
>>>>>>> +#include "meson_venc.h"
>>>>>>> +
>>>>>>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
>>>>>>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
>>>>>>> +
>>>>>>> +/* MIPI DSI/VENC Color Format Definitions */
>>>>>>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
>>>>>>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
>>>>>>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
>>>>>>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
>>>>>>> +
>>>>>>> +#define COLOR_16BIT_CFG_1 0x0
>>>>>>> +#define COLOR_16BIT_CFG_2 0x1
>>>>>>> +#define COLOR_16BIT_CFG_3 0x2
>>>>>>> +#define COLOR_18BIT_CFG_1 0x3
>>>>>>> +#define COLOR_18BIT_CFG_2 0x4
>>>>>>> +#define COLOR_24BIT 0x5
>>>>>>> +#define COLOR_20BIT_LOOSE 0x6
>>>>>>> +#define COLOR_24_BIT_YCBCR 0x7
>>>>>>> +#define COLOR_16BIT_YCBCR 0x8
>>>>>>> +#define COLOR_30BIT 0x9
>>>>>>> +#define COLOR_36BIT 0xa
>>>>>>> +#define COLOR_12BIT 0xb
>>>>>>> +#define COLOR_RGB_111 0xc
>>>>>>> +#define COLOR_RGB_332 0xd
>>>>>>> +#define COLOR_RGB_444 0xe
>>>>>>> +
>>>>>>> +/* MIPI DSI Relative REGISTERs Definitions */
>>>>>>> +/* For MIPI_DSI_TOP_CNTL */
>>>>>>> +#define BIT_DPI_COLOR_MODE 20
>>>>>>> +#define BIT_IN_COLOR_MODE 16
>>>>>>> +#define BIT_CHROMA_SUBSAMPLE 14
>>>>>>> +#define BIT_COMP2_SEL 12
>>>>>>> +#define BIT_COMP1_SEL 10
>>>>>>> +#define BIT_COMP0_SEL 8
>>>>>>> +#define BIT_DE_POL 6
>>>>>>> +#define BIT_HSYNC_POL 5
>>>>>>> +#define BIT_VSYNC_POL 4
>>>>>>> +#define BIT_DPICOLORM 3
>>>>>>> +#define BIT_DPISHUTDN 2
>>>>>>> +#define BIT_EDPITE_INTR_PULSE 1
>>>>>>> +#define BIT_ERR_INTR_PULSE 0
>>>>>>> +
>>>>>>> +/* HHI Registers */
>>>>>>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
>>>>>>> +#define VCLK2_DIV_MASK 0xff
>>>>>>> +#define VCLK2_DIV_EN BIT(16)
>>>>>>> +#define VCLK2_DIV_RESET BIT(17)
>>>>>>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
>>>>>>> +#define CTS_ENCL_SEL_SHIFT 12
>>>>>>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
>>>>>>> +#define VCLK2_EN BIT(19)
>>>>>>> +#define VCLK2_SEL_MASK (0x7 << 16)
>>>>>>> +#define VCLK2_SEL_SHIFT 16
>>>>>>> +#define VCLK2_SOFT_RESET BIT(15)
>>>>>>> +#define VCLK2_DIV1_EN BIT(0)
>>>>>>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
>>>>>>> +#define CTS_ENCL_EN BIT(3)
>>>>>>> +
>>>>>>> +/**
>>>>>>> + * DOC: MIPI DSI
>>>>>>> + *
>>>>>>> + */
>>>>>>> +
>>>>>>> +struct meson_dw_mipi_dsi {
>>>>>>> + struct drm_encoder encoder;
>>>>>>> + struct meson_drm *priv;
>>>>>>> + struct device *dev;
>>>>>>> + void __iomem *base;
>>>>>>> + struct phy *phy;
>>>>>>> + union phy_configure_opts phy_opts;
>>>>>>> + struct dw_mipi_dsi *dmd;
>>>>>>> + struct dw_mipi_dsi_plat_data pdata;
>>>>>>> + struct mipi_dsi_device *dsi_device;
>>>>>>> + unsigned long mode_flags;
>>>>>>> + struct clk *px_clk;
>>>>>>> +};
>>>>>>> +#define encoder_to_meson_dw_mipi_dsi(x) \
>>>>>>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
>>>>>>> +
>>>>>>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
>>>>>>> + struct drm_display_mode *mode)
>>>>>>> +{
>>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>>>> + unsigned int vclk2_div;
>>>>>>> + unsigned int pll_rate;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
>>>>>>> + vclk2_div = pll_rate / (mode->clock * 1000);
>>>>>>> +
>>>>>>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
>>>>>>> + if (ret) {
>>>>>>> + pr_err("Failed to set DSI PLL rate %lu\n",
>>>>>>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
>>>>>>> +
>>>>>>> + return;
>>>>>>> + }
>>>>>>> +
>>>>>>> + /* Disable VCLK2 */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
>>>>>>> +
>>>>>>> + /* Setup the VCLK2 divider value */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>>>> + VCLK2_DIV_MASK, (vclk2_div - 1));
>>>>>>> +
>>>>>>> + /* select gp0 for vclk2 */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>>>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
>>>>>>> +
>>>>>>> + /* enable vclk2 gate */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
>>>>>>> +
>>>>>>> + /* select vclk2_div1 for encl */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>>>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
>>>>>>> +
>>>>>>> + /* release vclk2_div_reset and enable vclk2_div */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
>>>>>>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
>>>>>>> +
>>>>>>> + /* enable vclk2_div1 gate */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>>>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
>>>>>>> +
>>>>>>> + /* reset vclk2 */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>>>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
>>>>>>> + VCLK2_SOFT_RESET, 0);
>>>>>>> +
>>>>>>> + /* enable encl_clk */
>>>>>>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
>>>>>>> + CTS_ENCL_EN, CTS_ENCL_EN);
>>>>>>> +
>>>>>>> + usleep_range(10000, 11000);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int dw_mipi_dsi_phy_init(void *priv_data)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>>>> +
>>>>>>> +
>>>>>>> + phy_power_on(mipi_dsi->phy);
>>>>>>> +
>>>>>>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>>>> +
>>>>>>> + phy_power_off(mipi_dsi->phy);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int
>>>>>>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
>>>>>>> + unsigned long mode_flags, u32 lanes, u32 format,
>>>>>>> + unsigned int *lane_mbps)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>>>> +
>>>>>>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int
>>>>>>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
>>>>>>> + struct dw_mipi_dsi_dphy_timing *timing)
>>>>>>> +{
>>>>>>> + /* TOFIX handle other cases */
>>>>>>> +
>>>>>>> + timing->clk_lp2hs = 37;
>>>>>>> + timing->clk_hs2lp = 135;
>>>>>>> + timing->data_lp2hs = 50;
>>>>>>> + timing->data_hs2lp = 3;
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int
>>>>>>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
>>>>>>> +{
>>>>>>> + *esc_clk_rate = 4; /* Mhz */
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
>>>>>>> + .init = dw_mipi_dsi_phy_init,
>>>>>>> + .power_off = dw_mipi_dsi_phy_power_off,
>>>>>>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
>>>>>>> + .get_timing = dw_mipi_dsi_phy_get_timing,
>>>>>>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
>>>>>>> +};
>>>>>>> +
>>>>>>> +/* Encoder */
>>>>>>> +
>>>>>>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
>>>>>>> +{
>>>>>>> + drm_encoder_cleanup(encoder);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
>>>>>>> + .destroy = meson_mipi_dsi_encoder_destroy,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
>>>>>>> + struct drm_crtc_state *crtc_state,
>>>>>>> + struct drm_connector_state *conn_state)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>>>> +
>>>>>>> + switch (mipi_dsi->dsi_device->format) {
>>>>>>> + case MIPI_DSI_FMT_RGB888:
>>>>>>> + break;
>>>>>>> + case MIPI_DSI_FMT_RGB666:
>>>>>>> + break;
>>>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>>>>>> + case MIPI_DSI_FMT_RGB565:
>>>>>>> + default:
>>>>>>> + DRM_DEV_ERROR(mipi_dsi->dev,
>>>>>>> + "invalid pixel format %d\n",
>>>>>>> + mipi_dsi->dsi_device->format);
>>>>>>> + return -EINVAL;
>>>>>>> + };
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>>>> +
>>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
>>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
>>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>>>> +
>>>>>>> + writel_bits_relaxed(BIT(3), BIT(3),
>>>>>>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
>>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
>>>>>>> +{
>>>>>>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
>>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>>>>>> +
>>>>>>> + writel_bits_relaxed(0xf, 0xf,
>>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>>>>>> + writel_bits_relaxed(0xf, 0,
>>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
>>>>>>> +
>>>>>>> + writel_bits_relaxed(0x3, 0x3,
>>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
>>>>>>> +
>>>>>>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
>>>>>>> + struct drm_display_mode *mode,
>>>>>>> + struct drm_display_mode *adjusted_mode)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
>>>>>>> + unsigned int dpi_data_format, venc_data_width;
>>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
>>>>>>> + int bpp;
>>>>>>> + u32 reg;
>>>>>>> +
>>>>>>> + mipi_dsi->mode_flags = mode->flags;
>>>>>>> +
>>>>>>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
>>>>>>> +
>>>>>>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
>>>>>>> + bpp, mipi_dsi->dsi_device->lanes,
>>>>>>> + &mipi_dsi->phy_opts.mipi_dphy);
>>>>>>> +
>>>>>>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
>>>>>>> +
>>>>>>> + switch (mipi_dsi->dsi_device->format) {
>>>>>>> + case MIPI_DSI_FMT_RGB888:
>>>>>>> + dpi_data_format = COLOR_24BIT;
>>>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
>>>>>>> + break;
>>>>>>> + case MIPI_DSI_FMT_RGB666:
>>>>>>> + dpi_data_format = COLOR_18BIT_CFG_2;
>>>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
>>>>>>> + break;
>>>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
>>>>>>> + case MIPI_DSI_FMT_RGB565:
>>>>>>> + /* invalid */
>>>>>>> + break;
>>>>>>> + };
>>>>>>> +
>>>>>>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
>>>>>>> + meson_venc_mipi_dsi_mode_set(priv, mode);
>>>>>>> +
>>>>>>> + meson_encl_load_gamma(priv);
>>>>>>> +
>>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
>>>>>>> +
>>>>>>> + meson_dw_mipi_dsi_init(mipi_dsi);
>>>>>>> +
>>>>>>> + /* Configure Set color format for DPI register */
>>>>>>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
>>>>>>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
>>>>>>> + ~(0x7<<BIT_IN_COLOR_MODE) &
>>>>>>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
>>>>>>> +
>>>>>>> + writel_relaxed(reg |
>>>>>>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
>>>>>>> + (venc_data_width << BIT_IN_COLOR_MODE) |
>>>>>>> + 0 << BIT_COMP0_SEL |
>>>>>>> + 1 << BIT_COMP1_SEL |
>>>>>>> + 2 << BIT_COMP2_SEL |
>>>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
>>>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
>>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct drm_encoder_helper_funcs
>>>>>>> + meson_mipi_dsi_encoder_helper_funcs = {
>>>>>>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
>>>>>>> + .disable = meson_mipi_dsi_encoder_disable,
>>>>>>> + .enable = meson_mipi_dsi_encoder_enable,
>>>>>>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
>>>>>>> + void *data)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>>>>>> + struct drm_device *drm = data;
>>>>>>> + struct meson_drm *priv = drm->dev_private;
>>>>>>> + struct drm_encoder *encoder;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + /* Check before if we are supposed to have a sub-device... */
>>>>>>> + if (!mipi_dsi->dsi_device)
>>>>>>> + return -EPROBE_DEFER;
>>>>>>> +
>>>>>>> + encoder = &mipi_dsi->encoder;
>>>>>>> + mipi_dsi->priv = priv;
>>>>>>> +
>>>>>>> + /* Encoder */
>>>>>>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
>>>>>>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
>>>>>>> + if (ret) {
>>>>>>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> +
>>>>>>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
>>>>>>> +
>>>>>>> + encoder->possible_crtcs = BIT(0);
>>>>>>> +
>>>>>>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
>>>>>>> + if (ret) {
>>>>>>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> +
>>>>>>> + phy_init(mipi_dsi->phy);
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
>>>>>>> + void *data)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
>>>>>>> +
>>>>>>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
>>>>>>> +
>>>>>>> + phy_exit(mipi_dsi->phy);
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
>>>>>>> + .bind = meson_dw_mipi_dsi_bind,
>>>>>>> + .unbind = meson_dw_mipi_dsi_unbind,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
>>>>>>> + struct mipi_dsi_device *device)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>>>> +
>>>>>>> + mipi_dsi->dsi_device = device;
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
>>>>>>> + struct mipi_dsi_device *device)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
>>>>>>> +
>>>>>>> + if (device == mipi_dsi->dsi_device)
>>>>>>> + mipi_dsi->dsi_device = NULL;
>>>>>>> + else
>>>>>>> + return -EINVAL;
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
>>>>>>> + .attach = meson_dw_mipi_dsi_host_attach,
>>>>>>> + .detach = meson_dw_mipi_dsi_host_detach,
>>>>>>> +};
>>>>>>> +
>>>>>>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi;
>>>>>>> + struct reset_control *top_rst;
>>>>>>> + struct resource *res;
>>>>>>> + int ret;
>>>>>>> +
>>>>>>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
>>>>>>> + if (!mipi_dsi)
>>>>>>> + return -ENOMEM;
>>>>>>> +
>>>>>>> + mipi_dsi->dev = &pdev->dev;
>>>>>>> +
>>>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>>>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
>>>>>>> + if (IS_ERR(mipi_dsi->base))
>>>>>>> + return PTR_ERR(mipi_dsi->base);
>>>>>>> +
>>>>>>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
>>>>>>> + if (IS_ERR(mipi_dsi->phy)) {
>>>>>>> + ret = PTR_ERR(mipi_dsi->phy);
>>>>>>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> +
>>>>>>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
>>>>>>> + if (IS_ERR(mipi_dsi->px_clk)) {
>>>>>>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
>>>>>>> + return PTR_ERR(mipi_dsi->px_clk);
>>>>>>> + }
>>>>>>> +
>>>>>>> + /*
>>>>>>> + * We use a TOP reset signal because the APB reset signal
>>>>>>> + * is handled by the TOP control registers.
>>>>>>> + */
>>>>>>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
>>>>>>> + if (IS_ERR(top_rst)) {
>>>>>>> + ret = PTR_ERR(top_rst);
>>>>>>> +
>>>>>>> + if (ret != -EPROBE_DEFER)
>>>>>>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
>>>>>>> +
>>>>>>> + return ret;
>>>>>>> + }
>>>>>>> +
>>>>>>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
>>>>>>> + if (ret) {
>>>>>>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
>>>>>>> + goto err_clkdisable;
>>>>>>> + }
>>>>>>> +
>>>>>>> + reset_control_assert(top_rst);
>>>>>>> + usleep_range(10, 20);
>>>>>>> + reset_control_deassert(top_rst);
>>>>>>> +
>>>>>>> + /* MIPI DSI Controller */
>>>>>>> +
>>>>>>> + mipi_dsi->pdata.base = mipi_dsi->base;
>>>>>>> + mipi_dsi->pdata.max_data_lanes = 4;
>>>>>>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
>>>>>>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
>>>>>>> + mipi_dsi->pdata.priv_data = mipi_dsi;
>>>>>>> + platform_set_drvdata(pdev, mipi_dsi);
>>>>>>> +
>>>>>>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
>>>>>>> + if (IS_ERR(mipi_dsi->dmd)) {
>>>>>>> + ret = PTR_ERR(mipi_dsi->dmd);
>>>>>>> + if (ret != -EPROBE_DEFER)
>>>>>>> + dev_err(&pdev->dev,
>>>>>>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
>>>>>>> + goto err_clkdisable;
>>>>>>> + }
>>>>>>> +
>>>>>>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>>>>>> +
>>>>>>> +err_clkdisable:
>>>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>>>>>> +
>>>>>>> + return ret;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
>>>>>>> +{
>>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
>>>>>>> +
>>>>>>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
>>>>>>> +
>>>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
>>>>>>> +
>>>>>>> + return 0;
>>>>>>> +}
>>>>>>> +
>>>>>>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
>>>>>>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
>>>>>>> + { }
>>>>>>> +};
>>>>>>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
>>>>>>> +
>>>>>>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
>>>>>>> + .probe = meson_dw_mipi_dsi_probe,
>>>>>>> + .remove = meson_dw_mipi_dsi_remove,
>>>>>>> + .driver = {
>>>>>>> + .name = DRIVER_NAME,
>>>>>>> + .of_match_table = meson_dw_mipi_dsi_of_table,
>>>>>>> + },
>>>>>>> +};
>>>>>>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
>>>>>>> +
>>>>>>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
>>>>>>> +MODULE_DESCRIPTION(DRIVER_DESC);
>>>>>>> +MODULE_LICENSE("GPL");
>>>>>>> --
>>>>>>> 2.22.0
>>>>>>>
>>>>>>
>>>>>> --
>>>>>> Daniel Vetter
>>>>>> Software Engineer, Intel Corporation
>>>>>> http://blog.ffwll.ch
>>>>>
>>>>
>>>> _______________________________________________
>>>> dri-devel mailing list
>>>> dri-devel@lists.freedesktop.org
>>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>>>
>>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-17 7:14 ` Neil Armstrong
@ 2020-09-17 11:32 ` Daniel Vetter
0 siblings, 0 replies; 22+ messages in thread
From: Daniel Vetter @ 2020-09-17 11:32 UTC (permalink / raw)
To: Neil Armstrong; +Cc: dri-devel, linux-amlogic, linux-kernel
On Thu, Sep 17, 2020 at 09:14:33AM +0200, Neil Armstrong wrote:
> On 08/09/2020 10:46, Daniel Vetter wrote:
> > On Tue, Sep 08, 2020 at 10:06:03AM +0200, Neil Armstrong wrote:
> >> Hi,
> >>
> >> On 07/09/2020 20:03, Daniel Vetter wrote:
> >>> On Mon, Sep 07, 2020 at 11:03:29AM +0200, Neil Armstrong wrote:
> >>>> On 07/09/2020 10:44, Daniel Vetter wrote:
> >>>>> On Mon, Sep 07, 2020 at 10:43:51AM +0200, Daniel Vetter wrote:
> >>>>>> On Mon, Sep 07, 2020 at 10:18:25AM +0200, Neil Armstrong wrote:
> >>>>>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> >>>>>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> >>>>>>> Amlogic SoCs.
> >>>>>>>
> >>>>>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> >>>>>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> >>>>>>> Analog PHY in the proper way.
> >>>>>>>
> >>>>>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> >>>>>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
> >>>>>>>
> >>>>>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> >>>>>>> DW-MIPI-DSI transceiver.
> >>>>>>>
> >>>>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >>>>>>
> >>>>>> More dw-hdmi drivers which aren't bridges but components, and the thing is
> >>>>>> still midlayer-y as heck :-/
> >>>>>
> >>>>> *dw-dsi, but really they both work the same way and should both be fixed
> >>>>> ...
> >>>>
> >>>> They are bridges but since they have platform-dependent code due to theirs's generic IP
> >>>> nature, they need to be intanciated by components to sync with the platform code.
> >>>
> >>> Yeah that's how it currently works, but there's not much reason why it
> >>> needs to work like that. That platform glue code can also be put behind
> >>> the drm_bridge abstraction, and we could use the normal dt based bridge
> >>> lookup like for everything else.
> >>>
> >>> Afaiui the only reason dw-* bridge drivers work like that is because for
> >>> historical reasons we only had component.c at first, and none of the more
> >>> fancy dynamic bridge lookup. So would be really good to switch this all
> >>> over to a proper&clean bridge abstraction, and not leak everything around.
> >>
> >> Does it mean we should avoit using components, right ?
> >
> > Yup, at least when there's an established specific mechanism to handle
> > cross-driver interactions/EPROBE_DEFER.
> >
> > So if you want a drm_panel or drm_bridge or a clock or i2c or anything
> > else standardized like that, no component.c please. That's just for the
> > driver-specific glue when you have entirely IP-specific way of building up
> > a driver from components, which will never be reused outside of that
> > overall driver.
> >
> > Hence why dw-* using components is rather uncool.
> >
> >>> I've typed up what I think should be the way forward a few times already,
> >>> but thus far not even the todo.rst entry materialized:
> >>>
> >>> https://lore.kernel.org/dri-devel/20200430135841.GE10381@phenom.ffwll.local/
> >>>
> >>> If everyone is always about "not in my patch series" it'll never happen.
> >>
> >> Today, the dw-mipi-dsi and dw-mipi-hdmi has mandatory callbacks to implement
> >> vendor specific features, like :
> >> - hdmi/dsi phy handling when mixed into the glue/custom/synopsys but with platform specific values
> >> - platform specific mode validation
> >> - hpd setup => could use laurent's work here with no_connector, but how do we handle rxsense ???
> >> - dsi timings/lane mbps ? these are platform phy specific
> >>
> >> For amlogic, I can split the "component" code handling venc/vclk into a primary bridge and add a
> >> secondary driver only handling the glue around dw-mipi-dsi/dw-mipi-hdmi, would that be a good start ?
> >
> > I think what we should do here:
> >
> > - type up todo.rst with the overall structure we want to aim for, i.e.
> > where is the code, who sets up what, how are the bridges bound into the
> > overall driver.
>
> OK, sure, this can be a good start, but first I would like all the other bridge
> maintainers & reviewers to agree on the the wanted structure.
>
> >
> > - demidlayer dw-* enough so that the callbacks are gone, and it becomes
> > more a toolbox/library for building a dw-* driver. Maybe we're there
> > already.
>
> This is not really wanted, otherwise we would duplicate a large amount of code
> over all the platform glues, is this really wanted ?
>
> Today, they already are a toolbox, with different levels of callback neded
> depending on how deep the integration is.
Yeah I guess getting rid of all of them doesn't make that much sense.
> > - All new drivers then need to use the toolbox and have everything behind
> > a drm_bridge driver in drm/bridge/, with just default binding exposed to
> > drivers, no EXPORT_SYMBOL at all. Also no exported symbols used, this
> > should all be directly linked into the dw-*.ko imo and treated as
> > internals.
>
> In theory this is cool, in practice, this is impossible for meson_dw_hdmi,
> the first reason is how the registers are accessed for GX family, we need to
> define custom regmap read/write functions.
>
> For dw-mipi-dsi, it may be feasible, but again I don't see why vendor glue code
> should live in drm/bridge/ ?
>
> The last point, this will impact multiple platforms support in a single patchset,
> I do not have enough time available to make such changes and check for non-regression.
Well we'd need something that's gradual, i.e. new stuff works like a
pure bridge without component interactions or other stuff.
> > - We might need to split the header files to make that clean enough.
> >
> > - Once all existing dw-* users are converted, we ditch the EXPORT_SYMBOL
> > stuff completely (since I expect we'll just have one overall dw-dsi.ko
> > module with all bridge driver variants).
>
> ?
>
> why ? why load & add multiple vendor adaptation in a single module ?
>
> this sounds like a bad idea, sorry.
You don't have to, I guess you can have them all separately if that's
desired. Just feels like that'll make things more complicated.
> In the meantime, I'd really like to have this upstream, should this really wait for
> multiple months for tractations and rework ?
> I can rework a little to only have the dw-mipi-dsi glue and the encoder stuff in an
> another file, is this fine for a first step ?
The overall idea that I at least discussed with Laurent and Sam (who've
probably done most of the drm_bridge refactoring) is that we should push
for drm_bridge as the abstraction and interface point. So no component.c,
and the entire bridge in drm/bridge/ folder.
I guess the fundamental question is whether the dw-* drivers should be
drm_bridges, or just their own private stuff. And everyone doing their own
private stuff for integrating these things kinda defeats the point.
The other thing is that this is roughly bridge addition no 3 or so where
this gets discussed, and everyone is "nah this isn't my problem, I just
want to merge my code".
-Daniel
>
> Neil
>
> >
> > Cheers, Daniel
> >
> >
> >
> >>
> >> Neil
> >>
> >>>
> >>> Cheers, Daniel
> >>>
> >>>
> >>>>
> >>>> Neil
> >>>>
> >>>>>
> >>>>>>
> >>>>>> Can we try to fix this? There's a ton of this going on, and the more we
> >>>>>> add the old fashioned way the harder this gets to fix up for real.
> >>>>>> -Daniel
> >>>>>>
> >>>>>>> ---
> >>>>>>> drivers/gpu/drm/meson/Kconfig | 7 +
> >>>>>>> drivers/gpu/drm/meson/Makefile | 1 +
> >>>>>>> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> >>>>>>> 3 files changed, 570 insertions(+)
> >>>>>>> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>>>>
> >>>>>>> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> >>>>>>> index 9f9281dd49f8..385f6f23839b 100644
> >>>>>>> --- a/drivers/gpu/drm/meson/Kconfig
> >>>>>>> +++ b/drivers/gpu/drm/meson/Kconfig
> >>>>>>> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> >>>>>>> default y if DRM_MESON
> >>>>>>> select DRM_DW_HDMI
> >>>>>>> imply DRM_DW_HDMI_I2S_AUDIO
> >>>>>>> +
> >>>>>>> +config DRM_MESON_DW_MIPI_DSI
> >>>>>>> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> >>>>>>> + depends on DRM_MESON
> >>>>>>> + default y if DRM_MESON
> >>>>>>> + select DRM_DW_MIPI_DSI
> >>>>>>> + select GENERIC_PHY_MIPI_DPHY
> >>>>>>> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> >>>>>>> index 28a519cdf66b..2cc870e91182 100644
> >>>>>>> --- a/drivers/gpu/drm/meson/Makefile
> >>>>>>> +++ b/drivers/gpu/drm/meson/Makefile
> >>>>>>> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
> >>>>>>>
> >>>>>>> obj-$(CONFIG_DRM_MESON) += meson-drm.o
> >>>>>>> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> >>>>>>> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> >>>>>>> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>>>> new file mode 100644
> >>>>>>> index 000000000000..bbe1294fce7c
> >>>>>>> --- /dev/null
> >>>>>>> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> >>>>>>> @@ -0,0 +1,562 @@
> >>>>>>> +// SPDX-License-Identifier: GPL-2.0-or-later
> >>>>>>> +/*
> >>>>>>> + * Copyright (C) 2016 BayLibre, SAS
> >>>>>>> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> >>>>>>> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> >>>>>>> + */
> >>>>>>> +
> >>>>>>> +#include <linux/clk.h>
> >>>>>>> +#include <linux/component.h>
> >>>>>>> +#include <linux/kernel.h>
> >>>>>>> +#include <linux/module.h>
> >>>>>>> +#include <linux/of_device.h>
> >>>>>>> +#include <linux/of_graph.h>
> >>>>>>> +#include <linux/reset.h>
> >>>>>>> +#include <linux/phy/phy.h>
> >>>>>>> +
> >>>>>>> +#include <video/mipi_display.h>
> >>>>>>> +
> >>>>>>> +#include <drm/bridge/dw_mipi_dsi.h>
> >>>>>>> +#include <drm/drm_mipi_dsi.h>
> >>>>>>> +
> >>>>>>> +#include <drm/drm_atomic_helper.h>
> >>>>>>> +#include <drm/drm_device.h>
> >>>>>>> +#include <drm/drm_probe_helper.h>
> >>>>>>> +#include <drm/drm_print.h>
> >>>>>>> +
> >>>>>>> +#include "meson_drv.h"
> >>>>>>> +#include "meson_dw_mipi_dsi.h"
> >>>>>>> +#include "meson_registers.h"
> >>>>>>> +#include "meson_venc.h"
> >>>>>>> +
> >>>>>>> +#define DRIVER_NAME "meson-dw-mipi-dsi"
> >>>>>>> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> >>>>>>> +
> >>>>>>> +/* MIPI DSI/VENC Color Format Definitions */
> >>>>>>> +#define MIPI_DSI_VENC_COLOR_30B 0x0
> >>>>>>> +#define MIPI_DSI_VENC_COLOR_24B 0x1
> >>>>>>> +#define MIPI_DSI_VENC_COLOR_18B 0x2
> >>>>>>> +#define MIPI_DSI_VENC_COLOR_16B 0x3
> >>>>>>> +
> >>>>>>> +#define COLOR_16BIT_CFG_1 0x0
> >>>>>>> +#define COLOR_16BIT_CFG_2 0x1
> >>>>>>> +#define COLOR_16BIT_CFG_3 0x2
> >>>>>>> +#define COLOR_18BIT_CFG_1 0x3
> >>>>>>> +#define COLOR_18BIT_CFG_2 0x4
> >>>>>>> +#define COLOR_24BIT 0x5
> >>>>>>> +#define COLOR_20BIT_LOOSE 0x6
> >>>>>>> +#define COLOR_24_BIT_YCBCR 0x7
> >>>>>>> +#define COLOR_16BIT_YCBCR 0x8
> >>>>>>> +#define COLOR_30BIT 0x9
> >>>>>>> +#define COLOR_36BIT 0xa
> >>>>>>> +#define COLOR_12BIT 0xb
> >>>>>>> +#define COLOR_RGB_111 0xc
> >>>>>>> +#define COLOR_RGB_332 0xd
> >>>>>>> +#define COLOR_RGB_444 0xe
> >>>>>>> +
> >>>>>>> +/* MIPI DSI Relative REGISTERs Definitions */
> >>>>>>> +/* For MIPI_DSI_TOP_CNTL */
> >>>>>>> +#define BIT_DPI_COLOR_MODE 20
> >>>>>>> +#define BIT_IN_COLOR_MODE 16
> >>>>>>> +#define BIT_CHROMA_SUBSAMPLE 14
> >>>>>>> +#define BIT_COMP2_SEL 12
> >>>>>>> +#define BIT_COMP1_SEL 10
> >>>>>>> +#define BIT_COMP0_SEL 8
> >>>>>>> +#define BIT_DE_POL 6
> >>>>>>> +#define BIT_HSYNC_POL 5
> >>>>>>> +#define BIT_VSYNC_POL 4
> >>>>>>> +#define BIT_DPICOLORM 3
> >>>>>>> +#define BIT_DPISHUTDN 2
> >>>>>>> +#define BIT_EDPITE_INTR_PULSE 1
> >>>>>>> +#define BIT_ERR_INTR_PULSE 0
> >>>>>>> +
> >>>>>>> +/* HHI Registers */
> >>>>>>> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> >>>>>>> +#define VCLK2_DIV_MASK 0xff
> >>>>>>> +#define VCLK2_DIV_EN BIT(16)
> >>>>>>> +#define VCLK2_DIV_RESET BIT(17)
> >>>>>>> +#define CTS_ENCL_SEL_MASK (0xf << 12)
> >>>>>>> +#define CTS_ENCL_SEL_SHIFT 12
> >>>>>>> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> >>>>>>> +#define VCLK2_EN BIT(19)
> >>>>>>> +#define VCLK2_SEL_MASK (0x7 << 16)
> >>>>>>> +#define VCLK2_SEL_SHIFT 16
> >>>>>>> +#define VCLK2_SOFT_RESET BIT(15)
> >>>>>>> +#define VCLK2_DIV1_EN BIT(0)
> >>>>>>> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> >>>>>>> +#define CTS_ENCL_EN BIT(3)
> >>>>>>> +
> >>>>>>> +/**
> >>>>>>> + * DOC: MIPI DSI
> >>>>>>> + *
> >>>>>>> + */
> >>>>>>> +
> >>>>>>> +struct meson_dw_mipi_dsi {
> >>>>>>> + struct drm_encoder encoder;
> >>>>>>> + struct meson_drm *priv;
> >>>>>>> + struct device *dev;
> >>>>>>> + void __iomem *base;
> >>>>>>> + struct phy *phy;
> >>>>>>> + union phy_configure_opts phy_opts;
> >>>>>>> + struct dw_mipi_dsi *dmd;
> >>>>>>> + struct dw_mipi_dsi_plat_data pdata;
> >>>>>>> + struct mipi_dsi_device *dsi_device;
> >>>>>>> + unsigned long mode_flags;
> >>>>>>> + struct clk *px_clk;
> >>>>>>> +};
> >>>>>>> +#define encoder_to_meson_dw_mipi_dsi(x) \
> >>>>>>> + container_of(x, struct meson_dw_mipi_dsi, encoder)
> >>>>>>> +
> >>>>>>> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> >>>>>>> + struct drm_display_mode *mode)
> >>>>>>> +{
> >>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>>>> + unsigned int vclk2_div;
> >>>>>>> + unsigned int pll_rate;
> >>>>>>> + int ret;
> >>>>>>> +
> >>>>>>> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> >>>>>>> + vclk2_div = pll_rate / (mode->clock * 1000);
> >>>>>>> +
> >>>>>>> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> >>>>>>> + if (ret) {
> >>>>>>> + pr_err("Failed to set DSI PLL rate %lu\n",
> >>>>>>> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> >>>>>>> +
> >>>>>>> + return;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + /* Disable VCLK2 */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> >>>>>>> +
> >>>>>>> + /* Setup the VCLK2 divider value */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>>>> + VCLK2_DIV_MASK, (vclk2_div - 1));
> >>>>>>> +
> >>>>>>> + /* select gp0 for vclk2 */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>>>> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> >>>>>>> +
> >>>>>>> + /* enable vclk2 gate */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> >>>>>>> +
> >>>>>>> + /* select vclk2_div1 for encl */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>>>> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> >>>>>>> +
> >>>>>>> + /* release vclk2_div_reset and enable vclk2_div */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> >>>>>>> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> >>>>>>> +
> >>>>>>> + /* enable vclk2_div1 gate */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>>>> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> >>>>>>> +
> >>>>>>> + /* reset vclk2 */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>>>> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> >>>>>>> + VCLK2_SOFT_RESET, 0);
> >>>>>>> +
> >>>>>>> + /* enable encl_clk */
> >>>>>>> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> >>>>>>> + CTS_ENCL_EN, CTS_ENCL_EN);
> >>>>>>> +
> >>>>>>> + usleep_range(10000, 11000);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int dw_mipi_dsi_phy_init(void *priv_data)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>>>> +
> >>>>>>> +
> >>>>>>> + phy_power_on(mipi_dsi->phy);
> >>>>>>> +
> >>>>>>> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>>>> +
> >>>>>>> + phy_power_off(mipi_dsi->phy);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int
> >>>>>>> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> >>>>>>> + unsigned long mode_flags, u32 lanes, u32 format,
> >>>>>>> + unsigned int *lane_mbps)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>>>> +
> >>>>>>> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int
> >>>>>>> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> >>>>>>> + struct dw_mipi_dsi_dphy_timing *timing)
> >>>>>>> +{
> >>>>>>> + /* TOFIX handle other cases */
> >>>>>>> +
> >>>>>>> + timing->clk_lp2hs = 37;
> >>>>>>> + timing->clk_hs2lp = 135;
> >>>>>>> + timing->data_lp2hs = 50;
> >>>>>>> + timing->data_hs2lp = 3;
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int
> >>>>>>> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> >>>>>>> +{
> >>>>>>> + *esc_clk_rate = 4; /* Mhz */
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> >>>>>>> + .init = dw_mipi_dsi_phy_init,
> >>>>>>> + .power_off = dw_mipi_dsi_phy_power_off,
> >>>>>>> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> >>>>>>> + .get_timing = dw_mipi_dsi_phy_get_timing,
> >>>>>>> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> +/* Encoder */
> >>>>>>> +
> >>>>>>> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> >>>>>>> +{
> >>>>>>> + drm_encoder_cleanup(encoder);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> >>>>>>> + .destroy = meson_mipi_dsi_encoder_destroy,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> >>>>>>> + struct drm_crtc_state *crtc_state,
> >>>>>>> + struct drm_connector_state *conn_state)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>>>> +
> >>>>>>> + switch (mipi_dsi->dsi_device->format) {
> >>>>>>> + case MIPI_DSI_FMT_RGB888:
> >>>>>>> + break;
> >>>>>>> + case MIPI_DSI_FMT_RGB666:
> >>>>>>> + break;
> >>>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>>>>>> + case MIPI_DSI_FMT_RGB565:
> >>>>>>> + default:
> >>>>>>> + DRM_DEV_ERROR(mipi_dsi->dev,
> >>>>>>> + "invalid pixel format %d\n",
> >>>>>>> + mipi_dsi->dsi_device->format);
> >>>>>>> + return -EINVAL;
> >>>>>>> + };
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>>>> +
> >>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi =
> >>>>>>> + encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>>>> +
> >>>>>>> + writel_bits_relaxed(BIT(3), BIT(3),
> >>>>>>> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> >>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> >>>>>>> +{
> >>>>>>> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> >>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>>>>>> +
> >>>>>>> + writel_bits_relaxed(0xf, 0xf,
> >>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>>>>>> + writel_bits_relaxed(0xf, 0,
> >>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> >>>>>>> +
> >>>>>>> + writel_bits_relaxed(0x3, 0x3,
> >>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> >>>>>>> +
> >>>>>>> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> >>>>>>> + struct drm_display_mode *mode,
> >>>>>>> + struct drm_display_mode *adjusted_mode)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> >>>>>>> + unsigned int dpi_data_format, venc_data_width;
> >>>>>>> + struct meson_drm *priv = mipi_dsi->priv;
> >>>>>>> + int bpp;
> >>>>>>> + u32 reg;
> >>>>>>> +
> >>>>>>> + mipi_dsi->mode_flags = mode->flags;
> >>>>>>> +
> >>>>>>> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> >>>>>>> +
> >>>>>>> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> >>>>>>> + bpp, mipi_dsi->dsi_device->lanes,
> >>>>>>> + &mipi_dsi->phy_opts.mipi_dphy);
> >>>>>>> +
> >>>>>>> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> >>>>>>> +
> >>>>>>> + switch (mipi_dsi->dsi_device->format) {
> >>>>>>> + case MIPI_DSI_FMT_RGB888:
> >>>>>>> + dpi_data_format = COLOR_24BIT;
> >>>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> >>>>>>> + break;
> >>>>>>> + case MIPI_DSI_FMT_RGB666:
> >>>>>>> + dpi_data_format = COLOR_18BIT_CFG_2;
> >>>>>>> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> >>>>>>> + break;
> >>>>>>> + case MIPI_DSI_FMT_RGB666_PACKED:
> >>>>>>> + case MIPI_DSI_FMT_RGB565:
> >>>>>>> + /* invalid */
> >>>>>>> + break;
> >>>>>>> + };
> >>>>>>> +
> >>>>>>> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> >>>>>>> + meson_venc_mipi_dsi_mode_set(priv, mode);
> >>>>>>> +
> >>>>>>> + meson_encl_load_gamma(priv);
> >>>>>>> +
> >>>>>>> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> >>>>>>> +
> >>>>>>> + meson_dw_mipi_dsi_init(mipi_dsi);
> >>>>>>> +
> >>>>>>> + /* Configure Set color format for DPI register */
> >>>>>>> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> >>>>>>> + ~(0xf<<BIT_DPI_COLOR_MODE) &
> >>>>>>> + ~(0x7<<BIT_IN_COLOR_MODE) &
> >>>>>>> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> >>>>>>> +
> >>>>>>> + writel_relaxed(reg |
> >>>>>>> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> >>>>>>> + (venc_data_width << BIT_IN_COLOR_MODE) |
> >>>>>>> + 0 << BIT_COMP0_SEL |
> >>>>>>> + 1 << BIT_COMP1_SEL |
> >>>>>>> + 2 << BIT_COMP2_SEL |
> >>>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> >>>>>>> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> >>>>>>> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct drm_encoder_helper_funcs
> >>>>>>> + meson_mipi_dsi_encoder_helper_funcs = {
> >>>>>>> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> >>>>>>> + .disable = meson_mipi_dsi_encoder_disable,
> >>>>>>> + .enable = meson_mipi_dsi_encoder_enable,
> >>>>>>> + .mode_set = meson_mipi_dsi_encoder_mode_set,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> >>>>>>> + void *data)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>>>>>> + struct drm_device *drm = data;
> >>>>>>> + struct meson_drm *priv = drm->dev_private;
> >>>>>>> + struct drm_encoder *encoder;
> >>>>>>> + int ret;
> >>>>>>> +
> >>>>>>> + /* Check before if we are supposed to have a sub-device... */
> >>>>>>> + if (!mipi_dsi->dsi_device)
> >>>>>>> + return -EPROBE_DEFER;
> >>>>>>> +
> >>>>>>> + encoder = &mipi_dsi->encoder;
> >>>>>>> + mipi_dsi->priv = priv;
> >>>>>>> +
> >>>>>>> + /* Encoder */
> >>>>>>> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> >>>>>>> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> >>>>>>> + if (ret) {
> >>>>>>> + dev_err(priv->dev, "Failed to init DSI encoder\n");
> >>>>>>> + return ret;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> >>>>>>> +
> >>>>>>> + encoder->possible_crtcs = BIT(0);
> >>>>>>> +
> >>>>>>> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> >>>>>>> + if (ret) {
> >>>>>>> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> >>>>>>> + return ret;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + phy_init(mipi_dsi->phy);
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> >>>>>>> + void *data)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> >>>>>>> +
> >>>>>>> + dw_mipi_dsi_remove(mipi_dsi->dmd);
> >>>>>>> +
> >>>>>>> + phy_exit(mipi_dsi->phy);
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> >>>>>>> + .bind = meson_dw_mipi_dsi_bind,
> >>>>>>> + .unbind = meson_dw_mipi_dsi_unbind,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> +static int meson_dw_mipi_dsi_host_attach(void *priv_data,
> >>>>>>> + struct mipi_dsi_device *device)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>>>> +
> >>>>>>> + mipi_dsi->dsi_device = device;
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int meson_dw_mipi_dsi_host_detach(void *priv_data,
> >>>>>>> + struct mipi_dsi_device *device)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> >>>>>>> +
> >>>>>>> + if (device == mipi_dsi->dsi_device)
> >>>>>>> + mipi_dsi->dsi_device = NULL;
> >>>>>>> + else
> >>>>>>> + return -EINVAL;
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct dw_mipi_dsi_host_ops meson_dw_mipi_dsi_host_ops = {
> >>>>>>> + .attach = meson_dw_mipi_dsi_host_attach,
> >>>>>>> + .detach = meson_dw_mipi_dsi_host_detach,
> >>>>>>> +};
> >>>>>>> +
> >>>>>>> +static int meson_dw_mipi_dsi_probe(struct platform_device *pdev)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi;
> >>>>>>> + struct reset_control *top_rst;
> >>>>>>> + struct resource *res;
> >>>>>>> + int ret;
> >>>>>>> +
> >>>>>>> + mipi_dsi = devm_kzalloc(&pdev->dev, sizeof(*mipi_dsi), GFP_KERNEL);
> >>>>>>> + if (!mipi_dsi)
> >>>>>>> + return -ENOMEM;
> >>>>>>> +
> >>>>>>> + mipi_dsi->dev = &pdev->dev;
> >>>>>>> +
> >>>>>>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>>>>>> + mipi_dsi->base = devm_ioremap_resource(&pdev->dev, res);
> >>>>>>> + if (IS_ERR(mipi_dsi->base))
> >>>>>>> + return PTR_ERR(mipi_dsi->base);
> >>>>>>> +
> >>>>>>> + mipi_dsi->phy = devm_phy_get(&pdev->dev, "dphy");
> >>>>>>> + if (IS_ERR(mipi_dsi->phy)) {
> >>>>>>> + ret = PTR_ERR(mipi_dsi->phy);
> >>>>>>> + dev_err(&pdev->dev, "failed to get mipi dphy: %d\n", ret);
> >>>>>>> + return ret;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + mipi_dsi->px_clk = devm_clk_get(&pdev->dev, "px_clk");
> >>>>>>> + if (IS_ERR(mipi_dsi->px_clk)) {
> >>>>>>> + dev_err(&pdev->dev, "Unable to get PLL clk\n");
> >>>>>>> + return PTR_ERR(mipi_dsi->px_clk);
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + /*
> >>>>>>> + * We use a TOP reset signal because the APB reset signal
> >>>>>>> + * is handled by the TOP control registers.
> >>>>>>> + */
> >>>>>>> + top_rst = devm_reset_control_get_exclusive(&pdev->dev, "top");
> >>>>>>> + if (IS_ERR(top_rst)) {
> >>>>>>> + ret = PTR_ERR(top_rst);
> >>>>>>> +
> >>>>>>> + if (ret != -EPROBE_DEFER)
> >>>>>>> + dev_err(&pdev->dev, "Unable to get reset control: %d\n", ret);
> >>>>>>> +
> >>>>>>> + return ret;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + ret = clk_prepare_enable(mipi_dsi->px_clk);
> >>>>>>> + if (ret) {
> >>>>>>> + dev_err(&pdev->dev, "Unable to prepare/enable PX clock\n");
> >>>>>>> + goto err_clkdisable;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + reset_control_assert(top_rst);
> >>>>>>> + usleep_range(10, 20);
> >>>>>>> + reset_control_deassert(top_rst);
> >>>>>>> +
> >>>>>>> + /* MIPI DSI Controller */
> >>>>>>> +
> >>>>>>> + mipi_dsi->pdata.base = mipi_dsi->base;
> >>>>>>> + mipi_dsi->pdata.max_data_lanes = 4;
> >>>>>>> + mipi_dsi->pdata.phy_ops = &meson_dw_mipi_dsi_phy_ops;
> >>>>>>> + mipi_dsi->pdata.host_ops = &meson_dw_mipi_dsi_host_ops;
> >>>>>>> + mipi_dsi->pdata.priv_data = mipi_dsi;
> >>>>>>> + platform_set_drvdata(pdev, mipi_dsi);
> >>>>>>> +
> >>>>>>> + mipi_dsi->dmd = dw_mipi_dsi_probe(pdev, &mipi_dsi->pdata);
> >>>>>>> + if (IS_ERR(mipi_dsi->dmd)) {
> >>>>>>> + ret = PTR_ERR(mipi_dsi->dmd);
> >>>>>>> + if (ret != -EPROBE_DEFER)
> >>>>>>> + dev_err(&pdev->dev,
> >>>>>>> + "Failed to probe dw_mipi_dsi: %d\n", ret);
> >>>>>>> + goto err_clkdisable;
> >>>>>>> + }
> >>>>>>> +
> >>>>>>> + return component_add(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>>>>>> +
> >>>>>>> +err_clkdisable:
> >>>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>>>>>> +
> >>>>>>> + return ret;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static int meson_dw_mipi_dsi_remove(struct platform_device *pdev)
> >>>>>>> +{
> >>>>>>> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(&pdev->dev);
> >>>>>>> +
> >>>>>>> + component_del(mipi_dsi->dev, &meson_dw_mipi_dsi_ops);
> >>>>>>> +
> >>>>>>> + clk_disable_unprepare(mipi_dsi->px_clk);
> >>>>>>> +
> >>>>>>> + return 0;
> >>>>>>> +}
> >>>>>>> +
> >>>>>>> +static const struct of_device_id meson_dw_mipi_dsi_of_table[] = {
> >>>>>>> + { .compatible = "amlogic,meson-axg-dw-mipi-dsi", },
> >>>>>>> + { }
> >>>>>>> +};
> >>>>>>> +MODULE_DEVICE_TABLE(of, meson_dw_mipi_dsi_of_table);
> >>>>>>> +
> >>>>>>> +static struct platform_driver meson_dw_mipi_dsi_platform_driver = {
> >>>>>>> + .probe = meson_dw_mipi_dsi_probe,
> >>>>>>> + .remove = meson_dw_mipi_dsi_remove,
> >>>>>>> + .driver = {
> >>>>>>> + .name = DRIVER_NAME,
> >>>>>>> + .of_match_table = meson_dw_mipi_dsi_of_table,
> >>>>>>> + },
> >>>>>>> +};
> >>>>>>> +module_platform_driver(meson_dw_mipi_dsi_platform_driver);
> >>>>>>> +
> >>>>>>> +MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
> >>>>>>> +MODULE_DESCRIPTION(DRIVER_DESC);
> >>>>>>> +MODULE_LICENSE("GPL");
> >>>>>>> --
> >>>>>>> 2.22.0
> >>>>>>>
> >>>>>>
> >>>>>> --
> >>>>>> Daniel Vetter
> >>>>>> Software Engineer, Intel Corporation
> >>>>>> http://blog.ffwll.ch
> >>>>>
> >>>>
> >>>> _______________________________________________
> >>>> dri-devel mailing list
> >>>> dri-devel@lists.freedesktop.org
> >>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >>>
> >>
> >> _______________________________________________
> >> dri-devel mailing list
> >> dri-devel@lists.freedesktop.org
> >> https://lists.freedesktop.org/mailman/listinfo/dri-devel
> >
>
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2020-09-07 8:18 ` [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver Neil Armstrong
2020-09-07 8:43 ` Daniel Vetter
@ 2022-01-12 7:24 ` Jagan Teki
2022-01-12 8:19 ` Neil Armstrong
1 sibling, 1 reply; 22+ messages in thread
From: Jagan Teki @ 2022-01-12 7:24 UTC (permalink / raw)
To: Neil Armstrong; +Cc: daniel, linux-amlogic, linux-kernel, dri-devel
Hi Neil,
On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> Amlogic SoCs.
>
> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> Analog PHY in the proper way.
>
> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> is derived and feeds the ENCL encoder and the VIU pixel reader.
>
> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> DW-MIPI-DSI transceiver.
>
> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> ---
> drivers/gpu/drm/meson/Kconfig | 7 +
> drivers/gpu/drm/meson/Makefile | 1 +
> drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 562 ++++++++++++++++++++++
> 3 files changed, 570 insertions(+)
> create mode 100644 drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
>
> diff --git a/drivers/gpu/drm/meson/Kconfig b/drivers/gpu/drm/meson/Kconfig
> index 9f9281dd49f8..385f6f23839b 100644
> --- a/drivers/gpu/drm/meson/Kconfig
> +++ b/drivers/gpu/drm/meson/Kconfig
> @@ -16,3 +16,10 @@ config DRM_MESON_DW_HDMI
> default y if DRM_MESON
> select DRM_DW_HDMI
> imply DRM_DW_HDMI_I2S_AUDIO
> +
> +config DRM_MESON_DW_MIPI_DSI
> + tristate "MIPI DSI Synopsys Controller support for Amlogic Meson Display"
> + depends on DRM_MESON
> + default y if DRM_MESON
> + select DRM_DW_MIPI_DSI
> + select GENERIC_PHY_MIPI_DPHY
> diff --git a/drivers/gpu/drm/meson/Makefile b/drivers/gpu/drm/meson/Makefile
> index 28a519cdf66b..2cc870e91182 100644
> --- a/drivers/gpu/drm/meson/Makefile
> +++ b/drivers/gpu/drm/meson/Makefile
> @@ -5,3 +5,4 @@ meson-drm-y += meson_rdma.o meson_osd_afbcd.o
>
> obj-$(CONFIG_DRM_MESON) += meson-drm.o
> obj-$(CONFIG_DRM_MESON_DW_HDMI) += meson_dw_hdmi.o
> +obj-$(CONFIG_DRM_MESON_DW_MIPI_DSI) += meson_dw_mipi_dsi.o
> diff --git a/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> new file mode 100644
> index 000000000000..bbe1294fce7c
> --- /dev/null
> +++ b/drivers/gpu/drm/meson/meson_dw_mipi_dsi.c
> @@ -0,0 +1,562 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * Copyright (C) 2016 BayLibre, SAS
> + * Author: Neil Armstrong <narmstrong@baylibre.com>
> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/reset.h>
> +#include <linux/phy/phy.h>
> +
> +#include <video/mipi_display.h>
> +
> +#include <drm/bridge/dw_mipi_dsi.h>
> +#include <drm/drm_mipi_dsi.h>
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_device.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/drm_print.h>
> +
> +#include "meson_drv.h"
> +#include "meson_dw_mipi_dsi.h"
> +#include "meson_registers.h"
> +#include "meson_venc.h"
> +
> +#define DRIVER_NAME "meson-dw-mipi-dsi"
> +#define DRIVER_DESC "Amlogic Meson MIPI-DSI DRM driver"
> +
> +/* MIPI DSI/VENC Color Format Definitions */
> +#define MIPI_DSI_VENC_COLOR_30B 0x0
> +#define MIPI_DSI_VENC_COLOR_24B 0x1
> +#define MIPI_DSI_VENC_COLOR_18B 0x2
> +#define MIPI_DSI_VENC_COLOR_16B 0x3
> +
> +#define COLOR_16BIT_CFG_1 0x0
> +#define COLOR_16BIT_CFG_2 0x1
> +#define COLOR_16BIT_CFG_3 0x2
> +#define COLOR_18BIT_CFG_1 0x3
> +#define COLOR_18BIT_CFG_2 0x4
> +#define COLOR_24BIT 0x5
> +#define COLOR_20BIT_LOOSE 0x6
> +#define COLOR_24_BIT_YCBCR 0x7
> +#define COLOR_16BIT_YCBCR 0x8
> +#define COLOR_30BIT 0x9
> +#define COLOR_36BIT 0xa
> +#define COLOR_12BIT 0xb
> +#define COLOR_RGB_111 0xc
> +#define COLOR_RGB_332 0xd
> +#define COLOR_RGB_444 0xe
> +
> +/* MIPI DSI Relative REGISTERs Definitions */
> +/* For MIPI_DSI_TOP_CNTL */
> +#define BIT_DPI_COLOR_MODE 20
> +#define BIT_IN_COLOR_MODE 16
> +#define BIT_CHROMA_SUBSAMPLE 14
> +#define BIT_COMP2_SEL 12
> +#define BIT_COMP1_SEL 10
> +#define BIT_COMP0_SEL 8
> +#define BIT_DE_POL 6
> +#define BIT_HSYNC_POL 5
> +#define BIT_VSYNC_POL 4
> +#define BIT_DPICOLORM 3
> +#define BIT_DPISHUTDN 2
> +#define BIT_EDPITE_INTR_PULSE 1
> +#define BIT_ERR_INTR_PULSE 0
> +
> +/* HHI Registers */
> +#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
> +#define VCLK2_DIV_MASK 0xff
> +#define VCLK2_DIV_EN BIT(16)
> +#define VCLK2_DIV_RESET BIT(17)
> +#define CTS_ENCL_SEL_MASK (0xf << 12)
> +#define CTS_ENCL_SEL_SHIFT 12
> +#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
> +#define VCLK2_EN BIT(19)
> +#define VCLK2_SEL_MASK (0x7 << 16)
> +#define VCLK2_SEL_SHIFT 16
> +#define VCLK2_SOFT_RESET BIT(15)
> +#define VCLK2_DIV1_EN BIT(0)
> +#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
> +#define CTS_ENCL_EN BIT(3)
> +
> +/**
> + * DOC: MIPI DSI
> + *
> + */
> +
> +struct meson_dw_mipi_dsi {
> + struct drm_encoder encoder;
> + struct meson_drm *priv;
> + struct device *dev;
> + void __iomem *base;
> + struct phy *phy;
> + union phy_configure_opts phy_opts;
> + struct dw_mipi_dsi *dmd;
> + struct dw_mipi_dsi_plat_data pdata;
> + struct mipi_dsi_device *dsi_device;
> + unsigned long mode_flags;
> + struct clk *px_clk;
> +};
> +#define encoder_to_meson_dw_mipi_dsi(x) \
> + container_of(x, struct meson_dw_mipi_dsi, encoder)
> +
> +static void dw_mipi_dsi_set_vclk(struct meson_dw_mipi_dsi *mipi_dsi,
> + struct drm_display_mode *mode)
> +{
> + struct meson_drm *priv = mipi_dsi->priv;
> + unsigned int vclk2_div;
> + unsigned int pll_rate;
> + int ret;
> +
> + pll_rate = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate;
> + vclk2_div = pll_rate / (mode->clock * 1000);
> +
> + ret = clk_set_rate(mipi_dsi->px_clk, pll_rate);
> + if (ret) {
> + pr_err("Failed to set DSI PLL rate %lu\n",
> + mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate);
> +
> + return;
> + }
> +
> + /* Disable VCLK2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, 0);
> +
> + /* Setup the VCLK2 divider value */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + VCLK2_DIV_MASK, (vclk2_div - 1));
> +
> + /* select gp0 for vclk2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SEL_MASK, (0 << VCLK2_SEL_SHIFT));
> +
> + /* enable vclk2 gate */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL, VCLK2_EN, VCLK2_EN);
> +
> + /* select vclk2_div1 for encl */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + CTS_ENCL_SEL_MASK, (8 << CTS_ENCL_SEL_SHIFT));
> +
> + /* release vclk2_div_reset and enable vclk2_div */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_DIV,
> + VCLK2_DIV_EN | VCLK2_DIV_RESET, VCLK2_DIV_EN);
> +
> + /* enable vclk2_div1 gate */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_DIV1_EN, VCLK2_DIV1_EN);
> +
> + /* reset vclk2 */
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SOFT_RESET, VCLK2_SOFT_RESET);
> + regmap_update_bits(priv->hhi, HHI_VIID_CLK_CNTL,
> + VCLK2_SOFT_RESET, 0);
> +
> + /* enable encl_clk */
> + regmap_update_bits(priv->hhi, HHI_VID_CLK_CNTL2,
> + CTS_ENCL_EN, CTS_ENCL_EN);
> +
> + usleep_range(10000, 11000);
> +}
> +
> +static int dw_mipi_dsi_phy_init(void *priv_data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> +
> + phy_power_on(mipi_dsi->phy);
> +
> + writel_relaxed(1, priv->io_base + _REG(ENCL_VIDEO_EN));
> +
> + return 0;
> +}
> +
> +static void dw_mipi_dsi_phy_power_off(void *priv_data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + phy_power_off(mipi_dsi->phy);
> +}
> +
> +static int
> +dw_mipi_dsi_get_lane_mbps(void *priv_data, const struct drm_display_mode *mode,
> + unsigned long mode_flags, u32 lanes, u32 format,
> + unsigned int *lane_mbps)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = priv_data;
> +
> + *lane_mbps = mipi_dsi->phy_opts.mipi_dphy.hs_clk_rate / 1000000;
> +
> + return 0;
> +}
> +
> +static int
> +dw_mipi_dsi_phy_get_timing(void *priv_data, unsigned int lane_mbps,
> + struct dw_mipi_dsi_dphy_timing *timing)
> +{
> + /* TOFIX handle other cases */
> +
> + timing->clk_lp2hs = 37;
> + timing->clk_hs2lp = 135;
> + timing->data_lp2hs = 50;
> + timing->data_hs2lp = 3;
> +
> + return 0;
> +}
> +
> +static int
> +dw_mipi_dsi_get_esc_clk_rate(void *priv_data, unsigned int *esc_clk_rate)
> +{
> + *esc_clk_rate = 4; /* Mhz */
> +
> + return 0;
> +}
> +
> +static const struct dw_mipi_dsi_phy_ops meson_dw_mipi_dsi_phy_ops = {
> + .init = dw_mipi_dsi_phy_init,
> + .power_off = dw_mipi_dsi_phy_power_off,
> + .get_lane_mbps = dw_mipi_dsi_get_lane_mbps,
> + .get_timing = dw_mipi_dsi_phy_get_timing,
> + .get_esc_clk_rate = dw_mipi_dsi_get_esc_clk_rate,
> +};
> +
> +/* Encoder */
> +
> +static void meson_mipi_dsi_encoder_destroy(struct drm_encoder *encoder)
> +{
> + drm_encoder_cleanup(encoder);
> +}
> +
> +static const struct drm_encoder_funcs meson_mipi_dsi_encoder_funcs = {
> + .destroy = meson_mipi_dsi_encoder_destroy,
> +};
> +
> +static int meson_mipi_dsi_encoder_atomic_check(struct drm_encoder *encoder,
> + struct drm_crtc_state *crtc_state,
> + struct drm_connector_state *conn_state)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> +
> + switch (mipi_dsi->dsi_device->format) {
> + case MIPI_DSI_FMT_RGB888:
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + case MIPI_DSI_FMT_RGB565:
> + default:
> + DRM_DEV_ERROR(mipi_dsi->dev,
> + "invalid pixel format %d\n",
> + mipi_dsi->dsi_device->format);
> + return -EINVAL;
> + };
> +
> + return 0;
> +}
> +
> +static void meson_mipi_dsi_encoder_disable(struct drm_encoder *encoder)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> +}
> +
> +static void meson_mipi_dsi_encoder_enable(struct drm_encoder *encoder)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi =
> + encoder_to_meson_dw_mipi_dsi(encoder);
> + struct meson_drm *priv = mipi_dsi->priv;
> +
> + writel_bits_relaxed(BIT(3), BIT(3),
> + priv->io_base + _REG(ENCL_VIDEO_MODE_ADV));
> + writel_relaxed(0, priv->io_base + _REG(ENCL_TST_EN));
> +}
> +
> +static void meson_dw_mipi_dsi_init(struct meson_dw_mipi_dsi *mipi_dsi)
> +{
> + writel_relaxed((1 << 4) | (1 << 5) | (0 << 6),
> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> +
> + writel_bits_relaxed(0xf, 0xf,
> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> + writel_bits_relaxed(0xf, 0,
> + mipi_dsi->base + MIPI_DSI_TOP_SW_RESET);
> +
> + writel_bits_relaxed(0x3, 0x3,
> + mipi_dsi->base + MIPI_DSI_TOP_CLK_CNTL);
> +
> + writel_relaxed(0, mipi_dsi->base + MIPI_DSI_TOP_MEM_PD);
> +}
> +
> +static void meson_mipi_dsi_encoder_mode_set(struct drm_encoder *encoder,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = encoder_to_meson_dw_mipi_dsi(encoder);
> + unsigned int dpi_data_format, venc_data_width;
> + struct meson_drm *priv = mipi_dsi->priv;
> + int bpp;
> + u32 reg;
> +
> + mipi_dsi->mode_flags = mode->flags;
> +
> + bpp = mipi_dsi_pixel_format_to_bpp(mipi_dsi->dsi_device->format);
> +
> + phy_mipi_dphy_get_default_config(mode->clock * 1000,
> + bpp, mipi_dsi->dsi_device->lanes,
> + &mipi_dsi->phy_opts.mipi_dphy);
> +
> + phy_configure(mipi_dsi->phy, &mipi_dsi->phy_opts);
> +
> + switch (mipi_dsi->dsi_device->format) {
> + case MIPI_DSI_FMT_RGB888:
> + dpi_data_format = COLOR_24BIT;
> + venc_data_width = MIPI_DSI_VENC_COLOR_24B;
> + break;
> + case MIPI_DSI_FMT_RGB666:
> + dpi_data_format = COLOR_18BIT_CFG_2;
> + venc_data_width = MIPI_DSI_VENC_COLOR_18B;
> + break;
> + case MIPI_DSI_FMT_RGB666_PACKED:
> + case MIPI_DSI_FMT_RGB565:
> + /* invalid */
> + break;
> + };
> +
> + dw_mipi_dsi_set_vclk(mipi_dsi, mode);
> + meson_venc_mipi_dsi_mode_set(priv, mode);
> +
> + meson_encl_load_gamma(priv);
> +
> + writel_relaxed(0, priv->io_base + _REG(ENCL_VIDEO_EN));
> +
> + meson_dw_mipi_dsi_init(mipi_dsi);
> +
> + /* Configure Set color format for DPI register */
> + reg = readl_relaxed(mipi_dsi->base + MIPI_DSI_TOP_CNTL) &
> + ~(0xf<<BIT_DPI_COLOR_MODE) &
> + ~(0x7<<BIT_IN_COLOR_MODE) &
> + ~(0x3<<BIT_CHROMA_SUBSAMPLE);
> +
> + writel_relaxed(reg |
> + (dpi_data_format << BIT_DPI_COLOR_MODE) |
> + (venc_data_width << BIT_IN_COLOR_MODE) |
> + 0 << BIT_COMP0_SEL |
> + 1 << BIT_COMP1_SEL |
> + 2 << BIT_COMP2_SEL |
> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NHSYNC ? 0 : BIT(BIT_HSYNC_POL)) |
> + (mipi_dsi->mode_flags & DRM_MODE_FLAG_NVSYNC ? 0 : BIT(BIT_VSYNC_POL)),
> + mipi_dsi->base + MIPI_DSI_TOP_CNTL);
> +}
> +
> +static const struct drm_encoder_helper_funcs
> + meson_mipi_dsi_encoder_helper_funcs = {
> + .atomic_check = meson_mipi_dsi_encoder_atomic_check,
> + .disable = meson_mipi_dsi_encoder_disable,
> + .enable = meson_mipi_dsi_encoder_enable,
> + .mode_set = meson_mipi_dsi_encoder_mode_set,
> +};
> +
> +static int meson_dw_mipi_dsi_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> + struct drm_device *drm = data;
> + struct meson_drm *priv = drm->dev_private;
> + struct drm_encoder *encoder;
> + int ret;
> +
> + /* Check before if we are supposed to have a sub-device... */
> + if (!mipi_dsi->dsi_device)
> + return -EPROBE_DEFER;
> +
> + encoder = &mipi_dsi->encoder;
> + mipi_dsi->priv = priv;
> +
> + /* Encoder */
> + ret = drm_encoder_init(drm, encoder, &meson_mipi_dsi_encoder_funcs,
> + DRM_MODE_ENCODER_DSI, "meson_mipi_dsi");
> + if (ret) {
> + dev_err(priv->dev, "Failed to init DSI encoder\n");
> + return ret;
> + }
> +
> + drm_encoder_helper_add(encoder, &meson_mipi_dsi_encoder_helper_funcs);
> +
> + encoder->possible_crtcs = BIT(0);
> +
> + ret = dw_mipi_dsi_bind(mipi_dsi->dmd, encoder);
> + if (ret) {
> + DRM_DEV_ERROR(dev, "Failed to bind: %d\n", ret);
> + return ret;
> + }
> +
> + phy_init(mipi_dsi->phy);
> +
> + return 0;
> +}
> +
> +static void meson_dw_mipi_dsi_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct meson_dw_mipi_dsi *mipi_dsi = dev_get_drvdata(dev);
> +
> + dw_mipi_dsi_remove(mipi_dsi->dmd);
> +
> + phy_exit(mipi_dsi->phy);
> +}
> +
> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> + .bind = meson_dw_mipi_dsi_bind,
> + .unbind = meson_dw_mipi_dsi_unbind,
> +};
Do you thought of non-component based meson DSI like STM DSI? It
require changes from meson drm but just to understand if you have any
such plan.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2022-01-12 7:24 ` Jagan Teki
@ 2022-01-12 8:19 ` Neil Armstrong
2022-01-20 11:03 ` Jagan Teki
0 siblings, 1 reply; 22+ messages in thread
From: Neil Armstrong @ 2022-01-12 8:19 UTC (permalink / raw)
To: Jagan Teki; +Cc: daniel, linux-amlogic, linux-kernel, dri-devel
Hi,
On 12/01/2022 08:24, Jagan Teki wrote:
> Hi Neil,
>
> On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>> Amlogic SoCs.
>>
>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
>> Analog PHY in the proper way.
>>
>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
>> is derived and feeds the ENCL encoder and the VIU pixel reader.
>>
>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
>> DW-MIPI-DSI transceiver.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>> ---
[..]
>> +
>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
>> + .bind = meson_dw_mipi_dsi_bind,
>> + .unbind = meson_dw_mipi_dsi_unbind,
>> +};
>
> Do you thought of non-component based meson DSI like STM DSI? It
> require changes from meson drm but just to understand if you have any
> such plan.
I have no such plans for now, note this serie has been rewritten at [1] but still
with based with components.
If worth it, the plan is to get it with components and than yes if it's simpler
drop components completely.
I'll have a look at how ST does
Neil
[1] https://lore.kernel.org/r/20220107145515.613009-1-narmstrong@baylibre.com
>
> Thanks,
> Jagan.
>
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2022-01-12 8:19 ` Neil Armstrong
@ 2022-01-20 11:03 ` Jagan Teki
2022-01-20 13:28 ` Neil Armstrong
0 siblings, 1 reply; 22+ messages in thread
From: Jagan Teki @ 2022-01-20 11:03 UTC (permalink / raw)
To: Neil Armstrong; +Cc: daniel, linux-amlogic, linux-kernel, dri-devel
On Wed, Jan 12, 2022 at 1:49 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>
> Hi,
>
> On 12/01/2022 08:24, Jagan Teki wrote:
> > Hi Neil,
> >
> > On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
> >>
> >> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
> >> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
> >> Amlogic SoCs.
> >>
> >> This adds support for the Glue managing the transceiver, mimicing the init flow provided
> >> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
> >> Analog PHY in the proper way.
> >>
> >> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
> >> is derived and feeds the ENCL encoder and the VIU pixel reader.
> >>
> >> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
> >> DW-MIPI-DSI transceiver.
> >>
> >> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
> >> ---
>
> [..]
>
> >> +
> >> +static const struct component_ops meson_dw_mipi_dsi_ops = {
> >> + .bind = meson_dw_mipi_dsi_bind,
> >> + .unbind = meson_dw_mipi_dsi_unbind,
> >> +};
> >
> > Do you thought of non-component based meson DSI like STM DSI? It
> > require changes from meson drm but just to understand if you have any
> > such plan.
>
> I have no such plans for now, note this serie has been rewritten at [1] but still
> with based with components.
>
> If worth it, the plan is to get it with components and than yes if it's simpler
> drop components completely.
Dropping components make the pipeline well suited for bridges as we
are moving bridge-driven pipelines in other areas.
>
> I'll have a look at how ST does
ST has no components. As I said above, eventually there would be
common bridge driver for dw-mipi-dsi if meson and rockchip moving away
from components.
Thanks,
Jagan.
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH 6/6] drm/meson: add support for MIPI-DSI transceiver
2022-01-20 11:03 ` Jagan Teki
@ 2022-01-20 13:28 ` Neil Armstrong
0 siblings, 0 replies; 22+ messages in thread
From: Neil Armstrong @ 2022-01-20 13:28 UTC (permalink / raw)
To: Jagan Teki; +Cc: daniel, linux-amlogic, linux-kernel, dri-devel
Hi Jagan,
On 20/01/2022 12:03, Jagan Teki wrote:
> On Wed, Jan 12, 2022 at 1:49 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>
>> Hi,
>>
>> On 12/01/2022 08:24, Jagan Teki wrote:
>>> Hi Neil,
>>>
>>> On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong <narmstrong@baylibre.com> wrote:
>>>>
>>>> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a), with a custom
>>>> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue on other
>>>> Amlogic SoCs.
>>>>
>>>> This adds support for the Glue managing the transceiver, mimicing the init flow provided
>>>> by Amlogic to setup the ENCl encoder, the glue, the transceiver, the digital D-PHY and the
>>>> Analog PHY in the proper way.
>>>>
>>>> The DW-MIPI-DSI transceiver + D-PHY are directly clocked by the VCLK2 clock, which pixel clock
>>>> is derived and feeds the ENCL encoder and the VIU pixel reader.
>>>>
>>>> An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
>>>> DW-MIPI-DSI transceiver.
>>>>
>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>>> ---
>>
>> [..]
>>
>>>> +
>>>> +static const struct component_ops meson_dw_mipi_dsi_ops = {
>>>> + .bind = meson_dw_mipi_dsi_bind,
>>>> + .unbind = meson_dw_mipi_dsi_unbind,
>>>> +};
>>>
>>> Do you thought of non-component based meson DSI like STM DSI? It
>>> require changes from meson drm but just to understand if you have any
>>> such plan.
>>
>> I have no such plans for now, note this serie has been rewritten at [1] but still
>> with based with components.
>>
>> If worth it, the plan is to get it with components and than yes if it's simpler
>> drop components completely.
>
> Dropping components make the pipeline well suited for bridges as we
> are moving bridge-driven pipelines in other areas.
>
>>
>> I'll have a look at how ST does
>
> ST has no components. As I said above, eventually there would be
> common bridge driver for dw-mipi-dsi if meson and rockchip moving away
> from components.
ST driver is much more simpler.
And having a common dw-mipi-dsi is unreal since each HW has a different glue HW
me must handle. Even if we moved all the glue handling under drm/bridge/synopsys,
we would need a different set of callbacks for each HW for each compatible
which is basically the actual situation except components.
Neil
>
> Thanks,
> Jagan.
>
^ permalink raw reply [flat|nested] 22+ messages in thread