* [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY @ 2020-10-30 17:29 Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy ` (3 more replies) 0 siblings, 4 replies; 24+ messages in thread From: Dan Murphy @ 2020-10-30 17:29 UTC (permalink / raw) To: davem, andrew, f.fainelli, hkallweit1, robh Cc: devicetree, netdev, linux-kernel, Dan Murphy Hello The DP83TD510 is an Ethernet PHY supporting single pair of twisted wires. The PHY is capable of 10Mbps communication over long distances and exceeds the IEEE 802.3cg 10BASE-T1L single-pair Ethernet specification. The PHY supports various voltage level signalling and can be forced to support a specific voltage or allowed to perfrom auto negotiation on the voltage level. The default for the PHY is auto negotiation but if the PHY is forced to a specific voltage then the LP must also support the same voltage. Add the 10BASE-T1L linkmodes for ethtool to properly advertise the PHY's capability. Dan Dan Murphy (4): ethtool: Add 10base-T1L link mode entries dt-bindings: net: Add Rx/Tx output configuration for 10base T1L dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY .../devicetree/bindings/net/ethernet-phy.yaml | 5 + .../devicetree/bindings/net/ti,dp83td510.yaml | 62 ++ drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 681 ++++++++++++++++++ drivers/net/phy/phy-core.c | 4 +- include/uapi/linux/ethtool.h | 2 + net/ethtool/common.c | 2 + net/ethtool/linkmodes.c | 2 + 9 files changed, 764 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml create mode 100644 drivers/net/phy/dp83td510.c -- 2.28.0.585.ge1cfff676549 ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries 2020-10-30 17:29 [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY Dan Murphy @ 2020-10-30 17:29 ` Dan Murphy 2020-10-30 19:43 ` Andrew Lunn 2020-11-05 2:42 ` Florian Fainelli 2020-10-30 17:29 ` [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L Dan Murphy ` (2 subsequent siblings) 3 siblings, 2 replies; 24+ messages in thread From: Dan Murphy @ 2020-10-30 17:29 UTC (permalink / raw) To: davem, andrew, f.fainelli, hkallweit1, robh Cc: devicetree, netdev, linux-kernel, Dan Murphy Add entries for the 10base-T1L full and half duplex supported modes. $ ethtool eth0 Supported ports: [ TP ] Supported link modes: 10baseT1L/Half 10baseT1L/Full Supported pause frame use: Symmetric Receive-only Supports auto-negotiation: Yes Supported FEC modes: Not reported Advertised link modes: 10baseT1L/Half 10baseT1L/Full Advertised pause frame use: No Advertised auto-negotiation: No Advertised FEC modes: Not reported Speed: 10Mb/s Duplex: Full Auto-negotiation: on Port: MII PHYAD: 1 Transceiver: external Supports Wake-on: gs Wake-on: d SecureOn password: 00:00:00:00:00:00 Current message level: 0x00000000 (0) Link detected: yes Signed-off-by: Dan Murphy <dmurphy@ti.com> --- drivers/net/phy/phy-core.c | 4 +++- include/uapi/linux/ethtool.h | 2 ++ net/ethtool/common.c | 2 ++ net/ethtool/linkmodes.c | 2 ++ 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 8d333d3084ed..616fae7f0c86 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -13,7 +13,7 @@ */ const char *phy_speed_to_str(int speed) { - BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 92, + BUILD_BUG_ON_MSG(__ETHTOOL_LINK_MODE_MASK_NBITS != 94, "Enum ethtool_link_mode_bit_indices and phylib are out of sync. " "If a speed or mode has been added please update phy_speed_to_str " "and the PHY settings array.\n"); @@ -175,6 +175,8 @@ static const struct phy_setting settings[] = { /* 10M */ PHY_SETTING( 10, FULL, 10baseT_Full ), PHY_SETTING( 10, HALF, 10baseT_Half ), + PHY_SETTING( 10, FULL, 10baseT1L_Full ), + PHY_SETTING( 10, HALF, 10baseT1L_Half ), }; #undef PHY_SETTING diff --git a/include/uapi/linux/ethtool.h b/include/uapi/linux/ethtool.h index 9ca87bc73c44..16b6ea7548d3 100644 --- a/include/uapi/linux/ethtool.h +++ b/include/uapi/linux/ethtool.h @@ -1619,6 +1619,8 @@ enum ethtool_link_mode_bit_indices { ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89, ETHTOOL_LINK_MODE_100baseFX_Half_BIT = 90, ETHTOOL_LINK_MODE_100baseFX_Full_BIT = 91, + ETHTOOL_LINK_MODE_10baseT1L_Half_BIT = 92, + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT = 93, /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS }; diff --git a/net/ethtool/common.c b/net/ethtool/common.c index 24036e3055a1..95f87febc742 100644 --- a/net/ethtool/common.c +++ b/net/ethtool/common.c @@ -194,6 +194,8 @@ const char link_mode_names[][ETH_GSTRING_LEN] = { __DEFINE_LINK_MODE_NAME(400000, CR4, Full), __DEFINE_LINK_MODE_NAME(100, FX, Half), __DEFINE_LINK_MODE_NAME(100, FX, Full), + __DEFINE_LINK_MODE_NAME(10, T1L, Half), + __DEFINE_LINK_MODE_NAME(10, T1L, Full), }; static_assert(ARRAY_SIZE(link_mode_names) == __ETHTOOL_LINK_MODE_MASK_NBITS); diff --git a/net/ethtool/linkmodes.c b/net/ethtool/linkmodes.c index c5bcb9abc8b9..a8fab6fb1b30 100644 --- a/net/ethtool/linkmodes.c +++ b/net/ethtool/linkmodes.c @@ -264,6 +264,8 @@ static const struct link_mode_info link_mode_params[] = { __DEFINE_LINK_MODE_PARAMS(400000, CR4, Full), __DEFINE_LINK_MODE_PARAMS(100, FX, Half), __DEFINE_LINK_MODE_PARAMS(100, FX, Full), + __DEFINE_LINK_MODE_PARAMS(10, T1L, Half), + __DEFINE_LINK_MODE_PARAMS(10, T1L, Full), }; const struct nla_policy ethnl_linkmodes_set_policy[] = { -- 2.28.0.585.ge1cfff676549 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy @ 2020-10-30 19:43 ` Andrew Lunn 2020-11-05 2:42 ` Florian Fainelli 1 sibling, 0 replies; 24+ messages in thread From: Andrew Lunn @ 2020-10-30 19:43 UTC (permalink / raw) To: Dan Murphy Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Fri, Oct 30, 2020 at 12:29:47PM -0500, Dan Murphy wrote: > Add entries for the 10base-T1L full and half duplex supported modes. > > $ ethtool eth0 > Supported ports: [ TP ] > Supported link modes: 10baseT1L/Half 10baseT1L/Full > Supported pause frame use: Symmetric Receive-only > Supports auto-negotiation: Yes > Supported FEC modes: Not reported > Advertised link modes: 10baseT1L/Half 10baseT1L/Full > Advertised pause frame use: No > Advertised auto-negotiation: No > Advertised FEC modes: Not reported > Speed: 10Mb/s > Duplex: Full > Auto-negotiation: on > Port: MII > PHYAD: 1 > Transceiver: external > Supports Wake-on: gs > Wake-on: d > SecureOn password: 00:00:00:00:00:00 > Current message level: 0x00000000 (0) > > Link detected: yes > > Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy 2020-10-30 19:43 ` Andrew Lunn @ 2020-11-05 2:42 ` Florian Fainelli 1 sibling, 0 replies; 24+ messages in thread From: Florian Fainelli @ 2020-11-05 2:42 UTC (permalink / raw) To: Dan Murphy, davem, andrew, hkallweit1, robh Cc: devicetree, netdev, linux-kernel On 10/30/2020 10:29 AM, Dan Murphy wrote: > Add entries for the 10base-T1L full and half duplex supported modes. > > $ ethtool eth0 > Supported ports: [ TP ] > Supported link modes: 10baseT1L/Half 10baseT1L/Full > Supported pause frame use: Symmetric Receive-only > Supports auto-negotiation: Yes > Supported FEC modes: Not reported > Advertised link modes: 10baseT1L/Half 10baseT1L/Full > Advertised pause frame use: No > Advertised auto-negotiation: No > Advertised FEC modes: Not reported > Speed: 10Mb/s > Duplex: Full > Auto-negotiation: on > Port: MII > PHYAD: 1 > Transceiver: external > Supports Wake-on: gs > Wake-on: d > SecureOn password: 00:00:00:00:00:00 > Current message level: 0x00000000 (0) > > Link detected: yes > > Signed-off-by: Dan Murphy <dmurphy@ti.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> -- Florian ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L 2020-10-30 17:29 [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy @ 2020-10-30 17:29 ` Dan Murphy 2020-10-30 19:56 ` Andrew Lunn 2020-10-30 17:29 ` [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy 3 siblings, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-10-30 17:29 UTC (permalink / raw) To: davem, andrew, f.fainelli, hkallweit1, robh Cc: devicetree, netdev, linux-kernel, Dan Murphy Per the 802.3cg spec the 10base T1L can operate at 2 different differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to drive that output is dependent on the PHY's on board power supply. This common feature is applicable to all 10base T1L PHYs so this binding property belongs in a top level ethernet document. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- Documentation/devicetree/bindings/net/ethernet-phy.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 6dd72faebd89..5cad653e143b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -174,6 +174,11 @@ properties: PHY's that have configurable TX internal delays. If this property is present then the PHY applies the TX delay. + tx-rx-output-high: + type: boolean + description: | + Enable the 2.4v p2p differential output voltage for 10base-T1L PHYs. + required: - reg -- 2.28.0.585.ge1cfff676549 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L 2020-10-30 17:29 ` [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L Dan Murphy @ 2020-10-30 19:56 ` Andrew Lunn 2020-11-03 16:52 ` Dan Murphy 2020-11-04 22:08 ` Rob Herring 0 siblings, 2 replies; 24+ messages in thread From: Andrew Lunn @ 2020-10-30 19:56 UTC (permalink / raw) To: Dan Murphy Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote: > Per the 802.3cg spec the 10base T1L can operate at 2 different > differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to > drive that output is dependent on the PHY's on board power supply. Hi Dan So this property is about the board being able to support the needed voltages? The PHY is not forced into 2.4v p2p, it just says the PHY can operate at 2.4v and the board will not melt, blow a fuse, etc? I actually think it is normal to specify the reverse. List the maximum that device can do because of board restrictions. e.g. - maximum-power-milliwatt : Maximum module power consumption Specifies the maximum power consumption allowable by a module in the slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. - max-link-speed: If present this property specifies PCI gen for link capability. Host drivers could add this as a strategy to avoid unnecessary operation for unsupported link speed, for instance, trying to do training for unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are invalid. - max-microvolt : The maximum voltage value supplied to the haptic motor. [The unit of the voltage is a micro] So i think this property should be max-tx-rx-p2p = <1000>; to limit it to 1000mv p2p because of board PSU limitations, and it is free to do 22000mv is the property is not present. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L 2020-10-30 19:56 ` Andrew Lunn @ 2020-11-03 16:52 ` Dan Murphy 2020-11-03 17:07 ` Andrew Lunn 2020-11-04 22:08 ` Rob Herring 1 sibling, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-11-03 16:52 UTC (permalink / raw) To: Andrew Lunn Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel Andrew On 10/30/20 2:56 PM, Andrew Lunn wrote: > On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote: >> Per the 802.3cg spec the 10base T1L can operate at 2 different >> differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to >> drive that output is dependent on the PHY's on board power supply. > Hi Dan > > So this property is about the board being able to support the needed > voltages? The PHY is not forced into 2.4v p2p, it just says the PHY > can operate at 2.4v and the board will not melt, blow a fuse, etc? > > I actually think it is normal to specify the reverse. List the maximum > that device can do because of board restrictions. e.g. > > - maximum-power-milliwatt : Maximum module power consumption > Specifies the maximum power consumption allowable by a module in the > slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. > > - max-link-speed: > If present this property specifies PCI gen for link capability. Host > drivers could add this as a strategy to avoid unnecessary operation for > unsupported link speed, for instance, trying to do training for > unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' > for gen2, and '1' for gen1. Any other values are invalid. > > - max-microvolt : The maximum voltage value supplied to the haptic motor. > [The unit of the voltage is a micro] > > So i think this property should be > > max-tx-rx-p2p = <1000>; When I was re-writing the code I couldn't come up with a better property name but I like this one. I will implement it. Do you have any issue with the property being in the ethernet-phy.yaml? Dan ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L 2020-11-03 16:52 ` Dan Murphy @ 2020-11-03 17:07 ` Andrew Lunn 0 siblings, 0 replies; 24+ messages in thread From: Andrew Lunn @ 2020-11-03 17:07 UTC (permalink / raw) To: Dan Murphy Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel > Do you have any issue with the property being in the ethernet-phy.yaml? It seems generic enough. Increasing the voltage increases the power requirements, and maybe not all boards are capable of that. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L 2020-10-30 19:56 ` Andrew Lunn 2020-11-03 16:52 ` Dan Murphy @ 2020-11-04 22:08 ` Rob Herring 1 sibling, 0 replies; 24+ messages in thread From: Rob Herring @ 2020-11-04 22:08 UTC (permalink / raw) To: Andrew Lunn Cc: Dan Murphy, davem, f.fainelli, hkallweit1, devicetree, netdev, linux-kernel On Fri, Oct 30, 2020 at 08:56:55PM +0100, Andrew Lunn wrote: > On Fri, Oct 30, 2020 at 12:29:48PM -0500, Dan Murphy wrote: > > Per the 802.3cg spec the 10base T1L can operate at 2 different > > differential voltages 1v p2p and 2.4v p2p. The abiility of the PHY to > > drive that output is dependent on the PHY's on board power supply. > > Hi Dan > > So this property is about the board being able to support the needed > voltages? The PHY is not forced into 2.4v p2p, it just says the PHY > can operate at 2.4v and the board will not melt, blow a fuse, etc? > > I actually think it is normal to specify the reverse. List the maximum > that device can do because of board restrictions. e.g. > > - maximum-power-milliwatt : Maximum module power consumption > Specifies the maximum power consumption allowable by a module in the > slot, in milli-Watts. Presently, modules can be up to 1W, 1.5W or 2W. > > - max-link-speed: > If present this property specifies PCI gen for link capability. Host > drivers could add this as a strategy to avoid unnecessary operation for > unsupported link speed, for instance, trying to do training for > unsupported link speed, etc. Must be '4' for gen4, '3' for gen3, '2' > for gen2, and '1' for gen1. Any other values are invalid. > > - max-microvolt : The maximum voltage value supplied to the haptic motor. > [The unit of the voltage is a micro] > > So i think this property should be > > max-tx-rx-p2p = <1000>; > > to limit it to 1000mv p2p because of board PSU limitations, and it is > free to do 22000mv is the property is not present. '-microvolt' suffix please. > > Andrew > ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY 2020-10-30 17:29 [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L Dan Murphy @ 2020-10-30 17:29 ` Dan Murphy 2020-10-31 9:27 ` Ioana Ciornei 2020-11-02 17:12 ` Rob Herring 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy 3 siblings, 2 replies; 24+ messages in thread From: Dan Murphy @ 2020-10-30 17:29 UTC (permalink / raw) To: davem, andrew, f.fainelli, hkallweit1, robh Cc: devicetree, netdev, linux-kernel, Dan Murphy The DP83TD510 is a 10M single twisted pair Ethernet PHY Signed-off-by: Dan Murphy <dmurphy@ti.com> --- .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml new file mode 100644 index 000000000000..aef949c1cfdd --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Texas Instruments Incorporated +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: TI DP83TD510 ethernet PHY + +allOf: + - $ref: "ethernet-controller.yaml#" + - $ref: "ethernet-phy.yaml#" + +maintainers: + - Dan Murphy <dmurphy@ti.com> + +description: | + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and + RGMII interfaces. + + Specifications about the Ethernet PHY can be found at: + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf + +properties: + reg: + maxItems: 1 + + tx-fifo-depth: + description: | + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble + depths. The valid nibble depths are 4, 5, 6 and 8. + enum: [ 4, 5, 6, 8 ] + default: 5 + + rx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the RX internal delay + for the PHY. The internal delay for the PHY is fixed to 30ns relative + to receive data. + + tx-internal-delay-ps: + description: | + Setting this property to a non-zero number sets the TX internal delay + for the PHY. The internal delay for the PHY has a range of -4 to 4ns + relative to transmit data. + +required: + - reg + +examples: + - | + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + tx-rx-output-high; + tx-fifo-depth = <5>; + rx-internal-delay-ps = <1>; + tx-internal-delay-ps = <1>; + }; + }; -- 2.28.0.585.ge1cfff676549 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY 2020-10-30 17:29 ` [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY Dan Murphy @ 2020-10-31 9:27 ` Ioana Ciornei 2020-11-02 17:12 ` Rob Herring 1 sibling, 0 replies; 24+ messages in thread From: Ioana Ciornei @ 2020-10-31 9:27 UTC (permalink / raw) To: Dan Murphy Cc: davem, andrew, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Fri, Oct 30, 2020 at 12:29:49PM -0500, Dan Murphy wrote: > The DP83TD510 is a 10M single twisted pair Ethernet PHY > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml > > diff --git a/Documentation/devicetree/bindings/net/ti,dp83td510.yaml b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > new file mode 100644 > index 000000000000..aef949c1cfdd > --- /dev/null > +++ b/Documentation/devicetree/bindings/net/ti,dp83td510.yaml > @@ -0,0 +1,62 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +# Copyright (C) 2020 Texas Instruments Incorporated > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/net/ti,dp83td510.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: TI DP83TD510 ethernet PHY > + > +allOf: > + - $ref: "ethernet-controller.yaml#" > + - $ref: "ethernet-phy.yaml#" > + > +maintainers: > + - Dan Murphy <dmurphy@ti.com> > + > +description: | > + The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and > + RGMII interfaces. > + > + Specifications about the Ethernet PHY can be found at: > + http://www.ti.com/lit/ds/symlink/dp83td510e.pdf > + > +properties: > + reg: > + maxItems: 1 > + > + tx-fifo-depth: > + description: | > + Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble > + depths. The valid nibble depths are 4, 5, 6 and 8. > + enum: [ 4, 5, 6, 8 ] > + default: 5 > + > + rx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the RX internal delay > + for the PHY. The internal delay for the PHY is fixed to 30ns relative > + to receive data. > + > + tx-internal-delay-ps: > + description: | > + Setting this property to a non-zero number sets the TX internal delay > + for the PHY. The internal delay for the PHY has a range of -4 to 4ns > + relative to transmit data. > + > +required: > + - reg > + I just got this feedback so I am passing it on. Every dtbinding should have the additionalProperties set to false so that dtbs_check can actually catch if there is a undefined property used. Ioana ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY 2020-10-30 17:29 ` [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY Dan Murphy 2020-10-31 9:27 ` Ioana Ciornei @ 2020-11-02 17:12 ` Rob Herring 1 sibling, 0 replies; 24+ messages in thread From: Rob Herring @ 2020-11-02 17:12 UTC (permalink / raw) To: Dan Murphy Cc: devicetree, hkallweit1, davem, netdev, f.fainelli, linux-kernel, andrew On Fri, 30 Oct 2020 12:29:49 -0500, Dan Murphy wrote: > The DP83TD510 is a 10M single twisted pair Ethernet PHY > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > .../devicetree/bindings/net/ti,dp83td510.yaml | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) > create mode 100644 Documentation/devicetree/bindings/net/ti,dp83td510.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: {'$id': 'http://devicetree.org/schemas/net/ti,dp83td510.yaml#', '$schema': 'http://devicetree.org/meta-schemas/core.yaml#', 'title': 'TI DP83TD510 ethernet PHY', 'allOf': [{'$ref': 'ethernet-controller.yaml#'}, {'$ref': 'ethernet-phy.yaml#'}], 'maintainers': ['Dan Murphy <dmurphy@ti.com>'], 'description': 'The PHY is an twisted pair 10Mbps Ethernet PHY that support MII, RMII and\nRGMII interfaces.\n\nSpecifications about the Ethernet PHY can be found at:\n http://www.ti.com/lit/ds/symlink/dp83td510e.pdf\n', 'properties': {'reg': {'maxItems': 1}, 'tx-fifo-depth': {'description': 'Transmitt FIFO depth for RMII mode. The PHY only exposes 4 nibble\ndepths. The valid nibble depths are 4, 5, 6 and 8.\n', 'enum': [4, 5, 6, 8], 'default': 5}, 'rx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the RX internal delay\nfor the PHY. The internal delay for the PHY is fixed to 30ns relative\nto receive data.\n'}, 'tx-internal-delay-ps': {'description': 'Setting this property to a non-zero number sets the TX internal delay\nfor the PHY. The internal delay for the PHY has a range of -4 to 4ns\nrelative to transmit data.\n'}}, 'required': ['reg'], 'examples': ['mdio0 {\n #address-cells = <1>;\n #size-cells = <0>;\n ethphy0: ethernet-phy@0 {\n reg = <0>;\n tx-rx-output-high;\n tx-fifo-depth = <5>;\n rx-internal-delay-ps = <1>;\n tx-internal-delay-ps = <1>;\n };\n};\n']} is not valid under any of the given schemas {'oneOf': [{'required': ['unevaluatedProperties']}, {'required': ['additionalProperties']}]} (Possible causes of the failure): /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: 'unevaluatedProperties' is a required property /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/net/ti,dp83td510.yaml: ignoring, error in schema: warning: no schema found in file: ./Documentation/devicetree/bindings/net/ti,dp83td510.yaml See https://patchwork.ozlabs.org/patch/1391184 The base for the patch is generally the last rc1. Any dependencies should be noted. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit. ^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 17:29 [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY Dan Murphy ` (2 preceding siblings ...) 2020-10-30 17:29 ` [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY Dan Murphy @ 2020-10-30 17:29 ` Dan Murphy 2020-10-30 20:15 ` Andrew Lunn ` (2 more replies) 3 siblings, 3 replies; 24+ messages in thread From: Dan Murphy @ 2020-10-30 17:29 UTC (permalink / raw) To: davem, andrew, f.fainelli, hkallweit1, robh Cc: devicetree, netdev, linux-kernel, Dan Murphy The DP83TD510E is an ultra-low power Ethernet physical layer transceiver that supports 10M single pair cable. The device supports both 2.4-V p2p and 1-V p2p output voltage as defined by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via the device tree or the device is defaulted to auto negotiation to determine the proper p2p voltage. Signed-off-by: Dan Murphy <dmurphy@ti.com> --- drivers/net/phy/Kconfig | 6 + drivers/net/phy/Makefile | 1 + drivers/net/phy/dp83td510.c | 681 ++++++++++++++++++++++++++++++++++++ 3 files changed, 688 insertions(+) create mode 100644 drivers/net/phy/dp83td510.c diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 698bea312adc..017252e1504c 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -302,6 +302,12 @@ config DP83869_PHY Currently supports the DP83869 PHY. This PHY supports copper and fiber connections. +config DP83TD510_PHY + tristate "Texas Instruments DP83TD510 10M Single Pair Ethernet PHY" + help + Support for the DP83TD510 Ethernet PHY. This PHY supports a 10M single + pair Ethernet connection. + config VITESSE_PHY tristate "Vitesse PHYs" help diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index a13e402074cf..bf62ce211eb4 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -56,6 +56,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o obj-$(CONFIG_DP83867_PHY) += dp83867.o obj-$(CONFIG_DP83869_PHY) += dp83869.o obj-$(CONFIG_DP83TC811_PHY) += dp83tc811.o +obj-$(CONFIG_DP83TD510_PHY) += dp83td510.o obj-$(CONFIG_FIXED_PHY) += fixed_phy.o obj-$(CONFIG_ICPLUS_PHY) += icplus.o obj-$(CONFIG_INTEL_XWAY_PHY) += intel-xway.o diff --git a/drivers/net/phy/dp83td510.c b/drivers/net/phy/dp83td510.c new file mode 100644 index 000000000000..0d1471bdcd45 --- /dev/null +++ b/drivers/net/phy/dp83td510.c @@ -0,0 +1,681 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Driver for the Texas Instruments DP83TD510 PHY + * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <linux/ethtool.h> +#include <linux/etherdevice.h> +#include <linux/kernel.h> +#include <linux/mii.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/phy.h> +#include <linux/netdevice.h> + +#define DP83TD510E_PHY_ID 0x20000180 +#define DP83TD510_DEVADDR_AN 0x7 +#define DP83TD510_DEVADDR 0x1f +#define DP83TD510_PMD_DEVADDR 0x1 + +#define DP83TD510_MII_REG 0x0 +#define DP83TD510_PHY_STAT 0x10 +#define DP83TD510_GEN_CFG 0x11 +#define DP83TD510_INT_REG1 0x12 +#define DP83TD510_INT_REG2 0x13 +#define DP83TD510_MAC_CFG_1 0x17 + +#define DP83TD510_ANEG_CTRL 0x200 +#define DP83TD510_PMD_CTRL 0x834 + +#define DP83TD510_SOR_1 0x467 + +#define DP83TD510_HW_RESET BIT(15) +#define DP83TD510_SW_RESET BIT(14) + +/* GEN CFG bits */ +#define DP83TD510_INT_OE BIT(0) +#define DP83TD510_INT_EN BIT(1) + +/* INT REG 1 bits */ +#define DP83TD510_INT1_ESD_EN BIT(3) +#define DP83TD510_INT1_LINK_EN BIT(5) +#define DP83TD510_INT1_RHF_EN BIT(7) +#define DP83TD510_INT1_ESD BIT(11) +#define DP83TD510_INT1_LINK BIT(13) +#define DP83TD510_INT1_RHF BIT(15) + +/* INT REG 2 bits */ +#define DP83TD510_INT2_POR_EN BIT(0) +#define DP83TD510_INT2_POL_EN BIT(1) +#define DP83TD510_INT2_PAGE_EN BIT(5) +#define DP83TD510_INT2_POR BIT(8) +#define DP83TD510_INT2_POL BIT(9) +#define DP83TD510_INT2_PAGE BIT(13) + +/* MAC CFG bits */ +#define DP83TD510_RX_CLK_SHIFT BIT(12) +#define DP83TD510_TX_CLK_SHIFT BIT(11) + +#define DP83TD510_MASTER_MODE BIT(14) +#define DP83TD510_AUTO_NEG_EN BIT(12) +#define DP83TD510_2_4V BIT(7) +#define DP83TD510_RGMII BIT(8) + +#define DP83TD510_FIFO_DEPTH_MASK GENMASK(6, 5) +#define DP83TD510_FIFO_DEPTH_4_B_NIB 0 +#define DP83TD510_FIFO_DEPTH_5_B_NIB BIT(5) +#define DP83TD510_FIFO_DEPTH_6_B_NIB BIT(6) +#define DP83TD510_FIFO_DEPTH_8_B_NIB (BIT(5) | BIT(6)) + +const int dp83td510_feature_array[3] = { + ETHTOOL_LINK_MODE_10baseT1L_Half_BIT, + ETHTOOL_LINK_MODE_10baseT1L_Full_BIT, + ETHTOOL_LINK_MODE_TP_BIT, +}; + +struct dp83td510_private { + bool hi_diff_output; + u32 tx_fifo_depth; + u32 rgmii_delay; + bool is_rgmii; +}; + +struct dp83td510_init_reg { + int reg; + int val; +}; + +static struct dp83td510_init_reg dp83td510_master_1_0[] = { + { 0x000d, 0x0001 }, /* force 1.0v swing */ + { 0x000e, 0x08f6 }, + { 0x000d, 0x4001 }, + { 0x000e, 0x0000 }, + { 0x0608, 0x003b }, /* disable_0_transition */ + { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */ + { 0x081a, 0x67c0 }, /* deq offset for 1V swing */ + { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */ + { 0x0830, 0x05a3 }, /* Enable energy lost fallback */ + { 0x0855, 0x1b55 }, /* MSE Threshold change */ + { 0x0831, 0x0403 }, /* energy detect threshold */ + { 0x0856, 0x1800 }, /* good1 MSE threshold change */ + { 0x0857, 0x8fa0 }, /* Enable fallback to phase 1 on watchdog trigger */ + { 0x0871, 0x000c }, /* TED input changed to slicer_in without FFE */ + { 0x0883, 0x022e }, /* Enable Rx Filter, Change PGA threshold for Short Cable detection */ + { 0x0402, 0x1800 }, /* Adjusr LD swing */ + { 0x0878, 0x2248 }, /* Change PI up/down polarity */ + { 0x010c, 0x0008 }, /* tx filter coefficient */ + { 0x0112, 0x1212 }, /* tx filter scaling factor */ + { 0x0809, 0x5c80 }, /* AGC retrain */ + { 0x0803, 0x1529 }, /* Master Ph1 Back-off */ + { 0x0804, 0x1a33 }, /* Master Ph1 Back-off */ + { 0x0805, 0x1f3d }, /* Master Ph1 Back-off */ + { 0x0850, 0x045b }, /* hybrid gain & delay */ + { 0x0874, 0x6967 }, /* kp step 0 for master */ + { 0x0852, 0x7800 }, /* FAGC init gain */ + { 0x0806, 0x1e1e }, /* Master/Slave Ph2 Back-off */ + { 0x0807, 0x2525 }, /* Master/Slave Ph2 Back-off */ + { 0x0808, 0x2c2c }, /* Master/Slave Ph2 Back-off */ + { 0x0850, 0x0590 }, /* Hybrid Gain/Delay Code */ + { 0x0827, 0x4000 }, /* Echo Fixed Delay */ + { 0x0849, 0x0fe4 }, /* Hybrid Cal enable */ + { 0x084b, 0x04b5 }, /* Echo Score Sel */ + { 0x0018, 0x0043 }, /* Set CRS/RX_DV pin as RX_DV for RMII repeater mode */ +}; + +static struct dp83td510_init_reg dp83td510_slave_1_0[] = { + { 0x000d, 0x0001 }, /* force 1.0v swing */ + { 0x000d, 0x4001 }, + { 0x000e, 0x0000 }, + { 0x0608, 0x003b }, /* disable_0_transition */ + { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */ + { 0x081a, 0x67c0 }, /* deq offset for 1V swing */ + { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */ + { 0x0830, 0x05a3 }, /* Enable energy lost fallback */ + { 0x0855, 0x1b55 }, /* MSE Threshold change */ + { 0x0831, 0x0403 }, /* energy detect threshold */ + { 0x0856, 0x1800 }, /* good1 MSE threshold change */ + { 0x0857, 0x8fa0 }, /* Enable fallback to phase 1 on watchdog trigger */ + { 0x0871, 0x000c }, /* TED input changed to slicer_in without FFE */ + { 0x0883, 0x022e }, /* Enable Rx Filter, PGA threshold for Short Cable detection */ + { 0x0402, 0x1800 }, /* Adjusr LD swing */ + { 0x0878, 0x2248 }, /* Change PI up/down polarity */ + { 0x010c, 0x0008 }, /* tx filter coefficient */ + { 0x0112, 0x1212 }, /* tx filter scaling factor */ + { 0x0809, 0x5c80 }, /* AGC retrain */ + { 0x0803, 0x1529 }, /* Master Ph1 Back-off */ + { 0x0804, 0x1a33 }, /* Master Ph1 Back-off */ + { 0x0805, 0x1f3d }, /* Master Ph1 Back-off */ + { 0x0850, 0x045b }, /* hybrid gain & delay */ + { 0x0874, 0x6967 }, /* kp step 0 for master */ + { 0x0852, 0x7800 }, /* FAGC init gain */ + { 0x0806, 0x1e1e }, /* Master/Slave Ph2 Back-off */ + { 0x0807, 0x2525 }, /* Master/Slave Ph2 Back-off */ + { 0x0808, 0x2c2c }, /* Master/Slave Ph2 Back-off */ + { 0x0850, 0x0590 }, /* Hybrid Gain/Delay Code */ + { 0x0827, 0x4000 }, /* Echo Fixed Delay */ + { 0x0849, 0x0fe4 }, /* Hybrid Cal enable */ + { 0x084b, 0x04b5 }, /* Echo Score Sel */ + { 0x0018, 0x0043 }, /* Set CRS/RX_DV pin as RX_DV for RMII repeater mode */ +}; + +static struct dp83td510_init_reg dp83td510_master_2_4[] = { + { 0x000d, 0x0001 }, /* force 2.4v swing */ + { 0x000e, 0x08f6 }, + { 0x000d, 0x4001 }, + { 0x000e, 0x1000 }, + { 0x0608, 0x003b }, /* disable_0_transition */ + { 0x0862, 0x39f8 }, /* AGC Gain during Autoneg */ + { 0x081a, 0x67c0 }, /* deq offset for 1V swing */ + { 0x081c, 0xfb62 }, /* deq offset for 2.4V swing */ + { 0x0830, 0x05a3 }, /* Enable energy lost fallback */ + { 0x0855, 0x1b55 }, /* MSE Threshold change */ + { 0x0831, 0x0403 }, /* energy detect threshold */ + { 0x0856, 0x1800 }, /* good1 MSE threshold change */ + { 0x0857, 0x8fa0 }, /* Enable fallback to phase 1 on watchdog trigger */ + { 0x0871, 0x000c }, /* TED input changed to slicer_in without FFE */ + { 0x0883, 0x022e }, /* Enable Rx Filter, Change PGA threshold for Short Cable detection */ + { 0x0402, 0x1800 }, /* Adjusr LD swing */ + { 0x0878, 0x2248 }, /* Change PI up/down polarity */ + { 0x010c, 0x0008 }, /* tx filter coefficient */ + { 0x0112, 0x1212 }, /* tx filter scaling factor */ + { 0x0809, 0x5c80 }, /* AGC retrain */ + { 0x0803, 0x1529 }, /* Master Ph1 Back-off */ + { 0x0804, 0x1a33 }, /* Master Ph1 Back-off */ + { 0x0805, 0x1f3d }, /* Master Ph1 Back-off */ + { 0x0850, 0x045b }, /* hybrid gain & delay */ + { 0x0874, 0x6967 }, /* kp step 0 for master */ + { 0x0852, 0x7800 }, /* FAGC init gain */ + { 0x0806, 0x1e1e }, /* Master/Slave Ph2 Back-off */ + { 0x0807, 0x2525 }, /* Master/Slave Ph2 Back-off */ + { 0x0808, 0x2c2c }, /* Master/Slave Ph2 Back-off */ + { 0x0850, 0x0590 }, /* Hybrid Gain/Delay Code */ + { 0x0827, 0x4000 }, /* Echo Fixed Delay */ + { 0x0849, 0x0fe4 }, /* Hybrid Cal enable */ + { 0x084b, 0x04b5 }, /* Echo Score Sel */ + { 0x0018, 0x0043 }, /* Set CRS/RX_DV pin as RX_DV for RMII repeater mode */ +}; + +static struct dp83td510_init_reg dp83td510_slave_2_4[] = { + { 0x000d, 0x0001}, /* force 2.4v swing */ + { 0x000e, 0x08f6}, + { 0x000d, 0x4001}, + { 0x000e, 0x1000}, + { 0x0608, 0x003b}, /* disable_0_transition */ + { 0x0862, 0x39f8}, /* AGC Gain during Autoneg */ + { 0x081a, 0x67c0}, /* deq offset for 1V swing */ + { 0x081c, 0xfb62}, /* deq offset for 2.4V swing */ + { 0x0830, 0x05a3}, /* Enable energy lost fallback */ + { 0x0855, 0x1b55}, /* MSE Threshold change */ + { 0x0831, 0x0403}, /* energy detect threshold */ + { 0x0856, 0x1800}, /* good1 MSE threshold change */ + { 0x0857, 0x8fa0}, /* Enable fallback to phase 1 on watchdog trigger */ + { 0x0871, 0x000c}, /* TED input changed to slicer_in without FFE */ + { 0x0883, 0x022e}, /* Enable Rx Filter, Change PGA threshold for Short Cable detection */ + { 0x0402, 0x1800}, /* Adjusr LD swing */ + { 0x0878, 0x2248}, /* Change PI up/down polarity */ + { 0x010c, 0x0008}, /* tx filter coefficient */ + { 0x0112, 0x1212}, /* tx filter scaling factor */ + { 0x0809, 0x5c80}, /* AGC retrain */ + { 0x0803, 0x1529}, /* Master Ph1 Back-off */ + { 0x0804, 0x1a33}, /* Master Ph1 Back-off */ + { 0x0805, 0x1f3d}, /* Master Ph1 Back-off */ + { 0x0850, 0x045b}, /* hybrid gain & delay */ + { 0x0874, 0x6967}, /* kp step 0 for master */ + { 0x0852, 0x7800}, /* FAGC init gain */ + { 0x0806, 0x1e1e}, /* Master/Slave Ph2 Back-off */ + { 0x0807, 0x2525}, /* Master/Slave Ph2 Back-off */ + { 0x0808, 0x2c2c}, /* Master/Slave Ph2 Back-off */ + { 0x0850, 0x0590}, /* Hybrid Gain/Delay Code */ + { 0x0827, 0x4000}, /* Echo Fixed Delay */ + { 0x0849, 0x0fe4}, /* Hybrid Cal enable */ + { 0x084b, 0x04b5}, /* Echo Score Sel */ + { 0x0018, 0x0043}, /* Set CRS/RX_DV pin as RX_DV for RMII repeater mode */ +}; + +static struct dp83td510_init_reg dp83td510_auto_neg[] = { + { 0x608, 0x003b }, /* disable_0_transition */ + { 0x862, 0x39f8 }, /* AGC Gain during Autoneg */ + { 0x81a, 0x67c0 }, /* deq offset for 1V swing */ + { 0x81c, 0xfb62 }, /* deq offset for 2.4V swing */ + { 0x830, 0x05a3 }, /* Enable energy lost fallback */ + { 0x855, 0x1b55 }, /* MSE Threshold change */ + { 0x831, 0x0403 }, /* energy detect threshold */ + { 0x856, 0x1800 }, /* good1 MSE threshold change */ + { 0x857, 0x8fa0 }, /* Enable fallback to phase 1 on watchdog trigger */ + { 0x871, 0x000c }, /* TED input changed to slicer_in without FFE */ + { 0x883, 0x022e }, /* Enable Rx Filter Change PGA threshold for Short Cable detection */ + { 0x402, 0x1800 }, /* Adjusr LD swing */ + { 0x878, 0x2248 }, /* Change PI up/down polarity */ + { 0x10c, 0x0008 }, /* tx filter coefficient */ + { 0x112, 0x1212 }, /* tx filter scaling factor */ + { 0x809, 0x5c80 }, /* AGC retrain */ + { 0x803, 0x1529 }, /* Master Ph1 Back-off */ + { 0x804, 0x1a33 }, /* Master Ph1 Back-off */ + { 0x805, 0x1f3d }, /* Master Ph1 Back-off */ + { 0x850, 0x045b }, /* hybrid gain & delay */ + { 0x874, 0x6967 }, /* kp step 0 for master */ + { 0x852, 0x7800 }, /* FAGC init gain */ + { 0x806, 0x1e1e }, /* Master/Slave Ph2 Back-off */ + { 0x807, 0x2525 }, /* Master/Slave Ph2 Back-off */ + { 0x808, 0x2c2c }, /* Master/Slave Ph2 Back-off */ + { 0x850, 0x0590 }, /* Hybrid Gain/Delay Code */ + { 0x827, 0x4000 }, /* Echo Fixed Delay */ + { 0x849, 0x0fe4 }, /* Hybrid Cal enable */ + { 0x84b, 0x04b5 }, /* Echo Score Sel */ + { 0x018, 0x0043 }, /* Set CRS/RX_DV pin as RX_DV for RMII repeater mode */ +}; + +static int dp83td510_ack_interrupt(struct phy_device *phydev) +{ + int ret; + + ret = phy_read(phydev, DP83TD510_INT_REG1); + if (ret < 0) + return ret; + + ret = phy_read(phydev, DP83TD510_INT_REG2); + if (ret < 0) + return ret; + + return 0; +} + +static int dp83td510_config_intr(struct phy_device *phydev) +{ + int int_status; + int gen_cfg_val; + int ret; + + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { + int_status = phy_read(phydev, DP83TD510_INT_REG1); + if (int_status < 0) + return int_status; + + int_status = (DP83TD510_INT1_ESD_EN | DP83TD510_INT1_LINK_EN | + DP83TD510_INT1_RHF_EN); + + ret = phy_write(phydev, DP83TD510_INT_REG1, int_status); + if (ret) + return ret; + + int_status = phy_read(phydev, DP83TD510_INT_REG2); + if (int_status < 0) + return int_status; + + int_status = (DP83TD510_INT2_POR | DP83TD510_INT2_POL | + DP83TD510_INT2_PAGE); + + ret = phy_write(phydev, DP83TD510_INT_REG2, int_status); + if (ret) + return ret; + + gen_cfg_val = phy_read(phydev, DP83TD510_GEN_CFG); + if (gen_cfg_val < 0) + return gen_cfg_val; + + gen_cfg_val |= DP83TD510_INT_OE | DP83TD510_INT_EN; + + } else { + ret = phy_write(phydev, DP83TD510_INT_REG1, 0); + if (ret) + return ret; + + ret = phy_write(phydev, DP83TD510_INT_REG2, 0); + if (ret) + return ret; + + gen_cfg_val = phy_read(phydev, DP83TD510_GEN_CFG); + if (gen_cfg_val < 0) + return gen_cfg_val; + + gen_cfg_val &= ~DP83TD510_INT_EN; + } + + return phy_write(phydev, DP83TD510_GEN_CFG, gen_cfg_val); +} + +static int dp83td510_configure_mode(struct phy_device *phydev) +{ + struct dp83td510_private *dp83td510 = phydev->priv; + struct dp83td510_init_reg *init_data; + int size; + int ret; + int i; + + ret = phy_set_bits(phydev, DP83TD510_MII_REG, DP83TD510_HW_RESET); + if (ret < 0) + return ret; + + switch (phydev->master_slave_set) { + case MASTER_SLAVE_CFG_MASTER_FORCE: + if (dp83td510->hi_diff_output) { + size = ARRAY_SIZE(dp83td510_master_2_4); + init_data = dp83td510_master_2_4; + } else { + size = ARRAY_SIZE(dp83td510_master_1_0); + init_data = dp83td510_master_1_0; + } + break; + case MASTER_SLAVE_CFG_SLAVE_FORCE: + if (dp83td510->hi_diff_output) { + size = ARRAY_SIZE(dp83td510_slave_2_4); + init_data = dp83td510_slave_2_4; + } else { + size = ARRAY_SIZE(dp83td510_slave_1_0); + init_data = dp83td510_slave_1_0; + } + break; + case MASTER_SLAVE_CFG_UNKNOWN: + case MASTER_SLAVE_CFG_UNSUPPORTED: + phydev_warn(phydev, "Unsupported Master/Slave mode\n"); + return -ENOTSUPP; + case MASTER_SLAVE_CFG_SLAVE_PREFERRED: + case MASTER_SLAVE_CFG_MASTER_PREFERRED: + default: + size = ARRAY_SIZE(dp83td510_auto_neg); + init_data = dp83td510_auto_neg; + break; + }; + + for (i = 0; i < size; i++) { + ret = phy_write_mmd(phydev, DP83TD510_DEVADDR, init_data[i].reg, + init_data[i].val); + if (ret) + return ret; + } + + return phy_set_bits(phydev, DP83TD510_MII_REG, DP83TD510_SW_RESET); +} + +static int dp83td510_read_status(struct phy_device *phydev) +{ + int mst_slave_cfg; + int auto_neg = 0; + int ret; + + ret = genphy_read_status_fixed(phydev); + if (ret) + return ret; + + mst_slave_cfg = phy_read_mmd(phydev, DP83TD510_PMD_DEVADDR, DP83TD510_PMD_CTRL); + mst_slave_cfg = DP83TD510_MASTER_MODE; + if (mst_slave_cfg < 0) + return mst_slave_cfg; + + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported)) + auto_neg = 1; + + if (mst_slave_cfg & DP83TD510_MASTER_MODE) { + if (auto_neg) { + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; + phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED; + } else { + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; + phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE; + } + } else { + if (auto_neg) { + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; + phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED; + } else { + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; + phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE; + } + } + + return 0; +} + +static int dp83td510_get_features(struct phy_device *phydev) +{ + linkmode_set_bit_array(dp83td510_feature_array, + ARRAY_SIZE(dp83td510_feature_array), + phydev->supported); + + return 0; +} + +static int dp83td510_config_aneg(struct phy_device *phydev) +{ + int pmd_ctrl = DP83TD510_MASTER_MODE; + int ret; + + switch (phydev->master_slave_set) { + case MASTER_SLAVE_CFG_MASTER_PREFERRED: + case MASTER_SLAVE_CFG_MASTER_FORCE: + if (phydev->autoneg) + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); + else + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); + + pmd_ctrl = DP83TD510_MASTER_MODE; + break; + case MASTER_SLAVE_CFG_SLAVE_PREFERRED: + case MASTER_SLAVE_CFG_SLAVE_FORCE: + if (phydev->autoneg) + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); + else + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); + + pmd_ctrl = 0; + break; + case MASTER_SLAVE_CFG_UNKNOWN: + case MASTER_SLAVE_CFG_UNSUPPORTED: + default: + phydev_warn(phydev, "Unsupported Master/Slave mode\n"); + return -ENOTSUPP; + } + + if (phydev->autoneg) { + ret = phy_modify_mmd(phydev, DP83TD510_DEVADDR_AN, + DP83TD510_ANEG_CTRL, + DP83TD510_AUTO_NEG_EN, + DP83TD510_AUTO_NEG_EN); + if (ret) + return ret; + } else { + ret = phy_modify_mmd(phydev, DP83TD510_DEVADDR_AN, + DP83TD510_ANEG_CTRL, + DP83TD510_AUTO_NEG_EN, 0); + if (ret) + return ret; + + ret = phy_modify_mmd(phydev, DP83TD510_PMD_DEVADDR, + DP83TD510_PMD_CTRL, + DP83TD510_MASTER_MODE, pmd_ctrl); + if (ret) + return ret; + } + + return dp83td510_configure_mode(phydev); +} + +static int dp83td510_config_init(struct phy_device *phydev) +{ + struct dp83td510_private *dp83td510 = phydev->priv; + int mst_slave_cfg; + int ret = 0; + + if (phy_interface_is_rgmii(phydev)) { + if (dp83td510->rgmii_delay) { + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); + if (ret) + return ret; + } + } + + if (phydev->interface == PHY_INTERFACE_MODE_RMII) { + ret = phy_modify(phydev, DP83TD510_GEN_CFG, + DP83TD510_FIFO_DEPTH_MASK, + dp83td510->tx_fifo_depth); + if (ret) + return ret; + } + + mst_slave_cfg = phy_read_mmd(phydev, DP83TD510_PMD_DEVADDR, DP83TD510_PMD_CTRL); + mst_slave_cfg = DP83TD510_MASTER_MODE; + if (mst_slave_cfg < 0) + return mst_slave_cfg; + + if (mst_slave_cfg & DP83TD510_MASTER_MODE) { + if(phydev->autoneg) { + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; + phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_PREFERRED; + } else { + phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; + phydev->master_slave_set = MASTER_SLAVE_CFG_MASTER_FORCE; + } + } else { + if(phydev->autoneg) { + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; + phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_PREFERRED; + } else { + phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; + phydev->master_slave_set = MASTER_SLAVE_CFG_SLAVE_FORCE; + } + } + + return 0; +} + +static int dp83td510_phy_reset(struct phy_device *phydev) +{ + int ret; + + ret = phy_set_bits(phydev, DP83TD510_MII_REG, DP83TD510_SW_RESET); + if (ret < 0) + return ret; + + usleep_range(10, 20); + + return dp83td510_config_init(phydev); +} + +static int dp83td510_read_straps(struct phy_device *phydev) +{ + struct dp83td510_private *dp83td510 = phydev->priv; + int strap; + + strap = phy_read_mmd(phydev, DP83TD510_DEVADDR, DP83TD510_SOR_1); + if (strap < 0) + return strap; + + if (strap & DP83TD510_RGMII) + dp83td510->is_rgmii = true; + + return 0; +}; + +#if IS_ENABLED(CONFIG_OF_MDIO) +static int dp83td510_of_init(struct phy_device *phydev) +{ + struct dp83td510_private *dp83td510 = phydev->priv; + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + s32 rx_int_delay; + s32 tx_int_delay; + int ret; + + if (!of_node) + return -ENODEV; + + ret = dp83td510_read_straps(phydev); + if (ret) + return ret; + + dp83td510->hi_diff_output = device_property_read_bool(&phydev->mdio.dev, + "tx-rx-output-high"); + + if (device_property_read_u32(&phydev->mdio.dev, "tx-fifo-depth", + &dp83td510->tx_fifo_depth)) + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB; + + switch (dp83td510->tx_fifo_depth) { + case 4: + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_4_B_NIB; + break; + case 5: + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB; + break; + case 6: + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_6_B_NIB; + break; + case 8: + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_8_B_NIB; + break; + default: + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB; + } + + rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, true); + if (rx_int_delay <= 0) + dp83td510->rgmii_delay = DP83TD510_RX_CLK_SHIFT; + else + dp83td510->rgmii_delay = 0; + + tx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0, false); + if (tx_int_delay <= 0) + dp83td510->rgmii_delay |= DP83TD510_TX_CLK_SHIFT; + else + dp83td510->rgmii_delay &= ~DP83TD510_TX_CLK_SHIFT; + + return 0; +} +#else +static int dp83869_of_init(struct phy_device *phydev) +{ + return dp83td510_read_straps(phydev); +} +#endif /* CONFIG_OF_MDIO */ + +static int dp83td510_probe(struct phy_device *phydev) +{ + struct dp83td510_private *dp83td510; + int ret; + + dp83td510 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83td510), GFP_KERNEL); + if (!dp83td510) + return -ENOMEM; + + phydev->priv = dp83td510; + + ret = dp83td510_of_init(phydev); + if (ret) + return ret; + + return dp83td510_config_init(phydev); +} + +static struct phy_driver dp83td510_driver[] = { + { + PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID), + .name = "TI DP83TD510E", + .probe = dp83td510_probe, + .config_init = dp83td510_config_init, + .soft_reset = dp83td510_phy_reset, + + /* IRQ related */ + .ack_interrupt = dp83td510_ack_interrupt, + .config_intr = dp83td510_config_intr, + .config_aneg = dp83td510_config_aneg, + .read_status = dp83td510_read_status, + + .get_features = dp83td510_get_features, + + .suspend = genphy_suspend, + .resume = genphy_resume, + }, +}; +module_phy_driver(dp83td510_driver); + +static struct mdio_device_id __maybe_unused dp83td510_tbl[] = { + { PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID) }, + { } +}; +MODULE_DEVICE_TABLE(mdio, dp83td510_tbl); + +MODULE_DESCRIPTION("Texas Instruments DP83TD510E PHY driver"); +MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com"); +MODULE_LICENSE("GPL v2"); + -- 2.28.0.585.ge1cfff676549 ^ permalink raw reply related [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy @ 2020-10-30 20:15 ` Andrew Lunn 2020-11-03 17:07 ` Dan Murphy 2020-10-30 23:03 ` Jakub Kicinski 2020-10-31 9:18 ` Ioana Ciornei 2 siblings, 1 reply; 24+ messages in thread From: Andrew Lunn @ 2020-10-30 20:15 UTC (permalink / raw) To: Dan Murphy Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel > +static int dp83td510_config_init(struct phy_device *phydev) > +{ > + struct dp83td510_private *dp83td510 = phydev->priv; > + int mst_slave_cfg; > + int ret = 0; > + > + if (phy_interface_is_rgmii(phydev)) { > + if (dp83td510->rgmii_delay) { > + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, > + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); > + if (ret) > + return ret; > + } > + } Hi Dan I'm getting a bit paranoid about RGMII delays... > +static int dp83td510_read_straps(struct phy_device *phydev) > +{ > + struct dp83td510_private *dp83td510 = phydev->priv; > + int strap; > + > + strap = phy_read_mmd(phydev, DP83TD510_DEVADDR, DP83TD510_SOR_1); > + if (strap < 0) > + return strap; > + > + if (strap & DP83TD510_RGMII) > + dp83td510->is_rgmii = true; > + > + return 0; > +}; So dp83td510->is_rgmii is the strapping configuration. So if one of the four RGMII modes is selected, your appear to ignore which of the four is selected, and program the hardware with the strapping? That seems like a bad idea. > +#if IS_ENABLED(CONFIG_OF_MDIO) > +static int dp83td510_of_init(struct phy_device *phydev) > +{ > + struct dp83td510_private *dp83td510 = phydev->priv; > + struct device *dev = &phydev->mdio.dev; > + struct device_node *of_node = dev->of_node; > + s32 rx_int_delay; > + s32 tx_int_delay; > + int ret; > + > + if (!of_node) > + return -ENODEV; > + > + ret = dp83td510_read_straps(phydev); > + if (ret) > + return ret; > + > + dp83td510->hi_diff_output = device_property_read_bool(&phydev->mdio.dev, > + "tx-rx-output-high"); > + > + if (device_property_read_u32(&phydev->mdio.dev, "tx-fifo-depth", > + &dp83td510->tx_fifo_depth)) > + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB; Please don't use device_property_read_foo API, we don't want to give the impression it is O.K. to stuff DT properties in ACPI tables. Please use of_ API calls. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 20:15 ` Andrew Lunn @ 2020-11-03 17:07 ` Dan Murphy 2020-11-03 17:18 ` Andrew Lunn 0 siblings, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-11-03 17:07 UTC (permalink / raw) To: Andrew Lunn Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel Andrew On 10/30/20 3:15 PM, Andrew Lunn wrote: >> +static int dp83td510_config_init(struct phy_device *phydev) >> +{ >> + struct dp83td510_private *dp83td510 = phydev->priv; >> + int mst_slave_cfg; >> + int ret = 0; >> + >> + if (phy_interface_is_rgmii(phydev)) { >> + if (dp83td510->rgmii_delay) { >> + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, >> + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); >> + if (ret) >> + return ret; >> + } >> + } > Hi Dan > > I'm getting a bit paranoid about RGMII delays... Not sure what this means. > >> +static int dp83td510_read_straps(struct phy_device *phydev) >> +{ >> + struct dp83td510_private *dp83td510 = phydev->priv; >> + int strap; >> + >> + strap = phy_read_mmd(phydev, DP83TD510_DEVADDR, DP83TD510_SOR_1); >> + if (strap < 0) >> + return strap; >> + >> + if (strap & DP83TD510_RGMII) >> + dp83td510->is_rgmii = true; >> + >> + return 0; >> +}; > So dp83td510->is_rgmii is the strapping configuration. So if one of > the four RGMII modes is selected, your appear to ignore which of the > four is selected, and program the hardware with the strapping? > > That seems like a bad idea. I will re-look at this code. > >> +#if IS_ENABLED(CONFIG_OF_MDIO) >> +static int dp83td510_of_init(struct phy_device *phydev) >> +{ >> + struct dp83td510_private *dp83td510 = phydev->priv; >> + struct device *dev = &phydev->mdio.dev; >> + struct device_node *of_node = dev->of_node; >> + s32 rx_int_delay; >> + s32 tx_int_delay; >> + int ret; >> + >> + if (!of_node) >> + return -ENODEV; >> + >> + ret = dp83td510_read_straps(phydev); >> + if (ret) >> + return ret; >> + >> + dp83td510->hi_diff_output = device_property_read_bool(&phydev->mdio.dev, >> + "tx-rx-output-high"); >> + >> + if (device_property_read_u32(&phydev->mdio.dev, "tx-fifo-depth", >> + &dp83td510->tx_fifo_depth)) >> + dp83td510->tx_fifo_depth = DP83TD510_FIFO_DEPTH_5_B_NIB; > Please don't use device_property_read_foo API, we don't want to give > the impression it is O.K. to stuff DT properties in ACPI > tables. Please use of_ API calls. Hmm. Is this a new stance in DT handling for the networking tree? If it is should I go back and rework some of my other drivers that use device_property APIs Dan ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:07 ` Dan Murphy @ 2020-11-03 17:18 ` Andrew Lunn 2020-11-03 17:35 ` Dan Murphy 0 siblings, 1 reply; 24+ messages in thread From: Andrew Lunn @ 2020-11-03 17:18 UTC (permalink / raw) To: Dan Murphy Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Tue, Nov 03, 2020 at 11:07:00AM -0600, Dan Murphy wrote: > Andrew > > On 10/30/20 3:15 PM, Andrew Lunn wrote: > > > +static int dp83td510_config_init(struct phy_device *phydev) > > > +{ > > > + struct dp83td510_private *dp83td510 = phydev->priv; > > > + int mst_slave_cfg; > > > + int ret = 0; > > > + > > > + if (phy_interface_is_rgmii(phydev)) { > > > + if (dp83td510->rgmii_delay) { > > > + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, > > > + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); > > > + if (ret) > > > + return ret; > > > + } > > > + } > > Hi Dan > > > > I'm getting a bit paranoid about RGMII delays... > Not sure what this means. See the discussion and breakage around the realtek PHY. It wrongly implemented RGMII delays. When it was fixed, lots of board broke because the bug in the PHY driver hid bugs in the DT. > > Please don't use device_property_read_foo API, we don't want to give > > the impression it is O.K. to stuff DT properties in ACPI > > tables. Please use of_ API calls. > > Hmm. Is this a new stance in DT handling for the networking tree? > > If it is should I go back and rework some of my other drivers that use > device_property APIs There is a slowly growing understanding what ACPI support in this area means. It seems to mean that the firmware should actually do all the setup, and the kernel should not touch the hardware configuration. But some developers are ignoring this, and just stuffing DT properties into ACPI tables and letting the kernel configure the hardware, if it happens to use the device_property_read API. So i want to make it clear that these properties are for device tree, and if you want to use ACPI, you should do things the ACPI way. For new code, i will be pushing for OF only calls. Older code is a bit more tricky. There might be boards out there using ACPI, but doing it wrongly, and stuffing OF properties into ACPI tables. We should try to avoid breaking them. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:18 ` Andrew Lunn @ 2020-11-03 17:35 ` Dan Murphy 2020-11-05 3:03 ` Florian Fainelli 0 siblings, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-11-03 17:35 UTC (permalink / raw) To: Andrew Lunn Cc: davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel Andrew On 11/3/20 11:18 AM, Andrew Lunn wrote: > On Tue, Nov 03, 2020 at 11:07:00AM -0600, Dan Murphy wrote: >> Andrew >> >> On 10/30/20 3:15 PM, Andrew Lunn wrote: >>>> +static int dp83td510_config_init(struct phy_device *phydev) >>>> +{ >>>> + struct dp83td510_private *dp83td510 = phydev->priv; >>>> + int mst_slave_cfg; >>>> + int ret = 0; >>>> + >>>> + if (phy_interface_is_rgmii(phydev)) { >>>> + if (dp83td510->rgmii_delay) { >>>> + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, >>>> + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); >>>> + if (ret) >>>> + return ret; >>>> + } >>>> + } >>> Hi Dan >>> >>> I'm getting a bit paranoid about RGMII delays... >> Not sure what this means. > See the discussion and breakage around the realtek PHY. It wrongly > implemented RGMII delays. When it was fixed, lots of board broke > because the bug in the PHY driver hid bugs in the DT. > I will have to go find that thread. Do you have a link? >>> Please don't use device_property_read_foo API, we don't want to give >>> the impression it is O.K. to stuff DT properties in ACPI >>> tables. Please use of_ API calls. >> Hmm. Is this a new stance in DT handling for the networking tree? >> >> If it is should I go back and rework some of my other drivers that use >> device_property APIs > There is a slowly growing understanding what ACPI support in this area > means. It seems to mean that the firmware should actually do all the > setup, and the kernel should not touch the hardware configuration. But > some developers are ignoring this, and just stuffing DT properties > into ACPI tables and letting the kernel configure the hardware, if it > happens to use the device_property_read API. So i want to make it > clear that these properties are for device tree, and if you want to > use ACPI, you should do things the ACPI way. > > For new code, i will be pushing for OF only calls. Older code is a bit > more tricky. There might be boards out there using ACPI, but doing it > wrongly, and stuffing OF properties into ACPI tables. We should try to > avoid breaking them. Got it. I will move back to of_* calls Dan > Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:35 ` Dan Murphy @ 2020-11-05 3:03 ` Florian Fainelli 0 siblings, 0 replies; 24+ messages in thread From: Florian Fainelli @ 2020-11-05 3:03 UTC (permalink / raw) To: Dan Murphy, Andrew Lunn Cc: davem, hkallweit1, robh, devicetree, netdev, linux-kernel On 11/3/2020 9:35 AM, Dan Murphy wrote: > Andrew > > On 11/3/20 11:18 AM, Andrew Lunn wrote: >> On Tue, Nov 03, 2020 at 11:07:00AM -0600, Dan Murphy wrote: >>> Andrew >>> >>> On 10/30/20 3:15 PM, Andrew Lunn wrote: >>>>> +static int dp83td510_config_init(struct phy_device *phydev) >>>>> +{ >>>>> + struct dp83td510_private *dp83td510 = phydev->priv; >>>>> + int mst_slave_cfg; >>>>> + int ret = 0; >>>>> + >>>>> + if (phy_interface_is_rgmii(phydev)) { >>>>> + if (dp83td510->rgmii_delay) { >>>>> + ret = phy_set_bits_mmd(phydev, DP83TD510_DEVADDR, >>>>> + DP83TD510_MAC_CFG_1, >>>>> dp83td510->rgmii_delay); >>>>> + if (ret) >>>>> + return ret; >>>>> + } >>>>> + } >>>> Hi Dan >>>> >>>> I'm getting a bit paranoid about RGMII delays... >>> Not sure what this means. >> See the discussion and breakage around the realtek PHY. It wrongly >> implemented RGMII delays. When it was fixed, lots of board broke >> because the bug in the PHY driver hid bugs in the DT. >> > I will have to go find that thread. Do you have a link? That would be the thread: https://lore.kernel.org/netdev/CAMj1kXEEF_Un-4NTaD5iUN0NoZYaJQn-rPediX0S6oRiuVuW-A@mail.gmail.com/ -- Florian ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy 2020-10-30 20:15 ` Andrew Lunn @ 2020-10-30 23:03 ` Jakub Kicinski 2020-11-03 17:09 ` Dan Murphy 2020-10-31 9:18 ` Ioana Ciornei 2 siblings, 1 reply; 24+ messages in thread From: Jakub Kicinski @ 2020-10-30 23:03 UTC (permalink / raw) To: Dan Murphy Cc: davem, andrew, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote: > The DP83TD510E is an ultra-low power Ethernet physical layer transceiver > that supports 10M single pair cable. > > The device supports both 2.4-V p2p and 1-V p2p output voltage as defined > by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via > the device tree or the device is defaulted to auto negotiation to > determine the proper p2p voltage. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array' was not declared. Should it be static? Also this: WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP #429: FILE: drivers/net/phy/dp83td510.c:371: + return -ENOTSUPP; WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP #524: FILE: drivers/net/phy/dp83td510.c:466: + return -ENOTSUPP; ERROR: space required before the open parenthesis '(' #580: FILE: drivers/net/phy/dp83td510.c:522: + if(phydev->autoneg) { ERROR: space required before the open parenthesis '(' #588: FILE: drivers/net/phy/dp83td510.c:530: + if(phydev->autoneg) { And please try to wrap the code on 80 chars on the non trivial lines: WARNING: line length of 88 exceeds 80 columns #458: FILE: drivers/net/phy/dp83td510.c:400: + mst_slave_cfg = phy_read_mmd(phydev, DP83TD510_PMD_DEVADDR, DP83TD510_PMD_CTRL); WARNING: line length of 91 exceeds 80 columns #505: FILE: drivers/net/phy/dp83td510.c:447: + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); WARNING: line length of 93 exceeds 80 columns #507: FILE: drivers/net/phy/dp83td510.c:449: + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); WARNING: line length of 91 exceeds 80 columns #514: FILE: drivers/net/phy/dp83td510.c:456: + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); WARNING: line length of 93 exceeds 80 columns #516: FILE: drivers/net/phy/dp83td510.c:458: + linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); WARNING: line length of 92 exceeds 80 columns #560: FILE: drivers/net/phy/dp83td510.c:502: + DP83TD510_MAC_CFG_1, dp83td510->rgmii_delay); WARNING: line length of 88 exceeds 80 columns #574: FILE: drivers/net/phy/dp83td510.c:516: + mst_slave_cfg = phy_read_mmd(phydev, DP83TD510_PMD_DEVADDR, DP83TD510_PMD_CTRL); WARNING: line length of 84 exceeds 80 columns #695: FILE: drivers/net/phy/dp83td510.c:637: + dp83td510 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83td510), GFP_KERNEL); ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 23:03 ` Jakub Kicinski @ 2020-11-03 17:09 ` Dan Murphy 2020-11-03 17:21 ` Andrew Lunn 0 siblings, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-11-03 17:09 UTC (permalink / raw) To: Jakub Kicinski Cc: davem, andrew, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel Hello On 10/30/20 6:03 PM, Jakub Kicinski wrote: > On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote: >> The DP83TD510E is an ultra-low power Ethernet physical layer transceiver >> that supports 10M single pair cable. >> >> The device supports both 2.4-V p2p and 1-V p2p output voltage as defined >> by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via >> the device tree or the device is defaulted to auto negotiation to >> determine the proper p2p voltage. >> >> Signed-off-by: Dan Murphy <dmurphy@ti.com> > drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array' was not declared. Should it be static? I did not see this warning. Did you use W=1? > > > Also this: > > WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP > #429: FILE: drivers/net/phy/dp83td510.c:371: > + return -ENOTSUPP; > > WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP > #524: FILE: drivers/net/phy/dp83td510.c:466: > + return -ENOTSUPP; Same with these warnings how where they reproduced? > > ERROR: space required before the open parenthesis '(' > #580: FILE: drivers/net/phy/dp83td510.c:522: > + if(phydev->autoneg) { > > ERROR: space required before the open parenthesis '(' > #588: FILE: drivers/net/phy/dp83td510.c:530: > + if(phydev->autoneg) { > > > And please try to wrap the code on 80 chars on the non trivial lines: What is the LoC limit for networking just for my clarification and I will align with that. I know some maintainers like to keep the 80 LoC and some allow a longer line. Dan ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:09 ` Dan Murphy @ 2020-11-03 17:21 ` Andrew Lunn 2020-11-03 17:23 ` Dan Murphy 0 siblings, 1 reply; 24+ messages in thread From: Andrew Lunn @ 2020-11-03 17:21 UTC (permalink / raw) To: Dan Murphy Cc: Jakub Kicinski, davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Tue, Nov 03, 2020 at 11:09:44AM -0600, Dan Murphy wrote: > Hello > > On 10/30/20 6:03 PM, Jakub Kicinski wrote: > > On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote: > > > The DP83TD510E is an ultra-low power Ethernet physical layer transceiver > > > that supports 10M single pair cable. > > > > > > The device supports both 2.4-V p2p and 1-V p2p output voltage as defined > > > by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via > > > the device tree or the device is defaulted to auto negotiation to > > > determine the proper p2p voltage. > > > > > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > > drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array' was not declared. Should it be static? > I did not see this warning. Did you use W=1? I _think_ that one is W=1. All the PHY drivers are W=1 clean, and i want to keep it that way. And i hope to make it the default in a lot of the network code soon. > > Also this: > > > > WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP > > #429: FILE: drivers/net/phy/dp83td510.c:371: > > + return -ENOTSUPP; > > > > WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP > > #524: FILE: drivers/net/phy/dp83td510.c:466: > > + return -ENOTSUPP; > Same with these warnings how where they reproduced? > > > > ERROR: space required before the open parenthesis '(' > > #580: FILE: drivers/net/phy/dp83td510.c:522: > > + if(phydev->autoneg) { > > > > ERROR: space required before the open parenthesis '(' > > #588: FILE: drivers/net/phy/dp83td510.c:530: > > + if(phydev->autoneg) { > > These look like checkpatch. > > > > And please try to wrap the code on 80 chars on the non trivial lines: > > What is the LoC limit for networking just for my clarification and I will > align with that. 80. I would not be too surprised to see checkpatch getting a patch to set it to 80 for networking code. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:21 ` Andrew Lunn @ 2020-11-03 17:23 ` Dan Murphy 2020-11-03 17:38 ` Andrew Lunn 0 siblings, 1 reply; 24+ messages in thread From: Dan Murphy @ 2020-11-03 17:23 UTC (permalink / raw) To: Andrew Lunn Cc: Jakub Kicinski, davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel Andrew On 11/3/20 11:21 AM, Andrew Lunn wrote: > On Tue, Nov 03, 2020 at 11:09:44AM -0600, Dan Murphy wrote: >> Hello >> >> On 10/30/20 6:03 PM, Jakub Kicinski wrote: >>> On Fri, 30 Oct 2020 12:29:50 -0500 Dan Murphy wrote: >>>> The DP83TD510E is an ultra-low power Ethernet physical layer transceiver >>>> that supports 10M single pair cable. >>>> >>>> The device supports both 2.4-V p2p and 1-V p2p output voltage as defined >>>> by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via >>>> the device tree or the device is defaulted to auto negotiation to >>>> determine the proper p2p voltage. >>>> >>>> Signed-off-by: Dan Murphy <dmurphy@ti.com> >>> drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array' was not declared. Should it be static? >> I did not see this warning. Did you use W=1? > I _think_ that one is W=1. All the PHY drivers are W=1 clean, and i > want to keep it that way. And i hope to make it the default in a lot > of the network code soon. OK I built with the W=1 before submission I did not see this but I will try some other things. >>> Also this: >>> >>> WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP >>> #429: FILE: drivers/net/phy/dp83td510.c:371: >>> + return -ENOTSUPP; >>> >>> WARNING: ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP >>> #524: FILE: drivers/net/phy/dp83td510.c:466: >>> + return -ENOTSUPP; >> Same with these warnings how where they reproduced? Same as above >>> ERROR: space required before the open parenthesis '(' >>> #580: FILE: drivers/net/phy/dp83td510.c:522: >>> + if(phydev->autoneg) { >>> >>> ERROR: space required before the open parenthesis '(' >>> #588: FILE: drivers/net/phy/dp83td510.c:530: >>> + if(phydev->autoneg) { >>> > These look like checkpatch. These I missed >>> And please try to wrap the code on 80 chars on the non trivial lines: >> What is the LoC limit for networking just for my clarification and I will >> align with that. > 80. I would not be too surprised to see checkpatch getting a patch to > set it to 80 for networking code. OK I will align the lines to 80 then. Dan > Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-11-03 17:23 ` Dan Murphy @ 2020-11-03 17:38 ` Andrew Lunn 0 siblings, 0 replies; 24+ messages in thread From: Andrew Lunn @ 2020-11-03 17:38 UTC (permalink / raw) To: Dan Murphy Cc: Jakub Kicinski, davem, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel > > > > drivers/net/phy/dp83td510.c:70:11: warning: symbol 'dp83td510_feature_array' was not declared. Should it be static? > > > I did not see this warning. Did you use W=1? > > I _think_ that one is W=1. All the PHY drivers are W=1 clean, and i > > want to keep it that way. And i hope to make it the default in a lot > > of the network code soon. > OK I built with the W=1 before submission I did not see this but I will try > some other things. Then it might be sparse. Try C=1. Andrew ^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the DP83TD510 Ethernet PHY 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy 2020-10-30 20:15 ` Andrew Lunn 2020-10-30 23:03 ` Jakub Kicinski @ 2020-10-31 9:18 ` Ioana Ciornei 2 siblings, 0 replies; 24+ messages in thread From: Ioana Ciornei @ 2020-10-31 9:18 UTC (permalink / raw) To: Dan Murphy Cc: davem, andrew, f.fainelli, hkallweit1, robh, devicetree, netdev, linux-kernel On Fri, Oct 30, 2020 at 12:29:50PM -0500, Dan Murphy wrote: > The DP83TD510E is an ultra-low power Ethernet physical layer transceiver > that supports 10M single pair cable. > > The device supports both 2.4-V p2p and 1-V p2p output voltage as defined > by IEEE 802.3cg 10Base-T1L specfications. These modes can be forced via > the device tree or the device is defaulted to auto negotiation to > determine the proper p2p voltage. > > Signed-off-by: Dan Murphy <dmurphy@ti.com> > --- > drivers/net/phy/Kconfig | 6 + > drivers/net/phy/Makefile | 1 + > drivers/net/phy/dp83td510.c | 681 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 688 insertions(+) > create mode 100644 drivers/net/phy/dp83td510.c > (...) > +static int dp83td510_ack_interrupt(struct phy_device *phydev) > +{ > + int ret; > + > + ret = phy_read(phydev, DP83TD510_INT_REG1); > + if (ret < 0) > + return ret; > + > + ret = phy_read(phydev, DP83TD510_INT_REG2); > + if (ret < 0) > + return ret; > + > + return 0; > +} > + > +static int dp83td510_config_intr(struct phy_device *phydev) > +{ > + int int_status; > + int gen_cfg_val; > + int ret; > + > + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { > + int_status = phy_read(phydev, DP83TD510_INT_REG1); > + if (int_status < 0) > + return int_status; > + > + int_status = (DP83TD510_INT1_ESD_EN | DP83TD510_INT1_LINK_EN | > + DP83TD510_INT1_RHF_EN); > + > + ret = phy_write(phydev, DP83TD510_INT_REG1, int_status); > + if (ret) > + return ret; > + > + int_status = phy_read(phydev, DP83TD510_INT_REG2); > + if (int_status < 0) > + return int_status; > + > + int_status = (DP83TD510_INT2_POR | DP83TD510_INT2_POL | > + DP83TD510_INT2_PAGE); > + > + ret = phy_write(phydev, DP83TD510_INT_REG2, int_status); > + if (ret) > + return ret; > + > + gen_cfg_val = phy_read(phydev, DP83TD510_GEN_CFG); > + if (gen_cfg_val < 0) > + return gen_cfg_val; > + > + gen_cfg_val |= DP83TD510_INT_OE | DP83TD510_INT_EN; > + > + } else { > + ret = phy_write(phydev, DP83TD510_INT_REG1, 0); > + if (ret) > + return ret; > + > + ret = phy_write(phydev, DP83TD510_INT_REG2, 0); > + if (ret) > + return ret; > + > + gen_cfg_val = phy_read(phydev, DP83TD510_GEN_CFG); > + if (gen_cfg_val < 0) > + return gen_cfg_val; > + > + gen_cfg_val &= ~DP83TD510_INT_EN; > + } > + > + return phy_write(phydev, DP83TD510_GEN_CFG, gen_cfg_val); > +} > + I am not really sure if the shared-IRQ work in the below linked patch set will go through, but I think it would be cleaner just to ack any pending interrupts after you disable them. https://lore.kernel.org/netdev/20201029100741.462818-1-ciorneiioana@gmail.com/ I see that you are reading the INT_REG1 and INT_REG2 registers (basically servicing any pending interrupts) before enabling the IRQ. The same reads should be done after the IRQ has been disabled. > +static struct phy_driver dp83td510_driver[] = { > + { > + PHY_ID_MATCH_MODEL(DP83TD510E_PHY_ID), > + .name = "TI DP83TD510E", > + .probe = dp83td510_probe, > + .config_init = dp83td510_config_init, > + .soft_reset = dp83td510_phy_reset, > + > + /* IRQ related */ > + .ack_interrupt = dp83td510_ack_interrupt, > + .config_intr = dp83td510_config_intr, I think the PHY maintainers could comment on this more, but maybe it would help if the driver implements the .handle_interrupt() callback just so that I wouldn't have to touch a driver that was just added to rework it for the shared-IRQ transition. Ioana ^ permalink raw reply [flat|nested] 24+ messages in thread
end of thread, other threads:[~2020-11-05 3:03 UTC | newest] Thread overview: 24+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2020-10-30 17:29 [PATCH net-next v3 0/4] DP83TD510 Single Pair 10Mbps Ethernet PHY Dan Murphy 2020-10-30 17:29 ` [PATCH net-next v3 1/4] ethtool: Add 10base-T1L link mode entries Dan Murphy 2020-10-30 19:43 ` Andrew Lunn 2020-11-05 2:42 ` Florian Fainelli 2020-10-30 17:29 ` [PATCH net-next v3 2/4] dt-bindings: net: Add Rx/Tx output configuration for 10base T1L Dan Murphy 2020-10-30 19:56 ` Andrew Lunn 2020-11-03 16:52 ` Dan Murphy 2020-11-03 17:07 ` Andrew Lunn 2020-11-04 22:08 ` Rob Herring 2020-10-30 17:29 ` [PATCH net-next v3 3/4] dt-bindings: dp83td510: Add binding for DP83TD510 Ethernet PHY Dan Murphy 2020-10-31 9:27 ` Ioana Ciornei 2020-11-02 17:12 ` Rob Herring 2020-10-30 17:29 ` [PATCH net-next v3 4/4] net: phy: dp83td510: Add support for the " Dan Murphy 2020-10-30 20:15 ` Andrew Lunn 2020-11-03 17:07 ` Dan Murphy 2020-11-03 17:18 ` Andrew Lunn 2020-11-03 17:35 ` Dan Murphy 2020-11-05 3:03 ` Florian Fainelli 2020-10-30 23:03 ` Jakub Kicinski 2020-11-03 17:09 ` Dan Murphy 2020-11-03 17:21 ` Andrew Lunn 2020-11-03 17:23 ` Dan Murphy 2020-11-03 17:38 ` Andrew Lunn 2020-10-31 9:18 ` Ioana Ciornei
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