From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: mturquette@baylibre.com
Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de,
john@phrozen.org, gregkh@linuxfoundation.org,
gch981213@gmail.com, hackpascal@gmail.com,
jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, devel@driverdev.osuosl.org,
neil@brown.name
Subject: [PATCH v3 2/5] dt: bindings: add mt7621-clk device tree binding documentation
Date: Fri, 13 Nov 2020 16:46:29 +0100 [thread overview]
Message-ID: <20201113154632.24973-3-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20201113154632.24973-1-sergio.paracuellos@gmail.com>
Adds device tree binding documentation for clocks in the
MT7621 SOC.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
.../bindings/clock/mediatek,mt7621-clk.yaml | 61 +++++++++++++++++++
1 file changed, 61 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
new file mode 100644
index 000000000000..363bd9880e29
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt7621-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MT7621 Clock Device Tree Bindings
+
+maintainers:
+ - Sergio Paracuellos <sergio.paracuellos@gmail.com>
+
+description: |
+ The MT7621 has a PLL controller from where the cpu clock is provided
+ as well as derived clocks for the bus and the peripherals. It also
+ can gate SoC device clocks.
+
+ Each clock is assigned an identifier and client nodes use this identifier
+ to specify the clock which they consume.
+
+ All these identifiers could be found in:
+ [1]: <include/dt-bindings/clock/mt7621-clk.h>.
+
+properties:
+ compatible:
+ const: mediatek,mt7621-clk
+
+ ralink,sysctl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the syscon which is in the same address area with syscon
+ device.
+
+ "#clock-cells":
+ description:
+ The first cell indicates the clock gate number, see [1] for available
+ clocks.
+ const: 1
+
+ clock-output-names:
+ maxItems: 8
+
+required:
+ - compatible
+ - ralink,sysctl
+ - '#clock-cells'
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt7621-clk.h>
+
+ pll {
+ compatible = "mediatek,mt7621-clk";
+ ralink,sysctl = <&sysc>;
+ #clock-cells = <1>;
+ clock-output-names = "xtal", "cpu", "bus",
+ "50m", "125m", "150m",
+ "250m", "270m";
+ };
--
2.25.1
next prev parent reply other threads:[~2020-11-13 15:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-13 15:46 [PATCH v3 0/5] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 1/5] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2020-11-21 13:30 ` Rob Herring
2020-11-13 15:46 ` Sergio Paracuellos [this message]
2020-11-21 13:34 ` [PATCH v3 2/5] dt: bindings: add mt7621-clk device tree binding documentation Rob Herring
2020-11-21 14:50 ` Sergio Paracuellos
2020-11-21 16:22 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2020-11-19 9:32 ` Chuanhong Guo
2020-11-19 9:35 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 4/5] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 5/5] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
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