From: Chuanhong Guo <gch981213@gmail.com>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
John Crispin <john@phrozen.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Weijie Gao <hackpascal@gmail.com>,
jiaxun.yang@flygoat.com,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
open list <linux-kernel@vger.kernel.org>,
"open list:MIPS" <linux-mips@vger.kernel.org>,
"open list:STAGING SUBSYSTEM" <devel@driverdev.osuosl.org>,
NeilBrown <neil@brown.name>
Subject: Re: [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC
Date: Thu, 19 Nov 2020 17:32:16 +0800 [thread overview]
Message-ID: <CAJsYDVL1ZYc=OaCS7_NNu27aUKmpHp63nPuVq1V8xp8s6Vguxw@mail.gmail.com> (raw)
In-Reply-To: <20201113154632.24973-4-sergio.paracuellos@gmail.com>
Hi!
On Fri, Nov 13, 2020 at 11:46 PM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
> [...]
> diff --git a/drivers/clk/ralink/Makefile b/drivers/clk/ralink/Makefile
> new file mode 100644
> index 000000000000..cf6f9216379d
> --- /dev/null
> +++ b/drivers/clk/ralink/Makefile
Why ralink? The clock design of mt7621 doesn't seem
to be part of ralink legacy stuff, and ralink is already
acquired by mediatek anyway.
I think it should be put in drivers/clk/mediatek instead.
--
Regards,
Chuanhong Guo
next prev parent reply other threads:[~2020-11-19 9:32 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-13 15:46 [PATCH v3 0/5] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 1/5] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2020-11-21 13:30 ` Rob Herring
2020-11-13 15:46 ` [PATCH v3 2/5] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2020-11-21 13:34 ` Rob Herring
2020-11-21 14:50 ` Sergio Paracuellos
2020-11-21 16:22 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2020-11-19 9:32 ` Chuanhong Guo [this message]
2020-11-19 9:35 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 4/5] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 5/5] MAINTAINERS: add MT7621 CLOCK maintainer Sergio Paracuellos
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