From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: mturquette@baylibre.com
Cc: sboyd@kernel.org, robh+dt@kernel.org, tsbogend@alpha.franken.de,
john@phrozen.org, gregkh@linuxfoundation.org,
gch981213@gmail.com, hackpascal@gmail.com,
jiaxun.yang@flygoat.com, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-mips@vger.kernel.org, devel@driverdev.osuosl.org,
neil@brown.name
Subject: [PATCH v3 5/5] MAINTAINERS: add MT7621 CLOCK maintainer
Date: Fri, 13 Nov 2020 16:46:32 +0100 [thread overview]
Message-ID: <20201113154632.24973-6-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20201113154632.24973-1-sergio.paracuellos@gmail.com>
Adding myself as maintainer for mt7621 clock driver.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
MAINTAINERS | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index f1f088a29bc2..30822ad6837c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11142,6 +11142,12 @@ L: linux-wireless@vger.kernel.org
S: Maintained
F: drivers/net/wireless/mediatek/mt7601u/
+MEDIATEK MT7621 CLOCK DRIVER
+M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/mediatek,mt7621-clk.yaml
+F: drivers/clk/ralink/clk-mt7621.c
+
MEDIATEK MT7621/28/88 I2C DRIVER
M: Stefan Roese <sr@denx.de>
L: linux-i2c@vger.kernel.org
--
2.25.1
prev parent reply other threads:[~2020-11-13 15:46 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-13 15:46 [PATCH v3 0/5] MIPS: ralink: add CPU clock detection and clock gate driver for MT7621 Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 1/5] dt-bindings: clock: add dt binding header for mt7621 clocks Sergio Paracuellos
2020-11-21 13:30 ` Rob Herring
2020-11-13 15:46 ` [PATCH v3 2/5] dt: bindings: add mt7621-clk device tree binding documentation Sergio Paracuellos
2020-11-21 13:34 ` Rob Herring
2020-11-21 14:50 ` Sergio Paracuellos
2020-11-21 16:22 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 3/5] clk: ralink: add clock driver for mt7621 SoC Sergio Paracuellos
2020-11-19 9:32 ` Chuanhong Guo
2020-11-19 9:35 ` Sergio Paracuellos
2020-11-13 15:46 ` [PATCH v3 4/5] staging: mt7621-dts: make use of new 'mt7621-clk' Sergio Paracuellos
2020-11-13 15:46 ` Sergio Paracuellos [this message]
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