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From: Thara Gopinath <thara.gopinath@linaro.org>
To: agross@kernel.org, bjorn.andersson@linaro.org,
	herbert@gondor.apana.org.au, davem@davemloft.net,
	robh+dt@kernel.org, sboyd@kernel.org, mturquette@baylibre.com
Cc: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org
Subject: [Patch v2 5/6] dts: qcom: sdm845: Add dt entries to support crypto engine.
Date: Thu, 19 Nov 2020 10:52:32 -0500	[thread overview]
Message-ID: <20201119155233.3974286-6-thara.gopinath@linaro.org> (raw)
In-Reply-To: <20201119155233.3974286-1-thara.gopinath@linaro.org>

Add crypto engine (CE) and CE BAM related nodes and definitions to
"sdm845.dtsi".

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 30 ++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 40e8c11f23ab..b5b2ea97681f 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2138,6 +2138,36 @@ ufs_mem_phy_lanes: lanes@1d87400 {
 			};
 		};
 
+		cryptobam: dma@1dc4000 {
+			compatible = "qcom,bam-v1.7.0";
+			reg = <0 0x01dc4000 0 0x24000>;
+			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&rpmhcc RPMH_CE_CLK>;
+			clock-names = "bam_clk";
+			#dma-cells = <1>;
+			qcom,ee = <0>;
+			qcom,controlled-remotely = <1>;
+			iommus = <&apps_smmu 0x704 0x1>,
+				 <&apps_smmu 0x706 0x1>,
+				 <&apps_smmu 0x714 0x1>,
+				 <&apps_smmu 0x716 0x1>;
+		};
+
+		crypto: crypto@1dfa000 {
+			compatible = "qcom,crypto-v5.4";
+			reg = <0 0x01dfa000 0 0x6000>;
+			clocks = <&gcc GCC_CE1_AHB_CLK>,
+				 <&gcc GCC_CE1_AHB_CLK>,
+				 <&rpmhcc RPMH_CE_CLK>;
+			clock-names = "iface", "bus", "core";
+			dmas = <&cryptobam 6>, <&cryptobam 7>;
+			dma-names = "rx", "tx";
+			iommus = <&apps_smmu 0x704 0x1>,
+				 <&apps_smmu 0x706 0x1>,
+				 <&apps_smmu 0x714 0x1>,
+				 <&apps_smmu 0x716 0x1>;
+		};
+
 		ipa: ipa@1e40000 {
 			compatible = "qcom,sdm845-ipa";
 
-- 
2.25.1


  parent reply	other threads:[~2020-11-19 15:52 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-19 15:52 [Patch v2 0/6] Enable Qualcomm Crypto Engine on sdm845 Thara Gopinath
2020-11-19 15:52 ` [Patch v2 1/6] dt-bindings: clock: Add entry for crypto engine RPMH clock resource Thara Gopinath
2020-11-25  2:05   ` Stephen Boyd
2020-11-19 15:52 ` [Patch v2 2/6] clk: qcom: rpmh: Add CE clock on sdm845 Thara Gopinath
2020-11-25  2:05   ` Stephen Boyd
2020-11-19 15:52 ` [Patch v2 3/6] drivers: crypto: qce: Enable support for crypto engine " Thara Gopinath
2020-11-19 15:52 ` [Patch v2 4/6] drivers: crypto: qce: Fix SHA result buffer corruption issues Thara Gopinath
2020-11-25  2:05   ` Stephen Boyd
2020-11-19 15:52 ` Thara Gopinath [this message]
2020-11-19 15:52 ` [Patch v2 6/6] dt-bindings: crypto: qcom-qce: Add v5.4 to binding Thara Gopinath
2020-12-07 22:09   ` Rob Herring
2020-12-12 15:25     ` Thara Gopinath
2020-11-19 22:44 ` [Patch v2 0/6] Enable Qualcomm Crypto Engine on sdm845 Eric Biggers
2020-11-24  2:42   ` Thara Gopinath
2020-11-27  6:25 ` Herbert Xu

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