* [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
2020-11-20 21:03 ` Rob Herring
2020-11-20 16:41 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
Controller to YAML format
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../mscc,ocelot-icpu-intr.txt | 21 -------
.../mscc,ocelot-icpu-intr.yaml | 60 +++++++++++++++++++
2 files changed, 60 insertions(+), 21 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
deleted file mode 100644
index f5baeccb689f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-Microsemi Ocelot SoC ICPU Interrupt Controller
-
-Required properties:
-
-- compatible : should be "mscc,ocelot-icpu-intr"
-- reg : Specifies base physical address and size of the registers.
-- interrupt-controller : Identifies the node as an interrupt controller
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 1.
-- interrupts : Specifies the CPU interrupt the controller is connected to.
-
-Example:
-
- intc: interrupt-controller@70000070 {
- compatible = "mscc,ocelot-icpu-intr";
- reg = <0x70000070 0x70>;
- #interrupt-cells = <1>;
- interrupt-controller;
- interrupt-parent = <&cpuintc>;
- interrupts = <2>;
- };
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
new file mode 100644
index 000000000000..f34b319c7874
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Microsemi Ocelot SoC ICPU Interrupt Controller
+
+maintainers:
+ - Alexandre Belloni <alexandre.belloni@bootlin.com>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+description: |
+ the Microsemi Ocelot interrupt controller that is part of the
+ ICPU. It is connected directly to the MIPS core interrupt
+ controller.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mscc,ocelot-icpu-intr
+
+ '#interrupt-cells':
+ const: 1
+
+ '#address-cells':
+ const: 0
+
+ interrupt-controller: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - '#interrupt-cells'
+ - '#address-cells'
+ - interrupt-controller
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ intc: interrupt-controller@70000070 {
+ compatible = "mscc,ocelot-icpu-intr";
+ reg = <0x70000070 0x70>;
+ #interrupt-cells = <1>;
+ #address-cells = <0>;
+ interrupt-controller;
+ interrupt-parent = <&cpuintc>;
+ interrupts = <2>;
+ };
+...
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema
2020-11-20 16:41 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT
@ 2020-11-20 21:03 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-11-20 21:03 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Marc Zyngier, Steen.Hegelund, Thomas Petazzoni,
Alexandre Belloni, Lars Povlsen, Rob Herring, devicetree,
Jason Cooper, linux-kernel, Thomas Gleixner
On Fri, 20 Nov 2020 17:41:03 +0100, Gregory CLEMENT wrote:
> Convert device tree bindings for Microsemi Ocelot SoC ICPU Interrupt
> Controller to YAML format
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---
> .../mscc,ocelot-icpu-intr.txt | 21 -------
> .../mscc,ocelot-icpu-intr.yaml | 60 +++++++++++++++++++
> 2 files changed, 60 insertions(+), 21 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
./Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml:55:1: [error] syntax error: found character '\t' that cannot start any token (syntax)
dtschema/dtc warnings/errors:
Traceback (most recent call last):
File "/usr/local/bin/dt-extract-example", line 45, in <module>
binding = yaml.load(open(args.yamlfile, encoding='utf-8').read())
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/main.py", line 343, in load
return constructor.get_single_data()
File "/usr/local/lib/python3.8/dist-packages/ruamel/yaml/constructor.py", line 111, in get_single_data
node = self.composer.get_single_node()
File "_ruamel_yaml.pyx", line 706, in _ruamel_yaml.CParser.get_single_node
File "_ruamel_yaml.pyx", line 724, in _ruamel_yaml.CParser._compose_document
File "_ruamel_yaml.pyx", line 775, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 889, in _ruamel_yaml.CParser._compose_mapping_node
File "_ruamel_yaml.pyx", line 773, in _ruamel_yaml.CParser._compose_node
File "_ruamel_yaml.pyx", line 848, in _ruamel_yaml.CParser._compose_sequence_node
File "_ruamel_yaml.pyx", line 904, in _ruamel_yaml.CParser._parse_next_event
ruamel.yaml.scanner.ScannerError: while scanning a block scalar
in "<unicode string>", line 50, column 5
found a tab character where an indentation space is expected
in "<unicode string>", line 55, column 1
make[1]: *** [Documentation/devicetree/bindings/Makefile:20: Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.example.dts] Error 1
make[1]: *** Deleting file 'Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.example.dts'
make[1]: *** Waiting for unfinished jobs....
make[1]: *** [Documentation/devicetree/bindings/Makefile:59: Documentation/devicetree/bindings/processed-schema-examples.json] Error 123
make: *** [Makefile:1364: dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1403891
The base for the patch is generally the last rc1. Any dependencies
should be noted.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC Gregory CLEMENT
` (3 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
Add the Device Tree binding documentation for the Microsemi Jaguar2,
Luton and Serval interrupt controller that is part of the ICPU. It is
connected directly to the MIPS core interrupt controller.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
.../bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
index f34b319c7874..92fb1baf600f 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -21,7 +21,11 @@ properties:
compatible:
items:
- enum:
+ - mscc,jaguar2-icpu-intr
+ - mscc,luton-icpu-intr
- mscc,ocelot-icpu-intr
+ - mscc,serval-icpu-intr
+
'#interrupt-cells':
const: 1
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 1/6] dt-bindings: interrupt-controller: convert icpu intr bindings to json-schema Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 2/6] dt-bindings: interrupt-controller: Add binding for few Microsemi interrupt controllers Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
2020-11-23 8:04 ` Alexandre Belloni
2020-11-20 16:41 ` [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT
` (2 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
This patch extends irqchip driver for oceleot to be used with other
vcoreiii base platforms.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/irqchip/irq-mscc-ocelot.c | 76 ++++++++++++++++++++++---------
1 file changed, 54 insertions(+), 22 deletions(-)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 88143c0b700c..6d4029a2ded0 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -12,30 +12,51 @@
#include <linux/irqchip/chained_irq.h>
#include <linux/interrupt.h>
-#define ICPU_CFG_INTR_INTR_STICKY 0x10
-#define ICPU_CFG_INTR_INTR_ENA 0x18
-#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c
-#define ICPU_CFG_INTR_INTR_ENA_SET 0x20
-#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x))
-#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x))
-
-#define OCELOT_NR_IRQ 24
+#define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
+#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
+
+#define FLAGS_HAS_TRIGGER BIT(0)
+
+struct chip_props {
+ u8 flags;
+ u8 reg_off_sticky;
+ u8 reg_off_ena;
+ u8 reg_off_ena_clr;
+ u8 reg_off_ena_set;
+ u8 reg_off_ident;
+ u8 reg_off_trigger;
+ u8 reg_off_ena_irq0;
+ u8 n_irq;
+};
+
+static struct chip_props ocelot_props = {
+ .flags = FLAGS_HAS_TRIGGER,
+ .reg_off_sticky = 0x10,
+ .reg_off_ena = 0x18,
+ .reg_off_ena_clr = 0x1c,
+ .reg_off_ena_set = 0x20,
+ .reg_off_ident = 0x38,
+ .reg_off_trigger = 0x5c,
+ .n_irq = 24,
+};
static void ocelot_irq_unmask(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
+ struct irq_domain *d = data->domain;
+ struct chip_props *p = d->host_data;
struct irq_chip_type *ct = irq_data_get_chip_type(data);
unsigned int mask = data->mask;
u32 val;
irq_gc_lock(gc);
- val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |
- irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));
+ val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
+ irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
if (!(val & mask))
- irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);
+ irq_reg_writel(gc, mask, p->reg_off_sticky);
*ct->mask_cache &= ~mask;
- irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);
+ irq_reg_writel(gc, mask, p->reg_off_ena_set);
irq_gc_unlock(gc);
}
@@ -43,8 +64,9 @@ static void ocelot_irq_handler(struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_domain *d = irq_desc_get_handler_data(desc);
+ struct chip_props *p = d->host_data;
struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
- u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));
+ u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0));
chained_irq_enter(chip, desc);
@@ -58,8 +80,9 @@ static void ocelot_irq_handler(struct irq_desc *desc)
chained_irq_exit(chip, desc);
}
-static int __init ocelot_irq_init(struct device_node *node,
- struct device_node *parent)
+static int __init vcoreiii_irq_init(struct device_node *node,
+ struct device_node *parent,
+ struct chip_props *p)
{
struct irq_domain *domain;
struct irq_chip_generic *gc;
@@ -69,14 +92,14 @@ static int __init ocelot_irq_init(struct device_node *node,
if (!parent_irq)
return -EINVAL;
- domain = irq_domain_add_linear(node, OCELOT_NR_IRQ,
+ domain = irq_domain_add_linear(node, p->n_irq,
&irq_generic_chip_ops, NULL);
if (!domain) {
pr_err("%pOFn: unable to add irq domain\n", node);
return -ENOMEM;
}
- ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1,
+ ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1,
"icpu", handle_level_irq,
0, 0, 0);
if (ret) {
@@ -92,16 +115,18 @@ static int __init ocelot_irq_init(struct device_node *node,
goto err_gc_free;
}
- gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;
- gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;
+ gc->chip_types[0].regs.ack = p->reg_off_sticky;
+ gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
- gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
+ if (p->flags & FLAGS_HAS_TRIGGER)
+ gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
/* Mask and ack all interrupts */
- irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);
- irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);
+ irq_reg_writel(gc, 0, p->reg_off_ena);
+ irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
+ domain->host_data = p;
irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
domain);
@@ -115,4 +140,11 @@ static int __init ocelot_irq_init(struct device_node *node,
return ret;
}
+
+static int __init ocelot_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return vcoreiii_irq_init(node, parent, &ocelot_props);
+}
+
IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC
2020-11-20 16:41 ` [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC Gregory CLEMENT
@ 2020-11-23 8:04 ` Alexandre Belloni
0 siblings, 0 replies; 10+ messages in thread
From: Alexandre Belloni @ 2020-11-23 8:04 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen,
Steen.Hegelund
On 20/11/2020 17:41:05+0100, Gregory CLEMENT wrote:
> This patch extends irqchip driver for oceleot to be used with other
> vcoreiii base platforms.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/irqchip/irq-mscc-ocelot.c | 76 ++++++++++++++++++++++---------
> 1 file changed, 54 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
> index 88143c0b700c..6d4029a2ded0 100644
> --- a/drivers/irqchip/irq-mscc-ocelot.c
> +++ b/drivers/irqchip/irq-mscc-ocelot.c
> @@ -12,30 +12,51 @@
> #include <linux/irqchip/chained_irq.h>
> #include <linux/interrupt.h>
>
> -#define ICPU_CFG_INTR_INTR_STICKY 0x10
> -#define ICPU_CFG_INTR_INTR_ENA 0x18
> -#define ICPU_CFG_INTR_INTR_ENA_CLR 0x1c
> -#define ICPU_CFG_INTR_INTR_ENA_SET 0x20
> -#define ICPU_CFG_INTR_DST_INTR_IDENT(x) (0x38 + 0x4 * (x))
> -#define ICPU_CFG_INTR_INTR_TRIGGER(x) (0x5c + 0x4 * (x))
> -
> -#define OCELOT_NR_IRQ 24
> +#define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
> +#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
> +
> +#define FLAGS_HAS_TRIGGER BIT(0)
> +
> +struct chip_props {
> + u8 flags;
> + u8 reg_off_sticky;
> + u8 reg_off_ena;
> + u8 reg_off_ena_clr;
> + u8 reg_off_ena_set;
> + u8 reg_off_ident;
> + u8 reg_off_trigger;
> + u8 reg_off_ena_irq0;
> + u8 n_irq;
> +};
> +
> +static struct chip_props ocelot_props = {
> + .flags = FLAGS_HAS_TRIGGER,
> + .reg_off_sticky = 0x10,
> + .reg_off_ena = 0x18,
> + .reg_off_ena_clr = 0x1c,
> + .reg_off_ena_set = 0x20,
> + .reg_off_ident = 0x38,
> + .reg_off_trigger = 0x5c,
> + .n_irq = 24,
> +};
>
> static void ocelot_irq_unmask(struct irq_data *data)
> {
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
> + struct irq_domain *d = data->domain;
> + struct chip_props *p = d->host_data;
> struct irq_chip_type *ct = irq_data_get_chip_type(data);
> unsigned int mask = data->mask;
> u32 val;
>
> irq_gc_lock(gc);
> - val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(0)) |
> - irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(1));
> + val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
> + irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
> if (!(val & mask))
> - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_STICKY);
> + irq_reg_writel(gc, mask, p->reg_off_sticky);
>
> *ct->mask_cache &= ~mask;
> - irq_reg_writel(gc, mask, ICPU_CFG_INTR_INTR_ENA_SET);
> + irq_reg_writel(gc, mask, p->reg_off_ena_set);
> irq_gc_unlock(gc);
> }
>
> @@ -43,8 +64,9 @@ static void ocelot_irq_handler(struct irq_desc *desc)
> {
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct irq_domain *d = irq_desc_get_handler_data(desc);
> + struct chip_props *p = d->host_data;
> struct irq_chip_generic *gc = irq_get_domain_generic_chip(d, 0);
> - u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(0));
> + u32 reg = irq_reg_readl(gc, ICPU_CFG_INTR_DST_INTR_IDENT(p, 0));
>
> chained_irq_enter(chip, desc);
>
> @@ -58,8 +80,9 @@ static void ocelot_irq_handler(struct irq_desc *desc)
> chained_irq_exit(chip, desc);
> }
>
> -static int __init ocelot_irq_init(struct device_node *node,
> - struct device_node *parent)
> +static int __init vcoreiii_irq_init(struct device_node *node,
> + struct device_node *parent,
> + struct chip_props *p)
> {
> struct irq_domain *domain;
> struct irq_chip_generic *gc;
> @@ -69,14 +92,14 @@ static int __init ocelot_irq_init(struct device_node *node,
> if (!parent_irq)
> return -EINVAL;
>
> - domain = irq_domain_add_linear(node, OCELOT_NR_IRQ,
> + domain = irq_domain_add_linear(node, p->n_irq,
> &irq_generic_chip_ops, NULL);
> if (!domain) {
> pr_err("%pOFn: unable to add irq domain\n", node);
> return -ENOMEM;
> }
>
> - ret = irq_alloc_domain_generic_chips(domain, OCELOT_NR_IRQ, 1,
> + ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1,
> "icpu", handle_level_irq,
> 0, 0, 0);
> if (ret) {
> @@ -92,16 +115,18 @@ static int __init ocelot_irq_init(struct device_node *node,
> goto err_gc_free;
> }
>
> - gc->chip_types[0].regs.ack = ICPU_CFG_INTR_INTR_STICKY;
> - gc->chip_types[0].regs.mask = ICPU_CFG_INTR_INTR_ENA_CLR;
> + gc->chip_types[0].regs.ack = p->reg_off_sticky;
> + gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
> gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
> gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> - gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
> + if (p->flags & FLAGS_HAS_TRIGGER)
> + gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
>
> /* Mask and ack all interrupts */
> - irq_reg_writel(gc, 0, ICPU_CFG_INTR_INTR_ENA);
> - irq_reg_writel(gc, 0xffffffff, ICPU_CFG_INTR_INTR_STICKY);
> + irq_reg_writel(gc, 0, p->reg_off_ena);
> + irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
>
> + domain->host_data = p;
> irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
> domain);
>
> @@ -115,4 +140,11 @@ static int __init ocelot_irq_init(struct device_node *node,
>
> return ret;
> }
> +
> +static int __init ocelot_irq_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + return vcoreiii_irq_init(node, parent, &ocelot_props);
> +}
> +
> IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
> --
> 2.29.2
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
` (2 preceding siblings ...)
2020-11-20 16:41 ` [PATCH v4 3/6] irqchip: ocelot: prepare to support more SoC Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
2020-11-23 8:04 ` Alexandre Belloni
2020-11-20 16:41 ` [PATCH v4 5/6] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 6/6] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT
5 siblings, 1 reply; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
This patch extends irqchip driver for oceleot to be used with an other
vcoreiii base platform: Luton.
For this platform there is a few differences:
- the interrupt must be enabled for the parent controller
- there is no trigger register needed to be managed
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/irqchip/irq-mscc-ocelot.c | 38 +++++++++++++++++++++++++++----
1 file changed, 34 insertions(+), 4 deletions(-)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 6d4029a2ded0..496f955b8fc4 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -16,6 +16,7 @@
#define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
#define FLAGS_HAS_TRIGGER BIT(0)
+#define FLAGS_NEED_INIT_ENABLE BIT(1)
struct chip_props {
u8 flags;
@@ -40,6 +41,17 @@ static struct chip_props ocelot_props = {
.n_irq = 24,
};
+static struct chip_props luton_props = {
+ .flags = FLAGS_NEED_INIT_ENABLE,
+ .reg_off_sticky = 0,
+ .reg_off_ena = 0x4,
+ .reg_off_ena_clr = 0x8,
+ .reg_off_ena_set = 0xc,
+ .reg_off_ident = 0x18,
+ .reg_off_ena_irq0 = 0x14,
+ .n_irq = 28,
+};
+
static void ocelot_irq_unmask(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
@@ -115,17 +127,27 @@ static int __init vcoreiii_irq_init(struct device_node *node,
goto err_gc_free;
}
- gc->chip_types[0].regs.ack = p->reg_off_sticky;
- gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
- gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
- if (p->flags & FLAGS_HAS_TRIGGER)
+ gc->chip_types[0].regs.ack = p->reg_off_sticky;
+ if (p->flags & FLAGS_HAS_TRIGGER) {
+ gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
+ } else {
+ gc->chip_types[0].regs.enable = p->reg_off_ena_set;
+ gc->chip_types[0].regs.disable = p->reg_off_ena_clr;
+ gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
+ gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
+ }
/* Mask and ack all interrupts */
irq_reg_writel(gc, 0, p->reg_off_ena);
irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
+ /* Overall init */
+ if (p->flags & FLAGS_NEED_INIT_ENABLE)
+ irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);
+
domain->host_data = p;
irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
domain);
@@ -148,3 +170,11 @@ static int __init ocelot_irq_init(struct device_node *node,
}
IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
+
+static int __init luton_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return vcoreiii_irq_init(node, parent, &luton_props);
+}
+
+IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms
2020-11-20 16:41 ` [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT
@ 2020-11-23 8:04 ` Alexandre Belloni
0 siblings, 0 replies; 10+ messages in thread
From: Alexandre Belloni @ 2020-11-23 8:04 UTC (permalink / raw)
To: Gregory CLEMENT
Cc: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree, Thomas Petazzoni, Lars Povlsen,
Steen.Hegelund
On 20/11/2020 17:41:06+0100, Gregory CLEMENT wrote:
> This patch extends irqchip driver for oceleot to be used with an other
> vcoreiii base platform: Luton.
>
> For this platform there is a few differences:
> - the interrupt must be enabled for the parent controller
> - there is no trigger register needed to be managed
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
> ---
> drivers/irqchip/irq-mscc-ocelot.c | 38 +++++++++++++++++++++++++++----
> 1 file changed, 34 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
> index 6d4029a2ded0..496f955b8fc4 100644
> --- a/drivers/irqchip/irq-mscc-ocelot.c
> +++ b/drivers/irqchip/irq-mscc-ocelot.c
> @@ -16,6 +16,7 @@
> #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x) ((_p)->reg_off_trigger + 0x4 * (x))
>
> #define FLAGS_HAS_TRIGGER BIT(0)
> +#define FLAGS_NEED_INIT_ENABLE BIT(1)
>
> struct chip_props {
> u8 flags;
> @@ -40,6 +41,17 @@ static struct chip_props ocelot_props = {
> .n_irq = 24,
> };
>
> +static struct chip_props luton_props = {
> + .flags = FLAGS_NEED_INIT_ENABLE,
> + .reg_off_sticky = 0,
> + .reg_off_ena = 0x4,
> + .reg_off_ena_clr = 0x8,
> + .reg_off_ena_set = 0xc,
> + .reg_off_ident = 0x18,
> + .reg_off_ena_irq0 = 0x14,
> + .n_irq = 28,
> +};
> +
> static void ocelot_irq_unmask(struct irq_data *data)
> {
> struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
> @@ -115,17 +127,27 @@ static int __init vcoreiii_irq_init(struct device_node *node,
> goto err_gc_free;
> }
>
> - gc->chip_types[0].regs.ack = p->reg_off_sticky;
> - gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
> gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
> - gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> - if (p->flags & FLAGS_HAS_TRIGGER)
> + gc->chip_types[0].regs.ack = p->reg_off_sticky;
> + if (p->flags & FLAGS_HAS_TRIGGER) {
> + gc->chip_types[0].regs.mask = p->reg_off_ena_clr;
> gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;
> + gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;
> + } else {
> + gc->chip_types[0].regs.enable = p->reg_off_ena_set;
> + gc->chip_types[0].regs.disable = p->reg_off_ena_clr;
> + gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;
> + gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;
> + }
>
> /* Mask and ack all interrupts */
> irq_reg_writel(gc, 0, p->reg_off_ena);
> irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);
>
> + /* Overall init */
> + if (p->flags & FLAGS_NEED_INIT_ENABLE)
> + irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);
> +
> domain->host_data = p;
> irq_set_chained_handler_and_data(parent_irq, ocelot_irq_handler,
> domain);
> @@ -148,3 +170,11 @@ static int __init ocelot_irq_init(struct device_node *node,
> }
>
> IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
> +
> +static int __init luton_irq_init(struct device_node *node,
> + struct device_node *parent)
> +{
> + return vcoreiii_irq_init(node, parent, &luton_props);
> +}
> +
> +IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
> --
> 2.29.2
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 5/6] irqchip: ocelot: Add support for Serval platforms
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
` (3 preceding siblings ...)
2020-11-20 16:41 ` [PATCH v4 4/6] irqchip: ocelot: Add support for Luton platforms Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
2020-11-20 16:41 ` [PATCH v4 6/6] irqchip: ocelot: Add support for Jaguar2 platforms Gregory CLEMENT
5 siblings, 0 replies; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Serval.
Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 496f955b8fc4..da5a0ad991a1 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -41,6 +41,17 @@ static struct chip_props ocelot_props = {
.n_irq = 24,
};
+static struct chip_props serval_props = {
+ .flags = FLAGS_HAS_TRIGGER,
+ .reg_off_sticky = 0xc,
+ .reg_off_ena = 0x14,
+ .reg_off_ena_clr = 0x18,
+ .reg_off_ena_set = 0x1c,
+ .reg_off_ident = 0x20,
+ .reg_off_trigger = 0x4,
+ .n_irq = 24,
+};
+
static struct chip_props luton_props = {
.flags = FLAGS_NEED_INIT_ENABLE,
.reg_off_sticky = 0,
@@ -171,6 +182,14 @@ static int __init ocelot_irq_init(struct device_node *node,
IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
+static int __init serval_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return vcoreiii_irq_init(node, parent, &serval_props);
+}
+
+IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init);
+
static int __init luton_irq_init(struct device_node *node,
struct device_node *parent)
{
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 6/6] irqchip: ocelot: Add support for Jaguar2 platforms
2020-11-20 16:41 [PATCH v4 0/6] Extend irqchip ocelot driver to support other SoCs Gregory CLEMENT
` (4 preceding siblings ...)
2020-11-20 16:41 ` [PATCH v4 5/6] irqchip: ocelot: Add support for Serval platforms Gregory CLEMENT
@ 2020-11-20 16:41 ` Gregory CLEMENT
5 siblings, 0 replies; 10+ messages in thread
From: Gregory CLEMENT @ 2020-11-20 16:41 UTC (permalink / raw)
To: Thomas Gleixner, Jason Cooper, Marc Zyngier, linux-kernel,
Rob Herring, devicetree
Cc: Thomas Petazzoni, Alexandre Belloni, Lars Povlsen,
Steen.Hegelund, Gregory CLEMENT
This patch extends irqchip driver for ocelot to be used with an other
vcoreiii base platform: Jaguar2.
Based on a larger patch from Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
---
drivers/irqchip/irq-mscc-ocelot.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index da5a0ad991a1..8235d98650c1 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -63,6 +63,17 @@ static struct chip_props luton_props = {
.n_irq = 28,
};
+static struct chip_props jaguar2_props = {
+ .flags = FLAGS_HAS_TRIGGER,
+ .reg_off_sticky = 0x10,
+ .reg_off_ena = 0x18,
+ .reg_off_ena_clr = 0x1c,
+ .reg_off_ena_set = 0x20,
+ .reg_off_ident = 0x38,
+ .reg_off_trigger = 0x5c,
+ .n_irq = 29,
+};
+
static void ocelot_irq_unmask(struct irq_data *data)
{
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
@@ -197,3 +208,11 @@ static int __init luton_irq_init(struct device_node *node,
}
IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
+
+static int __init jaguar2_irq_init(struct device_node *node,
+ struct device_node *parent)
+{
+ return vcoreiii_irq_init(node, parent, &jaguar2_props);
+}
+
+IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init);
--
2.29.2
^ permalink raw reply related [flat|nested] 10+ messages in thread