* [PATCH] drm/mediatek: fine tune the data lane trail by project dts
@ 2021-02-01 3:47 Jitao Shi
2021-02-03 4:02 ` Nicolas Boichat
2021-03-18 0:31 ` Chun-Kuang Hu
0 siblings, 2 replies; 3+ messages in thread
From: Jitao Shi @ 2021-02-01 3:47 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Matthias Brugger, Daniel Vetter,
David Airlie, dri-devel, linux-kernel
Cc: linux-mediatek, devicetree, linux-arm-kernel, srv_heupstream,
yingjoe.chen, eddie.huang, cawa.cheng, bibby.hsieh, ck.hu,
stonea168, huijuan.xie, shuijing.li, Jitao Shi
Some panels or bridges require customized hs_da_trail time.
So add a property in devicetree for this panels and bridges.
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 8c70ec39bfe1..6e7092fa2fee 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -194,6 +194,7 @@ struct mtk_dsi {
struct clk *hs_clk;
u32 data_rate;
+ u32 da_trail_delta;
unsigned long mode_flags;
enum mipi_dsi_pixel_format format;
@@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
timing->da_hs_prepare;
- timing->da_hs_trail = timing->da_hs_prepare + 1;
+ timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
timing->ta_go = 4 * timing->lpx - 2;
timing->ta_sure = timing->lpx + 2;
@@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
goto err_unregister_host;
}
+ ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
+ &dsi->da_trail_delta);
+ if (ret) {
+ dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n", ret);
+ dsi->da_trail_delta = 0;
+ }
+
comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
if (comp_id < 0) {
dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
--
2.12.5
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH] drm/mediatek: fine tune the data lane trail by project dts
2021-02-01 3:47 [PATCH] drm/mediatek: fine tune the data lane trail by project dts Jitao Shi
@ 2021-02-03 4:02 ` Nicolas Boichat
2021-03-18 0:31 ` Chun-Kuang Hu
1 sibling, 0 replies; 3+ messages in thread
From: Nicolas Boichat @ 2021-02-03 4:02 UTC (permalink / raw)
To: Jitao Shi
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Daniel Vetter,
David Airlie, dri-devel, lkml, Devicetree List, srv_heupstream,
huijuan.xie, stonea168, cawa cheng, shuijing.li,
moderated list:ARM/Mediatek SoC support, Yingjoe Chen,
Eddie Huang, linux-arm Mailing List
On Mon, Feb 1, 2021 at 11:48 AM Jitao Shi <jitao.shi@mediatek.com> wrote:
>
> Some panels or bridges require customized hs_da_trail time.
> So add a property in devicetree for this panels and bridges.
Since this changes the device tree, you also need to upload a binding
document change.
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 8c70ec39bfe1..6e7092fa2fee 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -194,6 +194,7 @@ struct mtk_dsi {
> struct clk *hs_clk;
>
> u32 data_rate;
> + u32 da_trail_delta;
>
> unsigned long mode_flags;
> enum mipi_dsi_pixel_format format;
> @@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
> timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
> timing->da_hs_prepare;
> - timing->da_hs_trail = timing->da_hs_prepare + 1;
> + timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
>
> timing->ta_go = 4 * timing->lpx - 2;
> timing->ta_sure = timing->lpx + 2;
> @@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> goto err_unregister_host;
> }
>
> + ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
> + &dsi->da_trail_delta);
> + if (ret) {
> + dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n", ret);
> + dsi->da_trail_delta = 0;
> + }
> +
> comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
> if (comp_id < 0) {
> dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> --
> 2.12.5
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH] drm/mediatek: fine tune the data lane trail by project dts
2021-02-01 3:47 [PATCH] drm/mediatek: fine tune the data lane trail by project dts Jitao Shi
2021-02-03 4:02 ` Nicolas Boichat
@ 2021-03-18 0:31 ` Chun-Kuang Hu
1 sibling, 0 replies; 3+ messages in thread
From: Chun-Kuang Hu @ 2021-03-18 0:31 UTC (permalink / raw)
To: Jitao Shi
Cc: Rob Herring, Mark Rutland, Matthias Brugger, Daniel Vetter,
David Airlie, DRI Development, linux-kernel, DTML,
srv_heupstream, huijuan.xie, stonea168, Cawa Cheng, shuijing.li,
moderated list:ARM/Mediatek SoC support, yingjoe.chen,
eddie.huang, Linux ARM
Hi, Jitao:
Jitao Shi <jitao.shi@mediatek.com> 於 2021年2月1日 週一 上午11:48寫道：
>
> Some panels or bridges require customized hs_da_trail time.
> So add a property in devicetree for this panels and bridges.
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
> index 8c70ec39bfe1..6e7092fa2fee 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dsi.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
> @@ -194,6 +194,7 @@ struct mtk_dsi {
> struct clk *hs_clk;
>
> u32 data_rate;
> + u32 da_trail_delta;
>
> unsigned long mode_flags;
> enum mipi_dsi_pixel_format format;
> @@ -234,7 +235,7 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
> timing->da_hs_prepare = (80 * data_rate_mhz + 4 * 1000) / 8000;
> timing->da_hs_zero = (170 * data_rate_mhz + 10 * 1000) / 8000 + 1 -
> timing->da_hs_prepare;
> - timing->da_hs_trail = timing->da_hs_prepare + 1;
> + timing->da_hs_trail = timing->da_hs_prepare + 1 + dsi->da_trail_delta;
>
> timing->ta_go = 4 * timing->lpx - 2;
> timing->ta_sure = timing->lpx + 2;
> @@ -1094,6 +1095,13 @@ static int mtk_dsi_probe(struct platform_device *pdev)
> goto err_unregister_host;
> }
>
> + ret = of_property_read_u32_index(dev->of_node, "da_trail_delta", 0,
> + &dsi->da_trail_delta);
This value depends on panel, so I think we should get some value from
panel's device node to calculate this value.
Regards,
Chun-Kuang.
> + if (ret) {
> + dev_info(dev, "Can't get da_trail_delta, keep it as 0: %d\n", ret);
> + dsi->da_trail_delta = 0;
> + }
> +
> comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DSI);
> if (comp_id < 0) {
> dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> --
> 2.12.5
> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 3+ messages in thread
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2021-02-01 3:47 [PATCH] drm/mediatek: fine tune the data lane trail by project dts Jitao Shi
2021-02-03 4:02 ` Nicolas Boichat
2021-03-18 0:31 ` Chun-Kuang Hu
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