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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
	suzuki.poulose@arm.com, mike.leach@linaro.org,
	lcherian@marvell.com, linux-kernel@vger.kernel.org,
	Leo Yan <leo.yan@linaro.org>
Subject: Re: [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles
Date: Wed, 3 Feb 2021 12:05:13 -0700	[thread overview]
Message-ID: <20210203190513.GF1536093@xps15> (raw)
In-Reply-To: <1611737738-1493-8-git-send-email-anshuman.khandual@arm.com>

On Wed, Jan 27, 2021 at 02:25:31PM +0530, Anshuman Khandual wrote:
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> The context associated with an ETM for a given perf event
> includes :
>   - handle -> the perf output handle for the AUX buffer.
>   - the path for the trace components
>   - the buffer config for the sink.
> 
> The path and the buffer config are part of the "aux_priv" data
> (etm_event_data) setup by the setup_aux() callback, and made available
> via perf_get_aux(handle).
> 
> Now with a sink supporting IRQ, the sink could "end" an output
> handle when the buffer reaches the programmed limit and would try
> to restart a handle. This could fail if there is not enough
> space left the AUX buffer (e.g, the userspace has not consumed
> the data). This leaves the "handle" disconnected from the "event"
> and also the "perf_get_aux()" cleared. This all happens within
> the sink driver, without the etm_perf driver being aware.
> Now when the event is actually stopped, etm_event_stop()
> will need to access the "event_data". But since the handle
> is not valid anymore, we loose the information to stop the
> "trace" path. So, we need a reliable way to access the etm_event_data
> even when the handle may not be active.
> 
> This patch replaces the per_cpu handle array with a per_cpu context
> for the ETM, which tracks the "handle" as well as the "etm_event_data".
> The context notes the etm_event_data at etm_event_start() and clears
> it at etm_event_stop(). This makes sure that we don't access a
> stale "etm_event_data" as we are guaranteed that it is not
> freed by free_aux() as long as the event is active and tracing,
> also provides us with access to the critical information
> needed to wind up a session even in the absence of an active
> output_handle.
> 
> This is not an issue for the legacy sinks as none of them supports
> an IRQ and is centrally handled by the etm-perf.
> 
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Cc: Anshuman Khandual <anshuman.khandual@arm.com>
> Cc: Leo Yan <leo.yan@linaro.org>
> Cc: Mike Leach <mike.leach@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm-perf.c | 45 +++++++++++++++++++++---
>  1 file changed, 40 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm-perf.c b/drivers/hwtracing/coresight/coresight-etm-perf.c
> index eb9e7e9..a3977b0 100644
> --- a/drivers/hwtracing/coresight/coresight-etm-perf.c
> +++ b/drivers/hwtracing/coresight/coresight-etm-perf.c
> @@ -24,7 +24,26 @@
>  static struct pmu etm_pmu;
>  static bool etm_perf_up;
>  
> -static DEFINE_PER_CPU(struct perf_output_handle, ctx_handle);
> +/*
> + * An ETM context for a running event includes the perf aux handle
> + * and aux_data. For ETM, the aux_data (etm_event_data), consists of
> + * the trace path and the sink configuration. The event data is accessible
> + * via perf_get_aux(handle). However, a sink could "end" a perf output
> + * handle via the IRQ handler. And if the "sink" encounters a failure
> + * to "begin" another session (e.g due to lack of space in the buffer),
> + * the handle will be cleared. Thus, the event_data may not be accessible
> + * from the handle when we get to the etm_event_stop(), which is required
> + * for stopping the trace path. The event_data is guaranteed to stay alive
> + * until "free_aux()", which cannot happen as long as the event is active on
> + * the ETM. Thus the event_data for the session must be part of the ETM context
> + * to make sure we can disable the trace path.
> + */
> +struct etm_ctxt {
> +	struct perf_output_handle handle;
> +	struct etm_event_data *event_data;
> +};
> +
> +static DEFINE_PER_CPU(struct etm_ctxt, etm_ctxt);
>  static DEFINE_PER_CPU(struct coresight_device *, csdev_src);
>  
>  /* ETMv3.5/PTM's ETMCR is 'config' */
> @@ -332,7 +351,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>  {
>  	int cpu = smp_processor_id();
>  	struct etm_event_data *event_data;
> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +	struct perf_output_handle *handle = &ctxt->handle;
>  	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
>  	struct list_head *path;
> 
        if (!csdev)
                goto fail;

        /*
         * Something went wrong if an event data is already associated
         * with a context.
         */
        if (WARN_ONE(ctxt->event_data))
                goto fail;
 
> @@ -374,6 +394,8 @@ static void etm_event_start(struct perf_event *event, int flags)
>  	if (source_ops(csdev)->enable(csdev, event, CS_MODE_PERF))
>  		goto fail_disable_path;
>  
> +	/* Save the event_data for this ETM */
> +	ctxt->event_data = event_data;
>  out:
>  	return;
>  
> @@ -392,13 +414,20 @@ static void etm_event_stop(struct perf_event *event, int mode)
>  	int cpu = smp_processor_id();
>  	unsigned long size;
>  	struct coresight_device *sink, *csdev = per_cpu(csdev_src, cpu);
> -	struct perf_output_handle *handle = this_cpu_ptr(&ctx_handle);
> -	struct etm_event_data *event_data = perf_get_aux(handle);
> +	struct etm_ctxt *ctxt = this_cpu_ptr(&etm_ctxt);
> +	struct perf_output_handle *handle = &ctxt->handle;

	struct etm_event_data *event_data = perf_get_aux(handle);
>  	struct list_head *path;
>

        if (WARN_ON(event_data && event_data != ctxt->event_data))
                return;

        event_data = ctxt->event_data;       
	/* Clear the event_data as this ETM is stopping the trace. */
	ctxt->event_data = NULL;

With the above:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
  
>  	if (event->hw.state == PERF_HES_STOPPED)
>  		return;
>  
> +	/* We must have a valid event_data for a running event */
> +	if (WARN_ON(!event_data))
> +		return;
> +
>  	if (!csdev)
>  		return;
>  
> @@ -416,7 +445,13 @@ static void etm_event_stop(struct perf_event *event, int mode)
>  	/* tell the core */
>  	event->hw.state = PERF_HES_STOPPED;
>  
> -	if (mode & PERF_EF_UPDATE) {
> +	/*
> +	 * If the handle is not bound to an event anymore
> +	 * (e.g, the sink driver was unable to restart the
> +	 * handle due to lack of buffer space), we don't
> +	 * have to do anything here.
> +	 */
> +	if (handle->event && (mode & PERF_EF_UPDATE)) {
>  		if (WARN_ON_ONCE(handle->event != event))
>  			return;
>  
> -- 
> 2.7.4
> 

  reply	other threads:[~2021-02-03 19:06 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-01-27  8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27  8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-02-01 23:17   ` Mathieu Poirier
2021-02-02  9:42     ` Suzuki K Poulose
2021-02-02 16:33       ` Mike Leach
2021-02-02 22:41         ` Suzuki K Poulose
2021-02-04 12:27           ` Mike Leach
2021-02-02 16:37       ` Mathieu Poirier
2021-01-27  8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-02-01 23:44   ` Mathieu Poirier
2021-02-02 11:10   ` Mike Leach
2021-02-02 14:36     ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-02-02 17:40   ` Mathieu Poirier
2021-02-02 18:03   ` Mathieu Poirier
2021-02-15 14:08   ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-02-02 17:52   ` Mathieu Poirier
2021-02-03 15:51     ` Suzuki K Poulose
2021-02-15 14:08   ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-02-02 18:56   ` Mathieu Poirier
2021-02-02 22:50     ` Suzuki K Poulose
2021-02-15 13:21     ` Mike Leach
2021-02-15 14:08       ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-02-09 19:00   ` Rob Herring
2021-02-10 12:33     ` Suzuki K Poulose
2021-02-18 18:33       ` Rob Herring
2021-02-18 22:51         ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-02-03 19:05   ` Mathieu Poirier [this message]
2021-02-03 23:36     ` Suzuki K Poulose
2021-02-15 16:27   ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-28  9:16   ` Suzuki K Poulose
2021-02-04 18:34     ` Mathieu Poirier
2021-02-16 10:40       ` Anshuman Khandual
2021-02-16 20:44         ` Mathieu Poirier
2021-02-16 10:21     ` Anshuman Khandual
2021-02-15 16:27   ` Mike Leach
2021-02-15 16:56     ` Mathieu Poirier
2021-02-15 17:58       ` Mike Leach
2021-02-16 20:30         ` Mathieu Poirier
2021-01-27  8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-28  9:31   ` Suzuki K Poulose
2021-01-28 17:18   ` Catalin Marinas
2021-02-15 18:06     ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27  9:58   ` Marc Zyngier
2021-01-28  9:34     ` Suzuki K Poulose
2021-01-28  9:46       ` Marc Zyngier
2021-01-28  9:48         ` Suzuki K Poulose
2021-01-27  8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
     [not found]   ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
2021-02-02  5:55     ` Anshuman Khandual
2021-02-05 17:53   ` Mathieu Poirier
2021-02-08  4:20     ` Anshuman Khandual
2021-02-09 17:39     ` Mathieu Poirier
2021-02-10  4:12       ` Anshuman Khandual
2021-02-10 16:54         ` Mathieu Poirier
2021-02-10 19:00   ` Mathieu Poirier
2021-02-12  5:43     ` Anshuman Khandual
2021-02-12 17:02       ` Mathieu Poirier
2021-02-11 19:00   ` Mathieu Poirier
2021-02-12  3:31     ` Anshuman Khandual
2021-02-12 16:57       ` Mathieu Poirier
2021-02-15  9:26         ` Anshuman Khandual
2021-02-12 20:26   ` Mathieu Poirier
2021-02-15  9:46     ` Anshuman Khandual
2021-02-16  9:00       ` Mike Leach
2021-02-16  9:44         ` Anshuman Khandual
2021-02-16 12:12           ` Mike Leach
2021-02-18  7:50         ` Suzuki K Poulose
2021-02-18 14:30           ` Mike Leach
2021-02-18 15:14             ` Suzuki K Poulose
2021-02-22 10:42               ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-02-09 19:04   ` Rob Herring
2021-01-27  8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 12:51   ` Peter Zijlstra
2021-02-16 10:59   ` Mike Leach
2021-01-27  8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 12:54   ` Peter Zijlstra
2021-01-27 13:00     ` Al Grant
2021-02-18  3:05       ` Anshuman Khandual
2021-01-27 14:12     ` Suzuki K Poulose
2021-02-16 11:01   ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18  4:23   ` Anshuman Khandual

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