From: Anshuman Khandual <anshuman.khandual@arm.com>
To: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: linux-arm-kernel@lists.infradead.org, coresight@lists.linaro.org,
suzuki.poulose@arm.com, mike.leach@linaro.org,
lcherian@marvell.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE
Date: Thu, 18 Feb 2021 09:53:22 +0530 [thread overview]
Message-ID: <e1af8031-5ba6-b04a-6e55-8d8d0f0c07c1@arm.com> (raw)
In-Reply-To: <20210201184436.GA1475392@xps15>
On 2/2/21 12:14 AM, Mathieu Poirier wrote:
> On Wed, Jan 27, 2021 at 02:25:24PM +0530, Anshuman Khandual wrote:
>> This series enables future IP trace features Embedded Trace Extension (ETE)
>> and Trace Buffer Extension (TRBE). This series depends on the ETM system
>> register instruction support series [0] which is available here [1]. This
>> series which applies on [1] is avaialble here [2] for quick access.
>>
>> ETE is the PE (CPU) trace unit for CPUs, implementing future architecture
>> extensions. ETE overlaps with the ETMv4 architecture, with additions to
>> support the newer architecture features and some restrictions on the
>> supported features w.r.t ETMv4. The ETE support is added by extending the
>> ETMv4 driver to recognise the ETE and handle the features as exposed by the
>> TRCIDRx registers. ETE only supports system instructions access from the
>> host CPU. The ETE could be integrated with a TRBE (see below), or with the
>> legacy CoreSight trace bus (e.g, ETRs). Thus the ETE follows same firmware
>> description as the ETMs and requires a node per instance.
>>
>> Trace Buffer Extensions (TRBE) implements a per CPU trace buffer, which is
>> accessible via the system registers and can be combined with the ETE to
>> provide a 1x1 configuration of source & sink. TRBE is being represented
>> here as a CoreSight sink. Primary reason is that the ETE source could work
>> with other traditional CoreSight sink devices. As TRBE captures the trace
>> data which is produced by ETE, it cannot work alone.
>>
>> TRBE representation here have some distinct deviations from a traditional
>> CoreSight sink device. Coresight path between ETE and TRBE are not built
>> during boot looking at respective DT or ACPI entries.
>>
>> Unlike traditional sinks, TRBE can generate interrupts to signal including
>> many other things, buffer got filled. The interrupt is a PPI and should be
>> communicated from the platform. DT or ACPI entry representing TRBE should
>> have the PPI number for a given platform. During perf session, the TRBE IRQ
>> handler should capture trace for perf auxiliary buffer before restarting it
>> back. System registers being used here to configure ETE and TRBE could be
>> referred in the link below.
>>
>> https://developer.arm.com/docs/ddi0601/g/aarch64-system-registers.
> This set is giving me several checkpatch.pl warnings... Those about complex
> macros and DT bindings are fine but everything else should have been addressed
> by now. Since this is your first patchset I will carry on but I expect future
> submissions to be clean.
>
Hello Mathieu,
All the potential patches for upcoming V4 series applies cleanly but these are
some checkpatch.pl errors or warnings which could not be resolved.
- Anshuman
1. 0004-coresight-ete-Add-support-for-ETE-sysreg-access.patch
=============================================================
ERROR: Macros with complex values should be enclosed in parentheses
#88: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:165:
+#define ETE_ONLY_SYSREG_LIST(op, val) \
+ CASE_##op((val), TRCRSR) \
+ CASE_##op((val), TRCEXTINSELRn(1)) \
+ CASE_##op((val), TRCEXTINSELRn(2)) \
+ CASE_##op((val), TRCEXTINSELRn(3))
ERROR: Macros with complex values should be enclosed in parentheses
#97: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:172:
+#define ETM4x_ONLY_SYSREG_LIST(op, val) \
CASE_##op((val), TRCPROCSELR) \
+ CASE_##op((val), TRCVDCTLR) \
+ CASE_##op((val), TRCVDSACCTLR) \
+ CASE_##op((val), TRCVDARCCTLR) \
+ CASE_##op((val), TRCOSLAR)
ERROR: Macros with complex values should be enclosed in parentheses
#104: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:179:
+#define ETM_COMMON_SYSREG_LIST(op, val) \
+ CASE_##op((val), TRCPRGCTLR) \
CASE_##op((val), TRCSTATR) \
CASE_##op((val), TRCCONFIGR) \
CASE_##op((val), TRCAUXCTLR) \
ERROR: Macros with complex values should be enclosed in parentheses
#133: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:382:
+#define ETM4x_READ_SYSREG_CASES(res) \
+ ETM_COMMON_SYSREG_LIST(READ, (res)) \
+ ETM4x_ONLY_SYSREG_LIST(READ, (res))
ERROR: Macros with complex values should be enclosed in parentheses
#137: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:386:
+#define ETM4x_WRITE_SYSREG_CASES(val) \
+ ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
+ ETM4x_ONLY_SYSREG_LIST(WRITE, (val))
ERROR: Macros with complex values should be enclosed in parentheses
#147: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:396:
+#define ETM4x_SYSREG_LIST_CASES \
+ ETM_COMMON_SYSREG_LIST_CASES \
+ ETM4x_ONLY_SYSREG_LIST(NOP, __unused)
ERROR: Macros with complex values should be enclosed in parentheses
#155: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:403:
+#define ETE_READ_CASES(res) \
+ ETM_COMMON_SYSREG_LIST(READ, (res)) \
+ ETE_ONLY_SYSREG_LIST(READ, (res))
ERROR: Macros with complex values should be enclosed in parentheses
#159: FILE: drivers/hwtracing/coresight/coresight-etm4x.h:407:
+#define ETE_WRITE_CASES(val) \
+ ETM_COMMON_SYSREG_LIST(WRITE, (val)) \
+ ETE_ONLY_SYSREG_LIST(WRITE, (val))
total: 8 errors, 0 warnings, 133 lines checked
2. 0006-dts-bindings-Document-device-tree-bindings-for-ETE.patch
================================================================
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#23:
new file mode 100644
total: 0 errors, 1 warnings, 74 lines checked
3. 0010-arm64-nvhe-Allow-TRBE-access-at-EL1.patch
=================================================
ERROR: spaces required around that ':' (ctx:VxE)
#49: FILE: arch/arm64/include/asm/el2_setup.h:93:
+1:
^
total: 1 errors, 0 warnings, 33 lines checked
4. 0011-coresight-sink-Add-TRBE-driver.patch
============================================
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#36:
new file mode 100644
total: 0 errors, 1 warnings, 1322 lines checked
5. 0012-dts-bindings-Document-device-tree-bindings-for-Arm-T.patch
==================================================================
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#22:
new file mode 100644
total: 0 errors, 1 warnings, 49 lines checked
6. 0014-coresight-etm-perf-Add-support-for-trace-buffer-form.patch
==================================================================
WARNING: line length of 103 exceeds 100 columns
#82: FILE: include/uapi/linux/perf_event.h:1115:
+#define PERF_AUX_FLAG_CORESIGHT_FORMAT_CORESIGHT 0x0000 /* Default for backward compatibility */
total: 0 errors, 1 warnings, 24 lines checked
prev parent reply other threads:[~2021-02-18 4:24 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-02-01 23:17 ` Mathieu Poirier
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 16:33 ` Mike Leach
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-04 12:27 ` Mike Leach
2021-02-02 16:37 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-02-01 23:44 ` Mathieu Poirier
2021-02-02 11:10 ` Mike Leach
2021-02-02 14:36 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-02-02 17:52 ` Mathieu Poirier
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-15 13:21 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-02-09 19:00 ` Rob Herring
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-18 18:33 ` Rob Herring
2021-02-18 22:51 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-15 16:27 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-28 9:16 ` Suzuki K Poulose
2021-02-04 18:34 ` Mathieu Poirier
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 10:21 ` Anshuman Khandual
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 17:58 ` Mike Leach
2021-02-16 20:30 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 17:18 ` Catalin Marinas
2021-02-15 18:06 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27 9:58 ` Marc Zyngier
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
[not found] ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
2021-02-02 5:55 ` Anshuman Khandual
2021-02-05 17:53 ` Mathieu Poirier
2021-02-08 4:20 ` Anshuman Khandual
2021-02-09 17:39 ` Mathieu Poirier
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 17:02 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 16:57 ` Mathieu Poirier
2021-02-15 9:26 ` Anshuman Khandual
2021-02-12 20:26 ` Mathieu Poirier
2021-02-15 9:46 ` Anshuman Khandual
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 12:12 ` Mike Leach
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 14:30 ` Mike Leach
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-22 10:42 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-02-09 19:04 ` Rob Herring
2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 12:51 ` Peter Zijlstra
2021-02-16 10:59 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 13:00 ` Al Grant
2021-02-18 3:05 ` Anshuman Khandual
2021-01-27 14:12 ` Suzuki K Poulose
2021-02-16 11:01 ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18 4:23 ` Anshuman Khandual [this message]
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