From: Mike Leach <mike.leach@linaro.org>
To: Anshuman Khandual <anshuman.khandual@arm.com>
Cc: linux-arm-kernel <linux-arm-kernel@lists.infradead.org>,
Coresight ML <coresight@lists.linaro.org>,
Mathieu Poirier <mathieu.poirier@linaro.org>,
"Suzuki K. Poulose" <suzuki.poulose@arm.com>,
Linu Cherian <lcherian@marvell.com>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Peter Ziljstra <peterz@infradead.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Ingo Molnar <mingo@redhat.com>, Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Jiri Olsa <jolsa@redhat.com>,
Mathieu Poirier <mathieu.poirer@linaro.org>
Subject: Re: [PATCH V3 13/14] perf: aux: Add flags for the buffer format
Date: Tue, 16 Feb 2021 10:59:33 +0000 [thread overview]
Message-ID: <CAJ9a7Vies-1wy8kmtpf_gFQgXi=rouP5njYkqjSQaCSrfUwt8w@mail.gmail.com> (raw)
In-Reply-To: <1611737738-1493-14-git-send-email-anshuman.khandual@arm.com>
On Wed, 27 Jan 2021 at 08:56, Anshuman Khandual
<anshuman.khandual@arm.com> wrote:
>
> From: Suzuki K Poulose <suzuki.poulose@arm.com>
>
> Allocate a byte for advertising the PMU specific format type
> of the given AUX record. A PMU could end up providing hardware
> trace data in multiple format in a single session.
>
> e.g, The format of hardware buffer produced by CoreSight ETM
> PMU depends on the type of the "sink" device used for collection
> for an event (Traditional TMC-ETR/Bs with formatting or
> TRBEs without any formatting).
>
> # Boring story of why this is needed. Goto The_End_of_Story for skipping.
>
> CoreSight ETM trace allows instruction level tracing of Arm CPUs.
> The ETM generates the CPU excecution trace and pumps it into CoreSight
> AMBA Trace Bus and is collected by a different CoreSight component
> (traditionally CoreSight TMC-ETR /ETB/ETF), called "sink".
> Important to note that there is no guarantee that every CPU has
> a dedicated sink. Thus multiple ETMs could pump the trace data
> into the same "sink" and thus they apply additional formatting
> of the trace data for the user to decode it properly and attribute
> the trace data to the corresponding ETM.
>
> However, with the introduction of Arm Trace buffer Extensions (TRBE),
> we now have a dedicated per-CPU architected sink for collecting the
> trace. Since the TRBE is always per-CPU, it doesn't apply any formatting
> of the trace. The support for this driver is under review [1].
>
> Now a system could have a per-cpu TRBE and one or more shared
> TMC-ETRs on the system. A user could choose a "specific" sink
> for a perf session (e.g, a TMC-ETR) or the driver could automatically
> select the nearest sink for a given ETM. It is possible that
> some ETMs could end up using TMC-ETR (e.g, if the TRBE is not
> usable on the CPU) while the others using TRBE in a single
> perf session. Thus we now have "formatted" trace collected
> from TMC-ETR and "unformatted" trace collected from TRBE.
> However, we don't get into a situation where a single event
> could end up using TMC-ETR & TRBE. i.e, any AUX buffer is
> guaranteed to be either RAW or FORMATTED, but not a mix
> of both.
>
> As for perf decoding, we need to know the type of the data
> in the individual AUX buffers, so that it can set up the
> "OpenCSD" (library for decoding CoreSight trace) decoder
> instance appropriately. Thus the perf.data file must conatin
> the hints for the tool to decode the data correctly.
>
> Since this is a runtime variable, and perf tool doesn't have
> a control on what sink gets used (in case of automatic sink
> selection), we need this information made available from
> the PMU driver for each AUX record.
>
> # The_End_of_Story
>
> Cc: Peter Ziljstra <peterz@infradead.org>
> Cc: alexander.shishkin@linux.intel.com
> Cc: mingo@redhat.com
> Cc: will@kernel.org
> Cc: mark.rutland@arm.com
> Cc: mike.leach@linaro.org
> Cc: acme@kernel.org
> Cc: jolsa@redhat.com
> Cc: Mathieu Poirier <mathieu.poirer@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
> include/uapi/linux/perf_event.h | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_event.h
> index b15e344..9a5ca45 100644
> --- a/include/uapi/linux/perf_event.h
> +++ b/include/uapi/linux/perf_event.h
> @@ -1105,10 +1105,11 @@ enum perf_callchain_context {
> /**
> * PERF_RECORD_AUX::flags bits
> */
> -#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
> -#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
> -#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
> -#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
> +#define PERF_AUX_FLAG_TRUNCATED 0x01 /* record was truncated to fit */
> +#define PERF_AUX_FLAG_OVERWRITE 0x02 /* snapshot from overwrite mode */
> +#define PERF_AUX_FLAG_PARTIAL 0x04 /* record contains gaps */
> +#define PERF_AUX_FLAG_COLLISION 0x08 /* sample collided with another */
> +#define PERF_AUX_FLAG_PMU_FORMAT_TYPE_MASK 0xff00 /* PMU specific trace format type */
>
> #define PERF_FLAG_FD_NO_GROUP (1UL << 0)
> #define PERF_FLAG_FD_OUTPUT (1UL << 1)
> --
> 2.7.4
>
Reviewed by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
next prev parent reply other threads:[~2021-02-16 11:03 UTC|newest]
Thread overview: 90+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 8:55 [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Anshuman Khandual
2021-01-27 8:55 ` [PATCH V3 01/14] coresight: etm-perf: Allow an event to use different sinks Anshuman Khandual
2021-02-01 23:17 ` Mathieu Poirier
2021-02-02 9:42 ` Suzuki K Poulose
2021-02-02 16:33 ` Mike Leach
2021-02-02 22:41 ` Suzuki K Poulose
2021-02-04 12:27 ` Mike Leach
2021-02-02 16:37 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 02/14] coresight: Do not scan for graph if none is present Anshuman Khandual
2021-02-01 23:44 ` Mathieu Poirier
2021-02-02 11:10 ` Mike Leach
2021-02-02 14:36 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 03/14] coresight: etm4x: Add support for PE OS lock Anshuman Khandual
2021-02-02 17:40 ` Mathieu Poirier
2021-02-02 18:03 ` Mathieu Poirier
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 04/14] coresight: ete: Add support for ETE sysreg access Anshuman Khandual
2021-02-02 17:52 ` Mathieu Poirier
2021-02-03 15:51 ` Suzuki K Poulose
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 05/14] coresight: ete: Add support for ETE tracing Anshuman Khandual
2021-02-02 18:56 ` Mathieu Poirier
2021-02-02 22:50 ` Suzuki K Poulose
2021-02-15 13:21 ` Mike Leach
2021-02-15 14:08 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 06/14] dts: bindings: Document device tree bindings for ETE Anshuman Khandual
2021-02-09 19:00 ` Rob Herring
2021-02-10 12:33 ` Suzuki K Poulose
2021-02-18 18:33 ` Rob Herring
2021-02-18 22:51 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 07/14] coresight: etm-perf: Handle stale output handles Anshuman Khandual
2021-02-03 19:05 ` Mathieu Poirier
2021-02-03 23:36 ` Suzuki K Poulose
2021-02-15 16:27 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 08/14] coresight: core: Add support for dedicated percpu sinks Anshuman Khandual
2021-01-28 9:16 ` Suzuki K Poulose
2021-02-04 18:34 ` Mathieu Poirier
2021-02-16 10:40 ` Anshuman Khandual
2021-02-16 20:44 ` Mathieu Poirier
2021-02-16 10:21 ` Anshuman Khandual
2021-02-15 16:27 ` Mike Leach
2021-02-15 16:56 ` Mathieu Poirier
2021-02-15 17:58 ` Mike Leach
2021-02-16 20:30 ` Mathieu Poirier
2021-01-27 8:55 ` [PATCH V3 09/14] arm64: Add TRBE definitions Anshuman Khandual
2021-01-28 9:31 ` Suzuki K Poulose
2021-01-28 17:18 ` Catalin Marinas
2021-02-15 18:06 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 10/14] arm64: nvhe: Allow TRBE access at EL1 Anshuman Khandual
2021-01-27 9:58 ` Marc Zyngier
2021-01-28 9:34 ` Suzuki K Poulose
2021-01-28 9:46 ` Marc Zyngier
2021-01-28 9:48 ` Suzuki K Poulose
2021-01-27 8:55 ` [PATCH V3 11/14] coresight: sink: Add TRBE driver Anshuman Khandual
[not found] ` <12cdc8ca-0a69-bfba-bbcd-fb392d6ca051@arm.com>
2021-02-02 5:55 ` Anshuman Khandual
2021-02-05 17:53 ` Mathieu Poirier
2021-02-08 4:20 ` Anshuman Khandual
2021-02-09 17:39 ` Mathieu Poirier
2021-02-10 4:12 ` Anshuman Khandual
2021-02-10 16:54 ` Mathieu Poirier
2021-02-10 19:00 ` Mathieu Poirier
2021-02-12 5:43 ` Anshuman Khandual
2021-02-12 17:02 ` Mathieu Poirier
2021-02-11 19:00 ` Mathieu Poirier
2021-02-12 3:31 ` Anshuman Khandual
2021-02-12 16:57 ` Mathieu Poirier
2021-02-15 9:26 ` Anshuman Khandual
2021-02-12 20:26 ` Mathieu Poirier
2021-02-15 9:46 ` Anshuman Khandual
2021-02-16 9:00 ` Mike Leach
2021-02-16 9:44 ` Anshuman Khandual
2021-02-16 12:12 ` Mike Leach
2021-02-18 7:50 ` Suzuki K Poulose
2021-02-18 14:30 ` Mike Leach
2021-02-18 15:14 ` Suzuki K Poulose
2021-02-22 10:42 ` Mike Leach
2021-01-27 8:55 ` [PATCH V3 12/14] dts: bindings: Document device tree bindings for Arm TRBE Anshuman Khandual
2021-02-09 19:04 ` Rob Herring
2021-01-27 8:55 ` [PATCH V3 13/14] perf: aux: Add flags for the buffer format Anshuman Khandual
2021-01-27 12:51 ` Peter Zijlstra
2021-02-16 10:59 ` Mike Leach [this message]
2021-01-27 8:55 ` [PATCH V3 14/14] coresight: etm-perf: Add support for trace " Anshuman Khandual
2021-01-27 12:54 ` Peter Zijlstra
2021-01-27 13:00 ` Al Grant
2021-02-18 3:05 ` Anshuman Khandual
2021-01-27 14:12 ` Suzuki K Poulose
2021-02-16 11:01 ` Mike Leach
2021-01-27 18:50 ` [PATCH V3 00/14] arm64: coresight: Enable ETE and TRBE Mathieu Poirier
2021-02-01 18:44 ` Mathieu Poirier
2021-02-18 4:23 ` Anshuman Khandual
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