[PATCH] mtd: rawnand: qcom: update last code word register

[PATCH] mtd: rawnand: qcom: update last code word register

[Md Sadre Alam]

From QPIC version 2.0 onwards new register got added to read last
codeword. This change will add the READ_LOCATION_LAST_CW_n register.

For first three code word READ_LOCATION_n register will be
use.For last code word READ_LOCATION_LAST_CW_n register will be
use.

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 90 +++++++++++++++++++++++++++++----------
 1 file changed, 67 insertions(+), 23 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 82d083ad..50fdf55 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -48,6 +48,10 @@
 #define	NAND_READ_LOCATION_1		0xf24
 #define	NAND_READ_LOCATION_2		0xf28
 #define	NAND_READ_LOCATION_3		0xf2c
+#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
+#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
+#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
+#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c
 
 /* dummy register offsets, used by write_reg_dma */
 #define	NAND_DEV_CMD1_RESTORE		0xdead
@@ -187,6 +191,11 @@ nandc_set_reg(nandc, reg,			\
 	      ((read_size) << READ_LOCATION_SIZE) |			\
 	      ((is_last_read_loc) << READ_LOCATION_LAST))
 
+#define nandc_set_read_loc_last(nandc, reg, cw_offset, read_size, is_last_read_loc)	\
+nandc_set_reg(nandc, reg,			\
+	      ((cw_offset) << READ_LOCATION_OFFSET) |		\
+	      ((read_size) << READ_LOCATION_SIZE) |			\
+	      ((is_last_read_loc) << READ_LOCATION_LAST))
 /*
  * Returns the actual register address for all NAND_DEV_ registers
  * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
@@ -316,6 +325,10 @@ struct nandc_regs {
 	__le32 read_location1;
 	__le32 read_location2;
 	__le32 read_location3;
+	__le32 read_location_last0;
+	__le32 read_location_last1;
+	__le32 read_location_last2;
+	__le32 read_location_last3;
 
 	__le32 erased_cw_detect_cfg_clr;
 	__le32 erased_cw_detect_cfg_set;
@@ -644,6 +657,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 		return &regs->read_location2;
 	case NAND_READ_LOCATION_3:
 		return &regs->read_location3;
+	case NAND_READ_LOCATION_LAST_CW_0:
+		return &regs->read_location_last0;
+	case NAND_READ_LOCATION_LAST_CW_1:
+		return &regs->read_location_last1;
+	case NAND_READ_LOCATION_LAST_CW_2:
+		return &regs->read_location_last2;
+	case NAND_READ_LOCATION_LAST_CW_3:
+		return &regs->read_location_last3;
 	default:
 		return NULL;
 	}
@@ -672,13 +693,19 @@ static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
 			       int cw_offset, int read_size, int is_last_read_loc)
 {
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
-
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	int reg_base = NAND_READ_LOCATION_0;
 
-	reg_base += reg * 4;
+	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
+		reg_base = NAND_READ_LOCATION_LAST_CW_0;
 
-	return nandc_set_read_loc_first(nandc, reg_base, cw_offset,
-			read_size, is_last_read_loc);
+	reg_base += reg * 4;
+	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
+		return nandc_set_read_loc_last(nandc, reg_base, cw_offset,
+				read_size, is_last_read_loc);
+	else
+		return nandc_set_read_loc_first(nandc, reg_base, cw_offset,
+				read_size, is_last_read_loc);
 }
 
 /* helper to configure address register values */
@@ -700,8 +727,9 @@ static void set_address(struct qcom_nand_host *host, u16 column, int page)
  *
  * @num_cw:		number of steps for the read/write operation
  * @read:		read or write operation
+ * @cw	:		which code word
  */
-static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
+static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
 {
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
@@ -740,7 +768,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
 	if (read)
-		nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
+		nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
 				   host->cw_data : host->cw_size, 1);
 }
 
@@ -1111,18 +1139,34 @@ static void config_nand_page_read(struct nand_chip *chip)
 		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
 }
 
+/* helper to check which location register should be use for this
+ * code word. NAND_READ_LOCATION or NAND_READ_LOCATION_LAST_CW
+ */
+static bool config_loc_last_reg(struct nand_chip *chip, int cw)
+{
+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
+		return true;
+
+	return false;
+}
 /*
  * Helper to prepare DMA descriptors for configuring registers
  * before reading each codeword in NAND page.
  */
 static void
-config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
+config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
 {
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	int reg = NAND_READ_LOCATION_0;
+
+	if (config_loc_last_reg(chip, cw))
+		reg = NAND_READ_LOCATION_LAST_CW_0;
 
 	if (nandc->props->is_bam)
-		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
-			      NAND_BAM_NEXT_SGL);
+		write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -1142,12 +1186,12 @@ config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
  */
 static void
 config_nand_single_cw_page_read(struct nand_chip *chip,
-				bool use_ecc)
+				bool use_ecc, int cw)
 {
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
 
 	config_nand_page_read(chip);
-	config_nand_cw_read(chip, use_ecc);
+	config_nand_cw_read(chip, use_ecc, cw);
 }
 
 /*
@@ -1245,7 +1289,7 @@ static int nandc_param(struct qcom_nand_host *host)
 	nandc->buf_count = 512;
 	memset(nandc->data_buffer, 0xff, nandc->buf_count);
 
-	config_nand_single_cw_page_read(chip, false);
+	config_nand_single_cw_page_read(chip, false, 0);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
 		      nandc->buf_count, 0);
@@ -1522,7 +1566,7 @@ static void qcom_nandc_command(struct nand_chip *chip, unsigned int command,
 
 		host->use_ecc = true;
 		set_address(host, 0, page_addr);
-		update_rw_regs(host, ecc->steps, true);
+		update_rw_regs(host, ecc->steps, true, 0);
 		break;
 
 	case NAND_CMD_SEQIN:
@@ -1646,7 +1690,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 
 	clear_bam_transaction(nandc);
 	set_address(host, host->cw_size * cw, page);
-	update_rw_regs(host, 1, true);
+	update_rw_regs(host, 1, true, cw);
 	config_nand_page_read(chip);
 
 	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
@@ -1675,7 +1719,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
 	}
 
-	config_nand_cw_read(chip, false);
+	config_nand_cw_read(chip, false, cw);
 
 	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 	reg_off += data_size1;
@@ -1914,7 +1958,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 			}
 		}
 
-		config_nand_cw_read(chip, true);
+		config_nand_cw_read(chip, true, i);
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
@@ -1974,9 +2018,9 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
 	memset(nandc->data_buffer, 0xff, size);
 
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
-	update_rw_regs(host, 1, true);
+	update_rw_regs(host, 1, true, ecc->steps - 1);
 
-	config_nand_single_cw_page_read(chip, host->use_ecc);
+	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
 
@@ -2041,7 +2085,7 @@ static int qcom_nandc_read_oob(struct nand_chip *chip, int page)
 
 	host->use_ecc = true;
 	set_address(host, 0, page);
-	update_rw_regs(host, ecc->steps, true);
+	update_rw_regs(host, ecc->steps, true, 0);
 
 	return read_page_ecc(host, NULL, chip->oob_poi, page);
 }
@@ -2065,7 +2109,7 @@ static int qcom_nandc_write_page(struct nand_chip *chip, const uint8_t *buf,
 	oob_buf = chip->oob_poi;
 
 	host->use_ecc = true;
-	update_rw_regs(host, ecc->steps, false);
+	update_rw_regs(host, ecc->steps, false, 0);
 	config_nand_page_write(chip);
 
 	for (i = 0; i < ecc->steps; i++) {
@@ -2136,7 +2180,7 @@ static int qcom_nandc_write_page_raw(struct nand_chip *chip,
 	oob_buf = chip->oob_poi;
 
 	host->use_ecc = false;
-	update_rw_regs(host, ecc->steps, false);
+	update_rw_regs(host, ecc->steps, false, 0);
 	config_nand_page_write(chip);
 
 	for (i = 0; i < ecc->steps; i++) {
@@ -2219,7 +2263,7 @@ static int qcom_nandc_write_oob(struct nand_chip *chip, int page)
 				    0, mtd->oobavail);
 
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
-	update_rw_regs(host, 1, false);
+	update_rw_regs(host, 1, false, 0);
 
 	config_nand_page_write(chip);
 	write_data_dma(nandc, FLASH_BUF_ACC,
@@ -2298,7 +2342,7 @@ static int qcom_nandc_block_markbad(struct nand_chip *chip, loff_t ofs)
 	/* prepare write */
 	host->use_ecc = false;
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
-	update_rw_regs(host, 1, false);
+	update_rw_regs(host, 1, false, ecc->steps - 1);
 
 	config_nand_page_write(chip);
 	write_data_dma(nandc, FLASH_BUF_ACC,
-- 
2.7.4

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021
01:34:27 +0530:

> From QPIC version 2.0 onwards new register got added to read last

                               a new

> codeword. This change will add the READ_LOCATION_LAST_CW_n register.

            Add support for this READ_LOCATION_LAST_CW_n register.

> 
> For first three code word READ_LOCATION_n register will be
> use.For last code word READ_LOCATION_LAST_CW_n register will be
> use.

"
In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
READ_LOCATION_n, while codeword 3 will be accessed through
READ_LOCATION_LAST_CW_n.
"

When I read my own sentence, I feel that there is something wrong.
If there are only 4 codewords, I guess a QPIC v2 is able to use
READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?

I guess the point of having these "last_cw_n" registers is to support
up to 8 codewords, am I wrong? If this the case, the current patch
completely fails doing that I don't get the point of such change.

> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> ---

[...]

>  /* helper to configure address register values */
> @@ -700,8 +727,9 @@ static void set_address(struct qcom_nand_host *host, u16 column, int page)
>   *
>   * @num_cw:		number of steps for the read/write operation
>   * @read:		read or write operation
> + * @cw	:		which code word
>   */
> -static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
> +static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read, int cw)
>  {
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> @@ -740,7 +768,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
>  	if (read)
> -		nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
> +		nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
>  				   host->cw_data : host->cw_size, 1);
>  }
>  
> @@ -1111,18 +1139,34 @@ static void config_nand_page_read(struct nand_chip *chip)
>  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>  }
>  
> +/* helper to check which location register should be use for this

    /*
     * Check which location...

> + * code word. NAND_READ_LOCATION or NAND_READ_LOCATION_LAST_CW
> + */
> +static bool config_loc_last_reg(struct nand_chip *chip, int cw)
> +{
> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
> +
> +	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
> +		return true;

Not sure this is really useful, it's probably better to drop this
helper and just use...

> +
> +	return false;
> +}
>  /*
>   * Helper to prepare DMA descriptors for configuring registers
>   * before reading each codeword in NAND page.
>   */
>  static void
> -config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>  {
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +	int reg = NAND_READ_LOCATION_0;
> +
> +	if (config_loc_last_reg(chip, cw))

...     if (nandc->props->qpic_v2 && qcom_nandc_is_lastcw()) here.

> +		reg = NAND_READ_LOCATION_LAST_CW_0;
>  
>  	if (nandc->props->is_bam)
> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> -			      NAND_BAM_NEXT_SGL);
> +		write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
>  
>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> @@ -1142,12 +1186,12 @@ config_nand_cw_read(struct nand_chip *chip, bool use_ecc)

Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-23 22:04, Miquel Raynal wrote:
> Hello,
> 
> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021
> 01:34:27 +0530:
> 
>> From QPIC version 2.0 onwards new register got added to read last
> 
>                                a new
> 
>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.
> 
>             Add support for this READ_LOCATION_LAST_CW_n register.
> 
>> 
>> For first three code word READ_LOCATION_n register will be
>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>> use.
> 
> "
> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
> READ_LOCATION_n, while codeword 3 will be accessed through
> READ_LOCATION_LAST_CW_n.
> "
> 
> When I read my own sentence, I feel that there is something wrong.
> If there are only 4 codewords, I guess a QPIC v2 is able to use
> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?
> 
> I guess the point of having these "last_cw_n" registers is to support
> up to 8 codewords, am I wrong? If this the case, the current patch
> completely fails doing that I don't get the point of such change.

This register is only use to read last code word.

I have address all the comments from all the previous sub sequent 
patches and pushed
all patches in only one series.

Please check.

> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
> 
> [...]
> 
>>  /* helper to configure address register values */
>> @@ -700,8 +727,9 @@ static void set_address(struct qcom_nand_host 
>> *host, u16 column, int page)
>>   *
>>   * @num_cw:		number of steps for the read/write operation
>>   * @read:		read or write operation
>> + * @cw	:		which code word
>>   */
>> -static void update_rw_regs(struct qcom_nand_host *host, int num_cw, 
>> bool read)
>> +static void update_rw_regs(struct qcom_nand_host *host, int num_cw, 
>> bool read, int cw)
>>  {
>>  	struct nand_chip *chip = &host->chip;
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> @@ -740,7 +768,7 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>>  	if (read)
>> -		nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
>> +		nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
>>  				   host->cw_data : host->cw_size, 1);
>>  }
>> 
>> @@ -1111,18 +1139,34 @@ static void config_nand_page_read(struct 
>> nand_chip *chip)
>>  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>>  }
>> 
>> +/* helper to check which location register should be use for this
> 
>     /*
>      * Check which location...
> 
>> + * code word. NAND_READ_LOCATION or NAND_READ_LOCATION_LAST_CW
>> + */
>> +static bool config_loc_last_reg(struct nand_chip *chip, int cw)
>> +{
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>> +
>> +	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
>> +		return true;
> 
> Not sure this is really useful, it's probably better to drop this
> helper and just use...
> 
>> +
>> +	return false;
>> +}
>>  /*
>>   * Helper to prepare DMA descriptors for configuring registers
>>   * before reading each codeword in NAND page.
>>   */
>>  static void
>> -config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
>> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>>  {
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	int reg = NAND_READ_LOCATION_0;
>> +
>> +	if (config_loc_last_reg(chip, cw))
> 
> ...     if (nandc->props->qpic_v2 && qcom_nandc_is_lastcw()) here.
> 
>> +		reg = NAND_READ_LOCATION_LAST_CW_0;
>> 
>>  	if (nandc->props->is_bam)
>> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> -			      NAND_BAM_NEXT_SGL);
>> +		write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
>> 
>>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> @@ -1142,12 +1186,12 @@ config_nand_cw_read(struct nand_chip *chip, 
>> bool use_ecc)
> 
> Thanks,
> Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-24 01:13, mdalam@codeaurora.org wrote:
> On 2021-02-23 22:04, Miquel Raynal wrote:
>> Hello,
>> 
>> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021
>> 01:34:27 +0530:
>> 
>>> From QPIC version 2.0 onwards new register got added to read last
>> 
>>                                a new
>> 
>>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.
>> 
>>             Add support for this READ_LOCATION_LAST_CW_n register.
>> 
>>> 
>>> For first three code word READ_LOCATION_n register will be
>>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>>> use.
>> 
>> "
>> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
>> READ_LOCATION_n, while codeword 3 will be accessed through
>> READ_LOCATION_LAST_CW_n.
>> "
>> 
>> When I read my own sentence, I feel that there is something wrong.
>> If there are only 4 codewords, I guess a QPIC v2 is able to use
>> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?
>> 
>> I guess the point of having these "last_cw_n" registers is to support
>> up to 8 codewords, am I wrong? If this the case, the current patch
>> completely fails doing that I don't get the point of such change.
> 
> This register is only use to read last code word.
> 
> I have address all the comments from all the previous sub sequent
> patches and pushed
> all patches in only one series.
> 
> Please check.

  The registers READ_LOCATION & READ_LOCATION_LAST are not associated 
with number of code words.
  These two registers are used to access the location inside a code word. 
So whether we are having 4 code words
  or 8 code words it doesn't matter. If we wanted access the location 
within normal code word we have to
  use READ_LOCATION register and if we wanted to access location in last 
code word then we have to use
  READ_LOCATION_LAST.
> 
>> 
>>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>>> ---
>> 
>> [...]
>> 
>>>  /* helper to configure address register values */
>>> @@ -700,8 +727,9 @@ static void set_address(struct qcom_nand_host 
>>> *host, u16 column, int page)
>>>   *
>>>   * @num_cw:		number of steps for the read/write operation
>>>   * @read:		read or write operation
>>> + * @cw	:		which code word
>>>   */
>>> -static void update_rw_regs(struct qcom_nand_host *host, int num_cw, 
>>> bool read)
>>> +static void update_rw_regs(struct qcom_nand_host *host, int num_cw, 
>>> bool read, int cw)
>>>  {
>>>  	struct nand_chip *chip = &host->chip;
>>>  	struct qcom_nand_controller *nandc = 
>>> get_qcom_nand_controller(chip);
>>> @@ -740,7 +768,7 @@ static void update_rw_regs(struct qcom_nand_host 
>>> *host, int num_cw, bool read)
>>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>>> 
>>>  	if (read)
>>> -		nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
>>> +		nandc_set_read_loc(chip, cw, 0, 0, host->use_ecc ?
>>>  				   host->cw_data : host->cw_size, 1);
>>>  }
>>> 
>>> @@ -1111,18 +1139,34 @@ static void config_nand_page_read(struct 
>>> nand_chip *chip)
>>>  		      NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
>>>  }
>>> 
>>> +/* helper to check which location register should be use for this
>> 
>>     /*
>>      * Check which location...
>> 
>>> + * code word. NAND_READ_LOCATION or NAND_READ_LOCATION_LAST_CW
>>> + */
>>> +static bool config_loc_last_reg(struct nand_chip *chip, int cw)
>>> +{
>>> +	struct qcom_nand_controller *nandc = 
>>> get_qcom_nand_controller(chip);
>>> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>>> +
>>> +	if (nandc->props->qpic_v2 && qcom_nandc_is_last_cw(ecc, cw))
>>> +		return true;
>> 
>> Not sure this is really useful, it's probably better to drop this
>> helper and just use...
>> 
>>> +
>>> +	return false;
>>> +}
>>>  /*
>>>   * Helper to prepare DMA descriptors for configuring registers
>>>   * before reading each codeword in NAND page.
>>>   */
>>>  static void
>>> -config_nand_cw_read(struct nand_chip *chip, bool use_ecc)
>>> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>>>  {
>>>  	struct qcom_nand_controller *nandc = 
>>> get_qcom_nand_controller(chip);
>>> +	int reg = NAND_READ_LOCATION_0;
>>> +
>>> +	if (config_loc_last_reg(chip, cw))
>> 
>> ...     if (nandc->props->qpic_v2 && qcom_nandc_is_lastcw()) here.
>> 
>>> +		reg = NAND_READ_LOCATION_LAST_CW_0;
>>> 
>>>  	if (nandc->props->is_bam)
>>> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>>> -			      NAND_BAM_NEXT_SGL);
>>> +		write_reg_dma(nandc, reg, 4, NAND_BAM_NEXT_SGL);
>>> 
>>>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>>> @@ -1142,12 +1186,12 @@ config_nand_cw_read(struct nand_chip *chip, 
>>> bool use_ecc)
>> 
>> Thanks,
>> Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 10:09:48 +0530:

> On 2021-02-24 01:13, mdalam@codeaurora.org wrote:
> > On 2021-02-23 22:04, Miquel Raynal wrote:  
> >> Hello,  
> >> >> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021  
> >> 01:34:27 +0530:  
> >> >>> From QPIC version 2.0 onwards new register got added to read last  
> >> >>                                a new  
> >> >>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.  
> >> >>             Add support for this READ_LOCATION_LAST_CW_n register.  
> >> >>> >>> For first three code word READ_LOCATION_n register will be  
> >>> use.For last code word READ_LOCATION_LAST_CW_n register will be
> >>> use.  
> >> >> "  
> >> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
> >> READ_LOCATION_n, while codeword 3 will be accessed through
> >> READ_LOCATION_LAST_CW_n.
> >> "  
> >> >> When I read my own sentence, I feel that there is something wrong.  
> >> If there are only 4 codewords, I guess a QPIC v2 is able to use
> >> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?  
> >> >> I guess the point of having these "last_cw_n" registers is to support  
> >> up to 8 codewords, am I wrong? If this the case, the current patch
> >> completely fails doing that I don't get the point of such change.  
> > 
> > This register is only use to read last code word.
> > 
> > I have address all the comments from all the previous sub sequent
> > patches and pushed
> > all patches in only one series.
> > 
> > Please check.  
> 
>   The registers READ_LOCATION & READ_LOCATION_LAST are not associated with number of code words.
>   These two registers are used to access the location inside a code word.

Ok. Can you please explain what is a location then? Or point me to a
datasheet that explains it.

Bottom line question: why having READ_LOCATION_0, _1,... an
READ_LOCATION_LAST_0, _1, etc?

> So whether we are having 4 code words
>   or 8 code words it doesn't matter. If we wanted access the location within normal code word we have to
>   use READ_LOCATION register and if we wanted to access location in last code word then we have to use
>   READ_LOCATION_LAST.
> >   
> >> >>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>  

Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-24 12:18, Miquel Raynal wrote:
> Hello,
> 
> mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 10:09:48 +0530:
> 
>> On 2021-02-24 01:13, mdalam@codeaurora.org wrote:
>> > On 2021-02-23 22:04, Miquel Raynal wrote:
>> >> Hello,
>> >> >> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021
>> >> 01:34:27 +0530:
>> >> >>> From QPIC version 2.0 onwards new register got added to read last
>> >> >>                                a new
>> >> >>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.
>> >> >>             Add support for this READ_LOCATION_LAST_CW_n register.
>> >> >>> >>> For first three code word READ_LOCATION_n register will be
>> >>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>> >>> use.
>> >> >> "
>> >> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
>> >> READ_LOCATION_n, while codeword 3 will be accessed through
>> >> READ_LOCATION_LAST_CW_n.
>> >> "
>> >> >> When I read my own sentence, I feel that there is something wrong.
>> >> If there are only 4 codewords, I guess a QPIC v2 is able to use
>> >> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?
>> >> >> I guess the point of having these "last_cw_n" registers is to support
>> >> up to 8 codewords, am I wrong? If this the case, the current patch
>> >> completely fails doing that I don't get the point of such change.
>> >
>> > This register is only use to read last code word.
>> >
>> > I have address all the comments from all the previous sub sequent
>> > patches and pushed
>> > all patches in only one series.
>> >
>> > Please check.
>> 
>>   The registers READ_LOCATION & READ_LOCATION_LAST are not associated 
>> with number of code words.
>>   These two registers are used to access the location inside a code 
>> word.
> 
> Ok. Can you please explain what is a location then? Or point me to a
> datasheet that explains it.

   The location is the position inside a code word.

> 
> Bottom line question: why having READ_LOCATION_0, _1,... an
> READ_LOCATION_LAST_0, _1, etc?

  READ_LOCATION_0, _1,... are used to extract multiple chunks from a code 
word.

  e.g If we wanted to extract first 100 bytes from a code word then 
(0...99) READ_LOCATION_0 will be configured.
      if we wanted to extract next 100 bytes (100...199) then 
READ_LOCATION_1 will be configured.

      same way for last code word READ_LOCATION_LAST_0, _1, will be used.


   Below is the mapping example for a 2K page size.

  
<---------------------2048------------------------------------------------><------64---------->2111
  
_______________________________________________________________________________________________
|                                                                        
   |   |               |
|                                                                        
   |   |               |
|                                                                        
   |   |               |
|                                                                        
   |   |               |
|__________________________________________________________________________|___|_______________|
                                                                          
       2048-bytes
                                                                          
       factory BBM


One code word:

              1-byte BBM       7-bytes ECC
______________________________________
|            |  |            |   |    |
|            |  |            |   |    |
|            |  |            |   |    |
|            |  |            |   |    |
|            |  |            |   |    |
|____________|__|____________|___|____|
  <-----------512 bytes------->    4-bytes spare
              data


  
<-------------------------------------2048-------------------------------------------------->2047<------64---------->2111
  
____________________________________________________________________________________________________________________
|                                                                        
                      |   |             |    |
|                                                                        
                      |   |             |    |
|                                                                        
                      |   |             |    |
|                                                                        
                      |   |             |    |
|_____________________________________________________________________________________________|___|_____________|____|
                                                                          
                             |   |
                                                                          
                             |   |
                                                                          
                             |   |<-----mapping
                                                                          
                             |   |
                                                                          
                             |   |
  
____________________________________________________________________________________________________|___|______
|                      |                           |                     
           |                            |
|                      |                           |                     
           |                            |
|                      |                           |                     
           |                            |
|                      |                           |                     
           |                            |
|                      |                           |                     
           |                            |
|______________________|___________________________|_______________________________|____________________________|
<-------CW1-----------><----------CW2-------------><-----------CW3----------------><----------CW4--------------->
                      /                             \
                     /                                \
                   /                                     \
                 /                                         \
               /                                             \
              /                                                 \
            /                                                      \
          /                                                            \
         
_________________________________________________________________ \___
        |                                                                 
     |
        |                                                                 
     |
        |                                                                 
     |
        |                                                                 
     |
        |                                                                 
     |
        |                                                                 
     |
        |<--read_location_0-->   <---read_location_1-->  
<--read_location_n-->|                                                   
               |
        
|_____________________________________________________________________|



So in QPIC V2 onwards to access last code word same way we have to use 
read_location_last_0,1,2..3 etc.


> 
>> So whether we are having 4 code words
>>   or 8 code words it doesn't matter. If we wanted access the location 
>> within normal code word we have to
>>   use READ_LOCATION register and if we wanted to access location in 
>> last code word then we have to use
>>   READ_LOCATION_LAST.
>> >
>> >> >>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> 
> Thanks,
> Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 22:00:05 +0530:

> On 2021-02-24 12:18, Miquel Raynal wrote:
> > Hello,
> > 
> > mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 10:09:48 +0530:
> >   
> >> On 2021-02-24 01:13, mdalam@codeaurora.org wrote:  
> >> > On 2021-02-23 22:04, Miquel Raynal wrote:  
> >> >> Hello,  
> >> >> >> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021  
> >> >> 01:34:27 +0530:  
> >> >> >>> From QPIC version 2.0 onwards new register got added to read last  
> >> >> >>                                a new  
> >> >> >>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.  
> >> >> >>             Add support for this READ_LOCATION_LAST_CW_n register.  
> >> >> >>> >>> For first three code word READ_LOCATION_n register will be  
> >> >>> use.For last code word READ_LOCATION_LAST_CW_n register will be
> >> >>> use.  
> >> >> >> "  
> >> >> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
> >> >> READ_LOCATION_n, while codeword 3 will be accessed through
> >> >> READ_LOCATION_LAST_CW_n.
> >> >> "  
> >> >> >> When I read my own sentence, I feel that there is something wrong.  
> >> >> If there are only 4 codewords, I guess a QPIC v2 is able to use
> >> >> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?  
> >> >> >> I guess the point of having these "last_cw_n" registers is to support  
> >> >> up to 8 codewords, am I wrong? If this the case, the current patch
> >> >> completely fails doing that I don't get the point of such change.  
> >> >
> >> > This register is only use to read last code word.
> >> >
> >> > I have address all the comments from all the previous sub sequent
> >> > patches and pushed
> >> > all patches in only one series.
> >> >
> >> > Please check.  
> >> >>   The registers READ_LOCATION & READ_LOCATION_LAST are not associated >> with number of code words.  
> >>   These two registers are used to access the location inside a code >> word.  
> > 
> > Ok. Can you please explain what is a location then? Or point me to a
> > datasheet that explains it.  
> 
>    The location is the position inside a code word.
> 
> > 
> > Bottom line question: why having READ_LOCATION_0, _1,... an
> > READ_LOCATION_LAST_0, _1, etc?  
> 
>   READ_LOCATION_0, _1,... are used to extract multiple chunks from a code word.
> 
>   e.g If we wanted to extract first 100 bytes from a code word then (0...99) READ_LOCATION_0 will be configured.
>       if we wanted to extract next 100 bytes (100...199) then READ_LOCATION_1 will be configured.
> 
>       same way for last code word READ_LOCATION_LAST_0, _1, will be used.
> 

Nice explanation, and thanks for the below figures. So I guess there is some kind of "small SRAM" that is
directly addressable perhaps?

I think I'm fine with your series now. Just a small nit: next time you send a series, please update the version number "[PATCH v6]" (automatically added with the -v6 parameter in git-format-patch). But no need to resend just for that.


Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-24 22:06, Miquel Raynal wrote:
> Hello,
> 
> mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 22:00:05 +0530:
> 
>> On 2021-02-24 12:18, Miquel Raynal wrote:
>> > Hello,
>> >
>> > mdalam@codeaurora.org wrote on Wed, 24 Feb 2021 10:09:48 +0530:
>> >
>> >> On 2021-02-24 01:13, mdalam@codeaurora.org wrote:
>> >> > On 2021-02-23 22:04, Miquel Raynal wrote:
>> >> >> Hello,
>> >> >> >> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 23 Feb 2021
>> >> >> 01:34:27 +0530:
>> >> >> >>> From QPIC version 2.0 onwards new register got added to read last
>> >> >> >>                                a new
>> >> >> >>> codeword. This change will add the READ_LOCATION_LAST_CW_n register.
>> >> >> >>             Add support for this READ_LOCATION_LAST_CW_n register.
>> >> >> >>> >>> For first three code word READ_LOCATION_n register will be
>> >> >>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>> >> >>> use.
>> >> >> >> "
>> >> >> In the case of QPIC v2, codewords 0, 1 and 2 will be accessed through
>> >> >> READ_LOCATION_n, while codeword 3 will be accessed through
>> >> >> READ_LOCATION_LAST_CW_n.
>> >> >> "
>> >> >> >> When I read my own sentence, I feel that there is something wrong.
>> >> >> If there are only 4 codewords, I guess a QPIC v2 is able to use
>> >> >> READ_LOCATION_3 or READ_LOCATION_LAST_CW_0 interchangeably. Isn't it?
>> >> >> >> I guess the point of having these "last_cw_n" registers is to support
>> >> >> up to 8 codewords, am I wrong? If this the case, the current patch
>> >> >> completely fails doing that I don't get the point of such change.
>> >> >
>> >> > This register is only use to read last code word.
>> >> >
>> >> > I have address all the comments from all the previous sub sequent
>> >> > patches and pushed
>> >> > all patches in only one series.
>> >> >
>> >> > Please check.
>> >> >>   The registers READ_LOCATION & READ_LOCATION_LAST are not associated >> with number of code words.
>> >>   These two registers are used to access the location inside a code >> word.
>> >
>> > Ok. Can you please explain what is a location then? Or point me to a
>> > datasheet that explains it.
>> 
>>    The location is the position inside a code word.
>> 
>> >
>> > Bottom line question: why having READ_LOCATION_0, _1,... an
>> > READ_LOCATION_LAST_0, _1, etc?
>> 
>>   READ_LOCATION_0, _1,... are used to extract multiple chunks from a 
>> code word.
>> 
>>   e.g If we wanted to extract first 100 bytes from a code word then 
>> (0...99) READ_LOCATION_0 will be configured.
>>       if we wanted to extract next 100 bytes (100...199) then 
>> READ_LOCATION_1 will be configured.
>> 
>>       same way for last code word READ_LOCATION_LAST_0, _1, will be 
>> used.
>> 
> 
> Nice explanation, and thanks for the below figures. So I guess there
> is some kind of "small SRAM" that is
> directly addressable perhaps?
> 
> I think I'm fine with your series now. Just a small nit: next time you
> send a series, please update the version number "[PATCH v6]"
> (automatically added with the -v6 parameter in git-format-patch). But
> no need to resend just for that.
> 

   Thanks Miquel. So now no need to test these patches further. I have 
already tested these patches on IPQ5018 SoC with mtd_test module & 
nand-utils tool.

> 
> Thanks,
> Miquèl

[PATCH] mtd: rawnand: qcom: update last code word register

[Md Sadre Alam]

From QPIC version 2.0 onwards new register got added to
read last codeword. This change will add the READ_LOCATION_LAST_CW_n
register.

For first three code word READ_LOCATION_n register will be
use.For last code word READ_LOCATION_LAST_CW_n register will be
use.

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
[V6]
 * Updated write_reg_dma() function in "v6"
 * Removed extra indentation level in read_page_ecc() to read last code word in "v6"
 * Removed boolean check in config_nand_cw_read() in "v6"
 drivers/mtd/nand/raw/qcom_nandc.c | 118 ++++++++++++++++++++++++++++----------
 1 file changed, 87 insertions(+), 31 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 667e4bf..bae352f 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -48,6 +48,10 @@
 #define	NAND_READ_LOCATION_1		0xf24
 #define	NAND_READ_LOCATION_2		0xf28
 #define	NAND_READ_LOCATION_3		0xf2c
+#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
+#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
+#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
+#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c
 
 /* dummy register offsets, used by write_reg_dma */
 #define	NAND_DEV_CMD1_RESTORE		0xdead
@@ -181,8 +185,14 @@
 #define	ECC_BCH_4BIT	BIT(2)
 #define	ECC_BCH_8BIT	BIT(3)
 
-#define nandc_set_read_loc(nandc, reg, offset, size, is_last)	\
-nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
+#define nandc_set_read_loc_first(nandc, reg, offset, size, is_last)	\
+nandc_set_reg(nandc, reg,					\
+	      ((offset) << READ_LOCATION_OFFSET) |		\
+	      ((size) << READ_LOCATION_SIZE) |			\
+	      ((is_last) << READ_LOCATION_LAST))
+
+#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
+nandc_set_reg(nandc, reg,					\
 	      ((offset) << READ_LOCATION_OFFSET) |		\
 	      ((size) << READ_LOCATION_SIZE) |			\
 	      ((is_last) << READ_LOCATION_LAST))
@@ -316,6 +326,10 @@ struct nandc_regs {
 	__le32 read_location1;
 	__le32 read_location2;
 	__le32 read_location3;
+	__le32 read_location_last0;
+	__le32 read_location_last1;
+	__le32 read_location_last2;
+	__le32 read_location_last3;
 
 	__le32 erased_cw_detect_cfg_clr;
 	__le32 erased_cw_detect_cfg_set;
@@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 		return &regs->read_location2;
 	case NAND_READ_LOCATION_3:
 		return &regs->read_location3;
+	case NAND_READ_LOCATION_LAST_CW_0:
+		return &regs->read_location_last0;
+	case NAND_READ_LOCATION_LAST_CW_1:
+		return &regs->read_location_last1;
+	case NAND_READ_LOCATION_LAST_CW_2:
+		return &regs->read_location_last2;
+	case NAND_READ_LOCATION_LAST_CW_3:
+		return &regs->read_location_last3;
 	default:
 		return NULL;
 	}
@@ -661,6 +683,26 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
 		*reg = cpu_to_le32(val);
 }
 
+/* helper to configure location register values */
+static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
+			       int offset, int size, int is_last)
+{
+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	int loc = NAND_READ_LOCATION_0;
+
+	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+		loc = NAND_READ_LOCATION_LAST_CW_0;
+
+	loc += reg * 4;
+
+	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+		return nandc_set_read_loc_last(nandc, loc, offset, size, is_last);
+	else
+		return nandc_set_read_loc_first(nandc, loc, offset, size, is_last);
+}
+
 /* helper to configure address register values */
 static void set_address(struct qcom_nand_host *host, u16 column, int page)
 {
@@ -685,6 +727,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 {
 	struct nand_chip *chip = &host->chip;
 	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
 	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
 
 	if (read) {
@@ -719,9 +762,14 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
-	if (read)
-		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
-				   host->cw_data : host->cw_size, 1);
+	if (read) {
+		if (nandc->props->qpic_v2)
+			nandc_set_read_loc(chip, ecc->steps - 1, 0, 0, host->use_ecc ?
+					host->cw_data : host->cw_size, 1);
+		else
+			nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
+					host->cw_data : host->cw_size, 1);
+	}
 }
 
 /*
@@ -1079,8 +1127,10 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
  * Helper to prepare DMA descriptors for configuring registers
  * before reading a NAND page.
  */
-static void config_nand_page_read(struct qcom_nand_controller *nandc)
+static void config_nand_page_read(struct nand_chip *chip)
 {
+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+
 	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
 	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
 	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
@@ -1094,11 +1144,19 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
  * before reading each codeword in NAND page.
  */
 static void
-config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
+config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
 {
-	if (nandc->props->is_bam)
-		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
-			      NAND_BAM_NEXT_SGL);
+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	if (nandc->props->is_bam) {
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
+				      NAND_BAM_NEXT_SGL);
+		else
+			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
+				      NAND_BAM_NEXT_SGL);
+	}
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -1117,11 +1175,11 @@ config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
  * single codeword in page
  */
 static void
-config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
-				bool use_ecc)
+config_nand_single_cw_page_read(struct nand_chip *chip,
+				bool use_ecc, int cw)
 {
-	config_nand_page_read(nandc);
-	config_nand_cw_read(nandc, use_ecc);
+	config_nand_page_read(chip);
+	config_nand_cw_read(chip, use_ecc, cw);
 }
 
 /*
@@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host *host)
 		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
 	}
 
-	nandc_set_read_loc(nandc, 0, 0, 512, 1);
+	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
 
 	if (!nandc->props->qpic_v2) {
 		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
@@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host *host)
 	nandc->buf_count = 512;
 	memset(nandc->data_buffer, 0xff, nandc->buf_count);
 
-	config_nand_single_cw_page_read(nandc, false);
+	config_nand_single_cw_page_read(chip, false, 0);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
 		      nandc->buf_count, 0);
@@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 	clear_bam_transaction(nandc);
 	set_address(host, host->cw_size * cw, page);
 	update_rw_regs(host, 1, true);
-	config_nand_page_read(nandc);
+	config_nand_page_read(chip);
 
 	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
 	oob_size1 = host->bbm_size;
@@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 	}
 
 	if (nandc->props->is_bam) {
-		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
+		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
 		read_loc += data_size1;
 
-		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
+		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
 		read_loc += oob_size1;
 
-		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
+		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
 		read_loc += data_size2;
 
-		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
+		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
 	}
 
-	config_nand_cw_read(nandc, false);
+	config_nand_cw_read(chip, false, cw);
 
 	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 	reg_off += data_size1;
@@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
 	int i, ret;
 
-	config_nand_page_read(nandc);
+	config_nand_page_read(chip);
 
 	/* queue cmd descs for each codeword */
 	for (i = 0; i < ecc->steps; i++) {
@@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 
 		if (nandc->props->is_bam) {
 			if (data_buf && oob_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
-				nandc_set_read_loc(nandc, 1, data_size,
-						   oob_size, 1);
+				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
+				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
 			} else if (data_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
+				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
 			} else {
-				nandc_set_read_loc(nandc, 0, data_size,
-						   oob_size, 1);
+				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
 			}
 		}
 
-		config_nand_cw_read(nandc, true);
+		config_nand_cw_read(chip, true, i);
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
@@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
 	update_rw_regs(host, 1, true);
 
-	config_nand_single_cw_page_read(nandc, host->use_ecc);
+	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
 
-- 
2.7.4

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 16 Feb 2021
00:46:42 +0530:

> From QPIC version 2.0 onwards new register got added to
> read last codeword. This change will add the READ_LOCATION_LAST_CW_n
> register.
> 
> For first three code word READ_LOCATION_n register will be
> use.For last code word READ_LOCATION_LAST_CW_n register will be
> use.
> 
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> ---
> [V6]

It is also very important that you mark the version in the subject:

	[PATCH v6] mtd: rawnand: etc

Otherwise it is difficult to keep track on the changes.

>  * Updated write_reg_dma() function in "v6"
>  * Removed extra indentation level in read_page_ecc() to read last code word in "v6"
>  * Removed boolean check in config_nand_cw_read() in "v6"
>  drivers/mtd/nand/raw/qcom_nandc.c | 118 ++++++++++++++++++++++++++++----------
>  1 file changed, 87 insertions(+), 31 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index 667e4bf..bae352f 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -48,6 +48,10 @@
>  #define	NAND_READ_LOCATION_1		0xf24
>  #define	NAND_READ_LOCATION_2		0xf28
>  #define	NAND_READ_LOCATION_3		0xf2c
> +#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
> +#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
> +#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
> +#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c
>  
>  /* dummy register offsets, used by write_reg_dma */
>  #define	NAND_DEV_CMD1_RESTORE		0xdead
> @@ -181,8 +185,14 @@
>  #define	ECC_BCH_4BIT	BIT(2)
>  #define	ECC_BCH_8BIT	BIT(3)
>  
> -#define nandc_set_read_loc(nandc, reg, offset, size, is_last)	\
> -nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
> +#define nandc_set_read_loc_first(nandc, reg, offset, size, is_last)	\
> +nandc_set_reg(nandc, reg,					\
> +	      ((offset) << READ_LOCATION_OFFSET) |		\
> +	      ((size) << READ_LOCATION_SIZE) |			\
> +	      ((is_last) << READ_LOCATION_LAST))
> +
> +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
> +nandc_set_reg(nandc, reg,					\
>  	      ((offset) << READ_LOCATION_OFFSET) |		\
>  	      ((size) << READ_LOCATION_SIZE) |			\
>  	      ((is_last) << READ_LOCATION_LAST))
> @@ -316,6 +326,10 @@ struct nandc_regs {
>  	__le32 read_location1;
>  	__le32 read_location2;
>  	__le32 read_location3;
> +	__le32 read_location_last0;
> +	__le32 read_location_last1;
> +	__le32 read_location_last2;
> +	__le32 read_location_last3;
>  
>  	__le32 erased_cw_detect_cfg_clr;
>  	__le32 erased_cw_detect_cfg_set;
> @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>  		return &regs->read_location2;
>  	case NAND_READ_LOCATION_3:
>  		return &regs->read_location3;
> +	case NAND_READ_LOCATION_LAST_CW_0:
> +		return &regs->read_location_last0;
> +	case NAND_READ_LOCATION_LAST_CW_1:
> +		return &regs->read_location_last1;
> +	case NAND_READ_LOCATION_LAST_CW_2:
> +		return &regs->read_location_last2;
> +	case NAND_READ_LOCATION_LAST_CW_3:
> +		return &regs->read_location_last3;
>  	default:
>  		return NULL;
>  	}
> @@ -661,6 +683,26 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
>  		*reg = cpu_to_le32(val);
>  }
>  
> +/* helper to configure location register values */
> +static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
> +			       int offset, int size, int is_last)

You know cw, you have access to chip->ecc.steps, so you can derive by
yourself if is_last is set or not. No need to forward it through
function calls.

> +{
> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
> +
> +	int loc = NAND_READ_LOCATION_0;
> +
> +	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +		loc = NAND_READ_LOCATION_LAST_CW_0;
> +
> +	loc += reg * 4;
> +
> +	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))

Just compute is_last a single time at the top of the helper and use it.

> +		return nandc_set_read_loc_last(nandc, loc, offset, size, is_last);
> +	else
> +		return nandc_set_read_loc_first(nandc, loc, offset, size, is_last);
> +}
> +
>  /* helper to configure address register values */
>  static void set_address(struct qcom_nand_host *host, u16 column, int page)
>  {
> @@ -685,6 +727,7 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>  {
>  	struct nand_chip *chip = &host->chip;
>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>  	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>  
>  	if (read) {
> @@ -719,9 +762,14 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> -	if (read)
> -		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
> -				   host->cw_data : host->cw_size, 1);
> +	if (read) {
> +		if (nandc->props->qpic_v2)
> +			nandc_set_read_loc(chip, ecc->steps - 1, 0, 0, host->use_ecc ?
> +					host->cw_data : host->cw_size, 1);
> +		else
> +			nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
> +					host->cw_data : host->cw_size, 1);

Here you should not have this extra indentation level as well,
nandc_set_read_log() should IMHO be able to hide the complexity of the
versions.

> +	}
>  }
>  
>  /*
> @@ -1079,8 +1127,10 @@ static int write_data_dma(struct qcom_nand_controller *nandc, int reg_off,
>   * Helper to prepare DMA descriptors for configuring registers
>   * before reading a NAND page.
>   */
> -static void config_nand_page_read(struct qcom_nand_controller *nandc)
> +static void config_nand_page_read(struct nand_chip *chip)
>  {
> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +

I don't get why you change the parameter from nandc to chip. Honnestly
I don't think it is a bad thing, I'm just curious to understand why. If
you want to do that, please start with a first patch just doing the
conversion, and then a second patch adding LAST_CW support. Otherwise
it is blurry.

>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>  	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
> @@ -1094,11 +1144,19 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
>   * before reading each codeword in NAND page.
>   */
>  static void
> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>  {
> -	if (nandc->props->is_bam)
> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> -			      NAND_BAM_NEXT_SGL);
> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
> +
> +	if (nandc->props->is_bam) {
> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
> +				      NAND_BAM_NEXT_SGL);
> +		else
> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> +				      NAND_BAM_NEXT_SGL);
> +	}

Same here, I am pretty sure we can abstract the complexity.

>  
>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> @@ -1117,11 +1175,11 @@ config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>   * single codeword in page
>   */
>  static void
> -config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
> -				bool use_ecc)
> +config_nand_single_cw_page_read(struct nand_chip *chip,
> +				bool use_ecc, int cw)
>  {
> -	config_nand_page_read(nandc);
> -	config_nand_cw_read(nandc, use_ecc);
> +	config_nand_page_read(chip);
> +	config_nand_cw_read(chip, use_ecc, cw);
>  }
>  
>  /*
> @@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host *host)
>  		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>  	}
>  
> -	nandc_set_read_loc(nandc, 0, 0, 512, 1);
> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
>  
>  	if (!nandc->props->qpic_v2) {
>  		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> @@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host *host)
>  	nandc->buf_count = 512;
>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);
>  
> -	config_nand_single_cw_page_read(nandc, false);
> +	config_nand_single_cw_page_read(chip, false, 0);
>  
>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
>  		      nandc->buf_count, 0);
> @@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
>  	clear_bam_transaction(nandc);
>  	set_address(host, host->cw_size * cw, page);
>  	update_rw_regs(host, 1, true);
> -	config_nand_page_read(nandc);
> +	config_nand_page_read(chip);
>  
>  	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
>  	oob_size1 = host->bbm_size;
> @@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
>  	}
>  
>  	if (nandc->props->is_bam) {
> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> +		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
>  		read_loc += data_size1;
>  
> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
> +		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
>  		read_loc += oob_size1;
>  
> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
> +		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
>  		read_loc += data_size2;
>  
> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> +		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
>  	}
>  
> -	config_nand_cw_read(nandc, false);
> +	config_nand_cw_read(chip, false, cw);
>  
>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>  	reg_off += data_size1;
> @@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
>  	int i, ret;
>  
> -	config_nand_page_read(nandc);
> +	config_nand_page_read(chip);
>  
>  	/* queue cmd descs for each codeword */
>  	for (i = 0; i < ecc->steps; i++) {
> @@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  
>  		if (nandc->props->is_bam) {
>  			if (data_buf && oob_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> -				nandc_set_read_loc(nandc, 1, data_size,
> -						   oob_size, 1);
> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
> +				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
>  			} else if (data_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>  			} else {
> -				nandc_set_read_loc(nandc, 0, data_size,
> -						   oob_size, 1);
> +				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
>  			}
>  		}
>  
> -		config_nand_cw_read(nandc, true);
> +		config_nand_cw_read(chip, true, i);
>  
>  		if (data_buf)
>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> @@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>  	update_rw_regs(host, 1, true);
>  
> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
> +	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 1);
>  
>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>  

Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-16 13:46, Miquel Raynal wrote:
> Hello,
> 
> Md Sadre Alam <mdalam@codeaurora.org> wrote on Tue, 16 Feb 2021
> 00:46:42 +0530:
> 
>> From QPIC version 2.0 onwards new register got added to
>> read last codeword. This change will add the READ_LOCATION_LAST_CW_n
>> register.
>> 
>> For first three code word READ_LOCATION_n register will be
>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>> use.
>> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
>> [V6]
> 
> It is also very important that you mark the version in the subject:
> 
> 	[PATCH v6] mtd: rawnand: etc
> 
> Otherwise it is difficult to keep track on the changes.

   Sure I will follow the same.
> 
>>  * Updated write_reg_dma() function in "v6"
>>  * Removed extra indentation level in read_page_ecc() to read last 
>> code word in "v6"
>>  * Removed boolean check in config_nand_cw_read() in "v6"
>>  drivers/mtd/nand/raw/qcom_nandc.c | 118 
>> ++++++++++++++++++++++++++++----------
>>  1 file changed, 87 insertions(+), 31 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c 
>> b/drivers/mtd/nand/raw/qcom_nandc.c
>> index 667e4bf..bae352f 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -48,6 +48,10 @@
>>  #define	NAND_READ_LOCATION_1		0xf24
>>  #define	NAND_READ_LOCATION_2		0xf28
>>  #define	NAND_READ_LOCATION_3		0xf2c
>> +#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
>> +#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
>> +#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
>> +#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c
>> 
>>  /* dummy register offsets, used by write_reg_dma */
>>  #define	NAND_DEV_CMD1_RESTORE		0xdead
>> @@ -181,8 +185,14 @@
>>  #define	ECC_BCH_4BIT	BIT(2)
>>  #define	ECC_BCH_8BIT	BIT(3)
>> 
>> -#define nandc_set_read_loc(nandc, reg, offset, size, is_last)	\
>> -nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
>> +#define nandc_set_read_loc_first(nandc, reg, offset, size, is_last)	\
>> +nandc_set_reg(nandc, reg,					\
>> +	      ((offset) << READ_LOCATION_OFFSET) |		\
>> +	      ((size) << READ_LOCATION_SIZE) |			\
>> +	      ((is_last) << READ_LOCATION_LAST))
>> +
>> +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
>> +nandc_set_reg(nandc, reg,					\
>>  	      ((offset) << READ_LOCATION_OFFSET) |		\
>>  	      ((size) << READ_LOCATION_SIZE) |			\
>>  	      ((is_last) << READ_LOCATION_LAST))
>> @@ -316,6 +326,10 @@ struct nandc_regs {
>>  	__le32 read_location1;
>>  	__le32 read_location2;
>>  	__le32 read_location3;
>> +	__le32 read_location_last0;
>> +	__le32 read_location_last1;
>> +	__le32 read_location_last2;
>> +	__le32 read_location_last3;
>> 
>>  	__le32 erased_cw_detect_cfg_clr;
>>  	__le32 erased_cw_detect_cfg_set;
>> @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct 
>> nandc_regs *regs, int offset)
>>  		return &regs->read_location2;
>>  	case NAND_READ_LOCATION_3:
>>  		return &regs->read_location3;
>> +	case NAND_READ_LOCATION_LAST_CW_0:
>> +		return &regs->read_location_last0;
>> +	case NAND_READ_LOCATION_LAST_CW_1:
>> +		return &regs->read_location_last1;
>> +	case NAND_READ_LOCATION_LAST_CW_2:
>> +		return &regs->read_location_last2;
>> +	case NAND_READ_LOCATION_LAST_CW_3:
>> +		return &regs->read_location_last3;
>>  	default:
>>  		return NULL;
>>  	}
>> @@ -661,6 +683,26 @@ static void nandc_set_reg(struct 
>> qcom_nand_controller *nandc, int offset,
>>  		*reg = cpu_to_le32(val);
>>  }
>> 
>> +/* helper to configure location register values */
>> +static void nandc_set_read_loc(struct nand_chip *chip, int cw, int 
>> reg,
>> +			       int offset, int size, int is_last)
> 
> You know cw, you have access to chip->ecc.steps, so you can derive by
> yourself if is_last is set or not. No need to forward it through
> function calls.


   This "is_last" is not for last code word, it will indicate the 
Location register "NAND_READ_LOCATION_n" last bit.

   bit[31]: Indicate this is the last Read location needing processing.

> 
>> +{
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>> +
>> +	int loc = NAND_READ_LOCATION_0;
>> +
>> +	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +		loc = NAND_READ_LOCATION_LAST_CW_0;
>> +
>> +	loc += reg * 4;
>> +
>> +	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> 
> Just compute is_last a single time at the top of the helper and use it.

    This "is_last" is not for last code word, it will indicate the 
Location register last bit.

    bit[31]: Indicate this is the last Read location needing processing.
> 
>> +		return nandc_set_read_loc_last(nandc, loc, offset, size, is_last);
>> +	else
>> +		return nandc_set_read_loc_first(nandc, loc, offset, size, is_last);
>> +}
>> +
>>  /* helper to configure address register values */
>>  static void set_address(struct qcom_nand_host *host, u16 column, int 
>> page)
>>  {
>> @@ -685,6 +727,7 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>  {
>>  	struct nand_chip *chip = &host->chip;
>>  	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>>  	u32 cmd, cfg0, cfg1, ecc_bch_cfg;
>> 
>>  	if (read) {
>> @@ -719,9 +762,14 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>> -	if (read)
>> -		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
>> -				   host->cw_data : host->cw_size, 1);
>> +	if (read) {
>> +		if (nandc->props->qpic_v2)
>> +			nandc_set_read_loc(chip, ecc->steps - 1, 0, 0, host->use_ecc ?
>> +					host->cw_data : host->cw_size, 1);
>> +		else
>> +			nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
>> +					host->cw_data : host->cw_size, 1);
> 
> Here you should not have this extra indentation level as well,
> nandc_set_read_log() should IMHO be able to hide the complexity of the
> versions.

    Yes , this one I will fix in next patch.
> 
>> +	}
>>  }
>> 
>>  /*
>> @@ -1079,8 +1127,10 @@ static int write_data_dma(struct 
>> qcom_nand_controller *nandc, int reg_off,
>>   * Helper to prepare DMA descriptors for configuring registers
>>   * before reading a NAND page.
>>   */
>> -static void config_nand_page_read(struct qcom_nand_controller *nandc)
>> +static void config_nand_page_read(struct nand_chip *chip)
>>  {
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +
> 
> I don't get why you change the parameter from nandc to chip. Honnestly
> I don't think it is a bad thing, I'm just curious to understand why. If
> you want to do that, please start with a first patch just doing the
> conversion, and then a second patch adding LAST_CW support. Otherwise
> it is blurry.

   Yes, here its not needed to change nandc to chip, i will revert this 
in next patch.
> 
>>  	write_reg_dma(nandc, NAND_ADDR0, 2, 0);
>>  	write_reg_dma(nandc, NAND_DEV0_CFG0, 3, 0);
>>  	write_reg_dma(nandc, NAND_EBI2_ECC_BUF_CFG, 1, 0);
>> @@ -1094,11 +1144,19 @@ static void config_nand_page_read(struct 
>> qcom_nand_controller *nandc)
>>   * before reading each codeword in NAND page.
>>   */
>>  static void
>> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>>  {
>> -	if (nandc->props->is_bam)
>> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> -			      NAND_BAM_NEXT_SGL);
>> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>> +
>> +	if (nandc->props->is_bam) {
>> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
>> +				      NAND_BAM_NEXT_SGL);
>> +		else
>> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> +				      NAND_BAM_NEXT_SGL);
>> +	}
> 
> Same here, I am pretty sure we can abstract the complexity.
> 
    Here I did this because , i need pointer to struct nand_ecc_ctrl 
structure
    to access ecc->steps for CW comparison for last code word. cw == 
(ecc->steps - 1)

    So i think no separate patch needed for conversion of nanc-->chip.
    Please let me know if still separate patch needed for nanc-->chip 
conversion.

>> 
>>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> @@ -1117,11 +1175,11 @@ config_nand_cw_read(struct 
>> qcom_nand_controller *nandc, bool use_ecc)
>>   * single codeword in page
>>   */
>>  static void
>> -config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
>> -				bool use_ecc)
>> +config_nand_single_cw_page_read(struct nand_chip *chip,
>> +				bool use_ecc, int cw)
>>  {
>> -	config_nand_page_read(nandc);
>> -	config_nand_cw_read(nandc, use_ecc);
>> +	config_nand_page_read(chip);
>> +	config_nand_cw_read(chip, use_ecc, cw);
>>  }
>> 
>>  /*
>> @@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>  		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>>  	}
>> 
>> -	nandc_set_read_loc(nandc, 0, 0, 512, 1);
>> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
>> 
>>  	if (!nandc->props->qpic_v2) {
>>  		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>> @@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host 
>> *host)
>>  	nandc->buf_count = 512;
>>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);
>> 
>> -	config_nand_single_cw_page_read(nandc, false);
>> +	config_nand_single_cw_page_read(chip, false, 0);
>> 
>>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
>>  		      nandc->buf_count, 0);
>> @@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, 
>> struct nand_chip *chip,
>>  	clear_bam_transaction(nandc);
>>  	set_address(host, host->cw_size * cw, page);
>>  	update_rw_regs(host, 1, true);
>> -	config_nand_page_read(nandc);
>> +	config_nand_page_read(chip);
>> 
>>  	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
>>  	oob_size1 = host->bbm_size;
>> @@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, 
>> struct nand_chip *chip,
>>  	}
>> 
>>  	if (nandc->props->is_bam) {
>> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>> +		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
>>  		read_loc += data_size1;
>> 
>> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>> +		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
>>  		read_loc += oob_size1;
>> 
>> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>> +		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
>>  		read_loc += data_size2;
>> 
>> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> +		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
>>  	}
>> 
>> -	config_nand_cw_read(nandc, false);
>> +	config_nand_cw_read(chip, false, cw);
>> 
>>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>>  	reg_off += data_size1;
>> @@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>>  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
>>  	int i, ret;
>> 
>> -	config_nand_page_read(nandc);
>> +	config_nand_page_read(chip);
>> 
>>  	/* queue cmd descs for each codeword */
>>  	for (i = 0; i < ecc->steps; i++) {
>> @@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>> 
>>  		if (nandc->props->is_bam) {
>>  			if (data_buf && oob_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> -				nandc_set_read_loc(nandc, 1, data_size,
>> -						   oob_size, 1);
>> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
>> +				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
>>  			} else if (data_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>>  			} else {
>> -				nandc_set_read_loc(nandc, 0, data_size,
>> -						   oob_size, 1);
>> +				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
>>  			}
>>  		}
>> 
>> -		config_nand_cw_read(nandc, true);
>> +		config_nand_cw_read(chip, true, i);
>> 
>>  		if (data_buf)
>>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>> @@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host 
>> *host, int page)
>>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>>  	update_rw_regs(host, 1, true);
>> 
>> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
>> +	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - 
>> 1);
>> 
>>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>> 
> 
> Thanks,
> Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

> >> >> +/* helper to configure location register values */  
> >> +static void nandc_set_read_loc(struct nand_chip *chip, int cw, int >> reg,
> >> +			       int offset, int size, int is_last)  
> > 
> > You know cw, you have access to chip->ecc.steps, so you can derive by
> > yourself if is_last is set or not. No need to forward it through
> > function calls.  
> 
> 
>    This "is_last" is not for last code word, it will indicate the Location register "NAND_READ_LOCATION_n" last bit.

Ok, I've mixed two things. Let's keep this boolean as it is for now and
just do the minimum changes to support the LOCATION_LAST_cw registers.

Nevertheless, can't you calculate is_last from nandc_set_read_loc() ?

I also think a bit of renaming (in a different patch) would be welcome
to avoid such confusions.

Just to be clear: I think you should take a step back, and try to
simplify a bit this driver. I understand you know every character by
heart but with an external eye it's not that easy to understand what
you want to do and why:
- write small commits with a single, atomic change
- try to reduce the number of parameters when it is possible
- try to use meaningful names (is_last vs. LAST_CW)
- try to avoid extra indentation level when possible


[...]

> >> @@ -1094,11 +1144,19 @@ static void
config_nand_page_read(struct
>> qcom_nand_controller *nandc)
> >>   * before reading each codeword in NAND page.
> >>   */
> >>  static void
> >> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
> >> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
> >>  {
> >> -	if (nandc->props->is_bam)
> >> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> >> -			      NAND_BAM_NEXT_SGL);
> >> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
> >> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
> >> +
> >> +	if (nandc->props->is_bam) {
> >> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
> >> +				      NAND_BAM_NEXT_SGL);
> >> +		else
> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> >> +				      NAND_BAM_NEXT_SGL);
> >> +	}  
> > 
> > Same here, I am pretty sure we can abstract the complexity.
> >   
>     Here I did this because , i need pointer to struct nand_ecc_ctrl structure
>     to access ecc->steps for CW comparison for last code word. cw == (ecc->steps - 1)
> 
>     So i think no separate patch needed for conversion of nanc-->chip.
>     Please let me know if still separate patch needed for nanc-->chip conversion.

I was talking about the extra indentation level.

the "qpic_v2 && cv == ..." condition can be checked by write_reg_dma
directly.

You could even introduce a helper returning the boolean value of which
register should be used.

Regarding the use of nand_chip instead of nandc, if there are too many
changes involved, I prefer a separate patch.

> 
> >> >>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);  
> >>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> >> @@ -1117,11 +1175,11 @@ config_nand_cw_read(struct >> qcom_nand_controller *nandc, bool use_ecc)
> >>   * single codeword in page
> >>   */
> >>  static void
> >> -config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
> >> -				bool use_ecc)
> >> +config_nand_single_cw_page_read(struct nand_chip *chip,
> >> +				bool use_ecc, int cw)
> >>  {
> >> -	config_nand_page_read(nandc);
> >> -	config_nand_cw_read(nandc, use_ecc);
> >> +	config_nand_page_read(chip);
> >> +	config_nand_cw_read(chip, use_ecc, cw);
> >>  }  
> >> >>  /*  
> >> @@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
> >>  		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
> >>  	}  
> >> >> -	nandc_set_read_loc(nandc, 0, 0, 512, 1);  
> >> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);  
> >> >>  	if (!nandc->props->qpic_v2) {  
> >>  		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
> >> @@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
> >>  	nandc->buf_count = 512;
> >>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);  
> >> >> -	config_nand_single_cw_page_read(nandc, false);  
> >> +	config_nand_single_cw_page_read(chip, false, 0);  
> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,  
> >>  		      nandc->buf_count, 0);
> >> @@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
> >>  	clear_bam_transaction(nandc);
> >>  	set_address(host, host->cw_size * cw, page);
> >>  	update_rw_regs(host, 1, true);
> >> -	config_nand_page_read(nandc);
> >> +	config_nand_page_read(chip);  
> >> >>  	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);  
> >>  	oob_size1 = host->bbm_size;
> >> @@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
> >>  	}  
> >> >>  	if (nandc->props->is_bam) {  
> >> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> >> +		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
> >>  		read_loc += data_size1;  
> >> >> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);  
> >> +		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
> >>  		read_loc += oob_size1;  
> >> >> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);  
> >> +		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
> >>  		read_loc += data_size2;  
> >> >> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);  
> >> +		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
> >>  	}  
> >> >> -	config_nand_cw_read(nandc, false);  
> >> +	config_nand_cw_read(chip, false, cw);  
> >> >>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);  
> >>  	reg_off += data_size1;
> >> @@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,
> >>  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
> >>  	int i, ret;  
> >> >> -	config_nand_page_read(nandc);  
> >> +	config_nand_page_read(chip);  
> >> >>  	/* queue cmd descs for each codeword */  
> >>  	for (i = 0; i < ecc->steps; i++) {
> >> @@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,  
> >> >>  		if (nandc->props->is_bam) {  
> >>  			if (data_buf && oob_buf) {
> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> >> -				nandc_set_read_loc(nandc, 1, data_size,
> >> -						   oob_size, 1);
> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
> >> +				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
> >>  			} else if (data_buf) {
> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
> >>  			} else {
> >> -				nandc_set_read_loc(nandc, 0, data_size,
> >> -						   oob_size, 1);
> >> +				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
> >>  			}
> >>  		}  
> >> >> -		config_nand_cw_read(nandc, true);  
> >> +		config_nand_cw_read(chip, true, i);  
> >> >>  		if (data_buf)  
> >>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> >> @@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host >> *host, int page)
> >>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
> >>  	update_rw_regs(host, 1, true);  
> >> >> -	config_nand_single_cw_page_read(nandc, host->use_ecc);  
> >> +	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - >> 1);  
> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
> >> > > Thanks,  
> > Miquèl  

Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-18 14:50, Miquel Raynal wrote:
> Hello,
> 
>> >> >> +/* helper to configure location register values */
>> >> +static void nandc_set_read_loc(struct nand_chip *chip, int cw, int >> reg,
>> >> +			       int offset, int size, int is_last)
>> >
>> > You know cw, you have access to chip->ecc.steps, so you can derive by
>> > yourself if is_last is set or not. No need to forward it through
>> > function calls.
>> 
>> 
>>    This "is_last" is not for last code word, it will indicate the 
>> Location register "NAND_READ_LOCATION_n" last bit.
> 
> Ok, I've mixed two things. Let's keep this boolean as it is for now and
> just do the minimum changes to support the LOCATION_LAST_cw registers.
> 
> Nevertheless, can't you calculate is_last from nandc_set_read_loc() ?
> 
> I also think a bit of renaming (in a different patch) would be welcome
> to avoid such confusions.
> 
> Just to be clear: I think you should take a step back, and try to
> simplify a bit this driver. I understand you know every character by
> heart but with an external eye it's not that easy to understand what
> you want to do and why:
> - write small commits with a single, atomic change
> - try to reduce the number of parameters when it is possible
> - try to use meaningful names (is_last vs. LAST_CW)
> - try to avoid extra indentation level when possible
> 
> 
   Sure , I will try to split these changes in multiple patches
   and re-pushed again.

> [...]
> 
>> >> @@ -1094,11 +1144,19 @@ static void
> config_nand_page_read(struct
>>> qcom_nand_controller *nandc)
>> >>   * before reading each codeword in NAND page.
>> >>   */
>> >>  static void
>> >> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>> >> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>> >>  {
>> >> -	if (nandc->props->is_bam)
>> >> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> >> -			      NAND_BAM_NEXT_SGL);
>> >> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>> >> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>> >> +
>> >> +	if (nandc->props->is_bam) {
>> >> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
>> >> +				      NAND_BAM_NEXT_SGL);
>> >> +		else
>> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> >> +				      NAND_BAM_NEXT_SGL);
>> >> +	}
>> >
>> > Same here, I am pretty sure we can abstract the complexity.
>> >
>>     Here I did this because , i need pointer to struct nand_ecc_ctrl 
>> structure
>>     to access ecc->steps for CW comparison for last code word. cw == 
>> (ecc->steps - 1)
>> 
>>     So i think no separate patch needed for conversion of nanc-->chip.
>>     Please let me know if still separate patch needed for nanc-->chip 
>> conversion.
> 
> I was talking about the extra indentation level.
> 
> the "qpic_v2 && cv == ..." condition can be checked by write_reg_dma
> directly.
> 
> You could even introduce a helper returning the boolean value of which
> register should be used.
> 
> Regarding the use of nand_chip instead of nandc, if there are too many
> changes involved, I prefer a separate patch.

   I will push separate patch for nandc to chip conversion.
> 
>> 
>> >> >>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>> >>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> >> @@ -1117,11 +1175,11 @@ config_nand_cw_read(struct >> qcom_nand_controller *nandc, bool use_ecc)
>> >>   * single codeword in page
>> >>   */
>> >>  static void
>> >> -config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
>> >> -				bool use_ecc)
>> >> +config_nand_single_cw_page_read(struct nand_chip *chip,
>> >> +				bool use_ecc, int cw)
>> >>  {
>> >> -	config_nand_page_read(nandc);
>> >> -	config_nand_cw_read(nandc, use_ecc);
>> >> +	config_nand_page_read(chip);
>> >> +	config_nand_cw_read(chip, use_ecc, cw);
>> >>  }
>> >> >>  /*
>> >> @@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
>> >>  		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>> >>  	}
>> >> >> -	nandc_set_read_loc(nandc, 0, 0, 512, 1);
>> >> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
>> >> >>  	if (!nandc->props->qpic_v2) {
>> >>  		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>> >> @@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
>> >>  	nandc->buf_count = 512;
>> >>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);
>> >> >> -	config_nand_single_cw_page_read(nandc, false);
>> >> +	config_nand_single_cw_page_read(chip, false, 0);
>> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
>> >>  		      nandc->buf_count, 0);
>> >> @@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
>> >>  	clear_bam_transaction(nandc);
>> >>  	set_address(host, host->cw_size * cw, page);
>> >>  	update_rw_regs(host, 1, true);
>> >> -	config_nand_page_read(nandc);
>> >> +	config_nand_page_read(chip);
>> >> >>  	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
>> >>  	oob_size1 = host->bbm_size;
>> >> @@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
>> >>  	}
>> >> >>  	if (nandc->props->is_bam) {
>> >> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>> >> +		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
>> >>  		read_loc += data_size1;
>> >> >> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>> >> +		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
>> >>  		read_loc += oob_size1;
>> >> >> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>> >> +		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
>> >>  		read_loc += data_size2;
>> >> >> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> >> +		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
>> >>  	}
>> >> >> -	config_nand_cw_read(nandc, false);
>> >> +	config_nand_cw_read(chip, false, cw);
>> >> >>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>> >>  	reg_off += data_size1;
>> >> @@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,
>> >>  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
>> >>  	int i, ret;
>> >> >> -	config_nand_page_read(nandc);
>> >> +	config_nand_page_read(chip);
>> >> >>  	/* queue cmd descs for each codeword */
>> >>  	for (i = 0; i < ecc->steps; i++) {
>> >> @@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,
>> >> >>  		if (nandc->props->is_bam) {
>> >>  			if (data_buf && oob_buf) {
>> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> >> -				nandc_set_read_loc(nandc, 1, data_size,
>> >> -						   oob_size, 1);
>> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
>> >> +				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
>> >>  			} else if (data_buf) {
>> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>> >>  			} else {
>> >> -				nandc_set_read_loc(nandc, 0, data_size,
>> >> -						   oob_size, 1);
>> >> +				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
>> >>  			}
>> >>  		}
>> >> >> -		config_nand_cw_read(nandc, true);
>> >> +		config_nand_cw_read(chip, true, i);
>> >> >>  		if (data_buf)
>> >>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>> >> @@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host >> *host, int page)
>> >>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>> >>  	update_rw_regs(host, 1, true);
>> >> >> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
>> >> +	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - >> 1);
>> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>> >> > > Thanks,
>> > Miquèl
> 
> Thanks,
> Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-18 21:59, mdalam@codeaurora.org wrote:
> On 2021-02-18 14:50, Miquel Raynal wrote:
>> Hello,
>> 
>>> >> >> +/* helper to configure location register values */
>>> >> +static void nandc_set_read_loc(struct nand_chip *chip, int cw, int >> reg,
>>> >> +			       int offset, int size, int is_last)
>>> >
>>> > You know cw, you have access to chip->ecc.steps, so you can derive by
>>> > yourself if is_last is set or not. No need to forward it through
>>> > function calls.
>>> 
>>> 
>>>    This "is_last" is not for last code word, it will indicate the 
>>> Location register "NAND_READ_LOCATION_n" last bit.
>> 
>> Ok, I've mixed two things. Let's keep this boolean as it is for now 
>> and
>> just do the minimum changes to support the LOCATION_LAST_cw registers.
>> 
>> Nevertheless, can't you calculate is_last from nandc_set_read_loc() ?
>> 
>> I also think a bit of renaming (in a different patch) would be welcome
>> to avoid such confusions.
>> 
>> Just to be clear: I think you should take a step back, and try to
>> simplify a bit this driver. I understand you know every character by
>> heart but with an external eye it's not that easy to understand what
>> you want to do and why:
>> - write small commits with a single, atomic change
>> - try to reduce the number of parameters when it is possible
>> - try to use meaningful names (is_last vs. LAST_CW)
>> - try to avoid extra indentation level when possible
>> 
>> 
>   Sure , I will try to split these changes in multiple patches
>   and re-pushed again.
> 
>> [...]
>> 
>>> >> @@ -1094,11 +1144,19 @@ static void
>> config_nand_page_read(struct
>>>> qcom_nand_controller *nandc)
>>> >>   * before reading each codeword in NAND page.
>>> >>   */
>>> >>  static void
>>> >> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>>> >> +config_nand_cw_read(struct nand_chip *chip, bool use_ecc, int cw)
>>> >>  {
>>> >> -	if (nandc->props->is_bam)
>>> >> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>>> >> -			      NAND_BAM_NEXT_SGL);
>>> >> +	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
>>> >> +	struct nand_ecc_ctrl *ecc = &chip->ecc;
>>> >> +
>>> >> +	if (nandc->props->is_bam) {
>>> >> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>>> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
>>> >> +				      NAND_BAM_NEXT_SGL);
>>> >> +		else
>>> >> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>>> >> +				      NAND_BAM_NEXT_SGL);
>>> >> +	}
>>> >
>>> > Same here, I am pretty sure we can abstract the complexity.
>>> >
>>>     Here I did this because , i need pointer to struct nand_ecc_ctrl 
>>> structure
>>>     to access ecc->steps for CW comparison for last code word. cw == 
>>> (ecc->steps - 1)
>>> 
>>>     So i think no separate patch needed for conversion of 
>>> nanc-->chip.
>>>     Please let me know if still separate patch needed for nanc-->chip 
>>> conversion.
>> 
>> I was talking about the extra indentation level.
>> 
>> the "qpic_v2 && cv == ..." condition can be checked by write_reg_dma
>> directly.
>> 
>> You could even introduce a helper returning the boolean value of which
>> register should be used.
>> 
>> Regarding the use of nand_chip instead of nandc, if there are too many
>> changes involved, I prefer a separate patch.
> 
>   I will push separate patch for nandc to chip conversion.

     I have pushed separate patch for nandc to chip conversion.
     Please check.

>> 
>>> 
>>> >> >>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>> >>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>>> >> @@ -1117,11 +1175,11 @@ config_nand_cw_read(struct >> qcom_nand_controller *nandc, bool use_ecc)
>>> >>   * single codeword in page
>>> >>   */
>>> >>  static void
>>> >> -config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
>>> >> -				bool use_ecc)
>>> >> +config_nand_single_cw_page_read(struct nand_chip *chip,
>>> >> +				bool use_ecc, int cw)
>>> >>  {
>>> >> -	config_nand_page_read(nandc);
>>> >> -	config_nand_cw_read(nandc, use_ecc);
>>> >> +	config_nand_page_read(chip);
>>> >> +	config_nand_cw_read(chip, use_ecc, cw);
>>> >>  }
>>> >> >>  /*
>>> >> @@ -1205,7 +1263,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
>>> >>  		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
>>> >>  	}
>>> >> >> -	nandc_set_read_loc(nandc, 0, 0, 512, 1);
>>> >> +	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
>>> >> >>  	if (!nandc->props->qpic_v2) {
>>> >>  		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
>>> >> @@ -1215,7 +1273,7 @@ static int nandc_param(struct qcom_nand_host >> *host)
>>> >>  	nandc->buf_count = 512;
>>> >>  	memset(nandc->data_buffer, 0xff, nandc->buf_count);
>>> >> >> -	config_nand_single_cw_page_read(nandc, false);
>>> >> +	config_nand_single_cw_page_read(chip, false, 0);
>>> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
>>> >>  		      nandc->buf_count, 0);
>>> >> @@ -1617,7 +1675,7 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
>>> >>  	clear_bam_transaction(nandc);
>>> >>  	set_address(host, host->cw_size * cw, page);
>>> >>  	update_rw_regs(host, 1, true);
>>> >> -	config_nand_page_read(nandc);
>>> >> +	config_nand_page_read(chip);
>>> >> >>  	data_size1 = mtd->writesize - host->cw_size * (ecc->steps - 1);
>>> >>  	oob_size1 = host->bbm_size;
>>> >> @@ -1633,19 +1691,19 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, >> struct nand_chip *chip,
>>> >>  	}
>>> >> >>  	if (nandc->props->is_bam) {
>>> >> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>>> >> +		nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
>>> >>  		read_loc += data_size1;
>>> >> >> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>>> >> +		nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
>>> >>  		read_loc += oob_size1;
>>> >> >> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>>> >> +		nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
>>> >>  		read_loc += data_size2;
>>> >> >> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>>> >> +		nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
>>> >>  	}
>>> >> >> -	config_nand_cw_read(nandc, false);
>>> >> +	config_nand_cw_read(chip, false, cw);
>>> >> >>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>>> >>  	reg_off += data_size1;
>>> >> @@ -1856,7 +1914,7 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,
>>> >>  	u8 *data_buf_start = data_buf, *oob_buf_start = oob_buf;
>>> >>  	int i, ret;
>>> >> >> -	config_nand_page_read(nandc);
>>> >> +	config_nand_page_read(chip);
>>> >> >>  	/* queue cmd descs for each codeword */
>>> >>  	for (i = 0; i < ecc->steps; i++) {
>>> >> @@ -1873,18 +1931,16 @@ static int read_page_ecc(struct qcom_nand_host >> *host, u8 *data_buf,
>>> >> >>  		if (nandc->props->is_bam) {
>>> >>  			if (data_buf && oob_buf) {
>>> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>>> >> -				nandc_set_read_loc(nandc, 1, data_size,
>>> >> -						   oob_size, 1);
>>> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
>>> >> +				nandc_set_read_loc(chip, i, 1, data_size, oob_size, 1);
>>> >>  			} else if (data_buf) {
>>> >> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>>> >> +				nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>>> >>  			} else {
>>> >> -				nandc_set_read_loc(nandc, 0, data_size,
>>> >> -						   oob_size, 1);
>>> >> +				nandc_set_read_loc(chip, i, 0, data_size, oob_size, 1);
>>> >>  			}
>>> >>  		}
>>> >> >> -		config_nand_cw_read(nandc, true);
>>> >> +		config_nand_cw_read(chip, true, i);
>>> >> >>  		if (data_buf)
>>> >>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>>> >> @@ -1946,7 +2002,7 @@ static int copy_last_cw(struct qcom_nand_host >> *host, int page)
>>> >>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>>> >>  	update_rw_regs(host, 1, true);
>>> >> >> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
>>> >> +	config_nand_single_cw_page_read(chip, host->use_ecc, ecc->steps - >> 1);
>>> >> >>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>>> >> > > Thanks,
>>> > Miquèl
>> 
>> Thanks,
>> Miquèl

[PATCH] mtd: rawnand: qcom: update last code word register

[Md Sadre Alam]

From QPIC version 2.0 onwards new register got added to
read last codeword. This change will add the READ_LOCATION_LAST_CW_n
register.

For first three code word READ_LOCATION_n register will be
use.For last code word READ_LOCATION_LAST_CW_n register will be
use.

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
[V5]
 * Added helper function to update location register value.
 drivers/mtd/nand/raw/qcom_nandc.c | 136 ++++++++++++++++++++++++++++++--------
 1 file changed, 107 insertions(+), 29 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 667e4bf..6d66dd1 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -48,6 +48,10 @@
 #define	NAND_READ_LOCATION_1		0xf24
 #define	NAND_READ_LOCATION_2		0xf28
 #define	NAND_READ_LOCATION_3		0xf2c
+#define	NAND_READ_LOCATION_LAST_CW_0	0xf40
+#define	NAND_READ_LOCATION_LAST_CW_1	0xf44
+#define	NAND_READ_LOCATION_LAST_CW_2	0xf48
+#define	NAND_READ_LOCATION_LAST_CW_3	0xf4c
 
 /* dummy register offsets, used by write_reg_dma */
 #define	NAND_DEV_CMD1_RESTORE		0xdead
@@ -181,8 +185,14 @@
 #define	ECC_BCH_4BIT	BIT(2)
 #define	ECC_BCH_8BIT	BIT(3)
 
-#define nandc_set_read_loc(nandc, reg, offset, size, is_last)	\
-nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
+#define nandc_set_read_loc_first(nandc, reg, offset, size, is_last)	\
+nandc_set_reg(nandc, reg,					\
+	      ((offset) << READ_LOCATION_OFFSET) |		\
+	      ((size) << READ_LOCATION_SIZE) |			\
+	      ((is_last) << READ_LOCATION_LAST))
+
+#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
+nandc_set_reg(nandc, reg,					\
 	      ((offset) << READ_LOCATION_OFFSET) |		\
 	      ((size) << READ_LOCATION_SIZE) |			\
 	      ((is_last) << READ_LOCATION_LAST))
@@ -316,6 +326,10 @@ struct nandc_regs {
 	__le32 read_location1;
 	__le32 read_location2;
 	__le32 read_location3;
+	__le32 read_location_last0;
+	__le32 read_location_last1;
+	__le32 read_location_last2;
+	__le32 read_location_last3;
 
 	__le32 erased_cw_detect_cfg_clr;
 	__le32 erased_cw_detect_cfg_set;
@@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 		return &regs->read_location2;
 	case NAND_READ_LOCATION_3:
 		return &regs->read_location3;
+	case NAND_READ_LOCATION_LAST_CW_0:
+		return &regs->read_location_last0;
+	case NAND_READ_LOCATION_LAST_CW_1:
+		return &regs->read_location_last1;
+	case NAND_READ_LOCATION_LAST_CW_2:
+		return &regs->read_location_last2;
+	case NAND_READ_LOCATION_LAST_CW_3:
+		return &regs->read_location_last3;
 	default:
 		return NULL;
 	}
@@ -661,6 +683,26 @@ static void nandc_set_reg(struct qcom_nand_controller *nandc, int offset,
 		*reg = cpu_to_le32(val);
 }
 
+/* helper to configure location register values */
+static void nandc_set_read_loc(struct nand_chip *chip, int cw, int reg,
+			       int offset, int size, int is_last)
+{
+	struct qcom_nand_controller *nandc = get_qcom_nand_controller(chip);
+	struct nand_ecc_ctrl *ecc = &chip->ecc;
+
+	int loc = NAND_READ_LOCATION_0;
+
+	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+		loc = NAND_READ_LOCATION_LAST_CW_0;
+
+	loc += reg * 4;
+
+	if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+		return nandc_set_read_loc_last(nandc, loc, offset, size, is_last);
+	else
+		return nandc_set_read_loc_first(nandc, loc, offset, size, is_last);
+}
+
 /* helper to configure address register values */
 static void set_address(struct qcom_nand_host *host, u16 column, int page)
 {
@@ -719,9 +761,14 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
-	if (read)
-		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
-				   host->cw_data : host->cw_size, 1);
+	if (read) {
+		if (nandc->props->qpic_v2)
+			nandc_set_read_loc(chip, 3, 0, 0, host->use_ecc ?
+					host->cw_data : host->cw_size, 1);
+		else
+			nandc_set_read_loc(chip, 0, 0, 0, host->use_ecc ?
+					host->cw_data : host->cw_size, 1);
+	}
 }
 
 /*
@@ -1094,11 +1141,16 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
  * before reading each codeword in NAND page.
  */
 static void
-config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
+config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc, bool last_cw)
 {
-	if (nandc->props->is_bam)
-		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
-			      NAND_BAM_NEXT_SGL);
+	if (nandc->props->is_bam) {
+		if (nandc->props->qpic_v2 && last_cw)
+			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
+				      NAND_BAM_NEXT_SGL);
+		else
+			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
+				      NAND_BAM_NEXT_SGL);
+	}
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -1118,10 +1170,10 @@ config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
  */
 static void
 config_nand_single_cw_page_read(struct qcom_nand_controller *nandc,
-				bool use_ecc)
+				bool use_ecc, bool last_cw)
 {
 	config_nand_page_read(nandc);
-	config_nand_cw_read(nandc, use_ecc);
+	config_nand_cw_read(nandc, use_ecc, last_cw);
 }
 
 /*
@@ -1205,7 +1257,7 @@ static int nandc_param(struct qcom_nand_host *host)
 		nandc_set_reg(nandc, NAND_DEV_CMD_VLD_RESTORE, nandc->vld);
 	}
 
-	nandc_set_read_loc(nandc, 0, 0, 512, 1);
+	nandc_set_read_loc(chip, 0, 0, 0, 512, 1);
 
 	if (!nandc->props->qpic_v2) {
 		write_reg_dma(nandc, NAND_DEV_CMD_VLD, 1, 0);
@@ -1215,7 +1267,7 @@ static int nandc_param(struct qcom_nand_host *host)
 	nandc->buf_count = 512;
 	memset(nandc->data_buffer, 0xff, nandc->buf_count);
 
-	config_nand_single_cw_page_read(nandc, false);
+	config_nand_single_cw_page_read(nandc, false, false);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer,
 		      nandc->buf_count, 0);
@@ -1633,19 +1685,32 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 	}
 
 	if (nandc->props->is_bam) {
-		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
-		read_loc += data_size1;
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1)) {
+			nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
+			read_loc += data_size1;
+
+			nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
+			read_loc += oob_size1;
+
+			nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
+			read_loc += data_size2;
 
-		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
-		read_loc += oob_size1;
+			nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
+		} else {
+			nandc_set_read_loc(chip, cw, 0, read_loc, data_size1, 0);
+			read_loc += data_size1;
+
+			nandc_set_read_loc(chip, cw, 1, read_loc, oob_size1, 0);
+			read_loc += oob_size1;
 
-		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
-		read_loc += data_size2;
+			nandc_set_read_loc(chip, cw, 2, read_loc, data_size2, 0);
+			read_loc += data_size2;
 
-		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
+			nandc_set_read_loc(chip, cw, 3, read_loc, oob_size2, 1);
+		}
 	}
 
-	config_nand_cw_read(nandc, false);
+	config_nand_cw_read(nandc, false, cw == ecc->steps - 1 ? true : false);
 
 	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
 	reg_off += data_size1;
@@ -1873,18 +1938,31 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 
 		if (nandc->props->is_bam) {
 			if (data_buf && oob_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
-				nandc_set_read_loc(nandc, 1, data_size,
-						   oob_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
+					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
+					nandc_set_read_loc(chip, i, 1, data_size,
+							   oob_size, 1);
+				} else {
+					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
+					nandc_set_read_loc(chip, i, 1, data_size,
+							   oob_size, 1);
+				}
 			} else if (data_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
+					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
+				else
+					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
 			} else {
-				nandc_set_read_loc(nandc, 0, data_size,
-						   oob_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
+					nandc_set_read_loc(chip, i, 0, data_size,
+							   oob_size, 1);
+				else
+					nandc_set_read_loc(chip, i, 0, data_size,
+							   oob_size, 1);
 			}
 		}
 
-		config_nand_cw_read(nandc, true);
+		config_nand_cw_read(nandc, true, i == ecc->steps - 1 ? true : false);
 
 		if (data_buf)
 			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
@@ -1946,7 +2024,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
 	set_address(host, host->cw_size * (ecc->steps - 1), page);
 	update_rw_regs(host, 1, true);
 
-	config_nand_single_cw_page_read(nandc, host->use_ecc);
+	config_nand_single_cw_page_read(nandc, host->use_ecc, true);
 
 	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
 
-- 
2.7.4

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Miquel Raynal]

Hello,

Md Sadre Alam <mdalam@codeaurora.org> wrote on Mon, 15 Feb 2021
02:47:31 +0530:

> From QPIC version 2.0 onwards new register got added to
> read last codeword. This change will add the READ_LOCATION_LAST_CW_n
> register.
> 
> For first three code word READ_LOCATION_n register will be
> use.For last code word READ_LOCATION_LAST_CW_n register will be
> use.
> 
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> ---
> [V5]
>  * Added helper function to update location register value.


Please don't forget the "v5" in the message object.

>  /*
> @@ -1094,11 +1141,16 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
>   * before reading each codeword in NAND page.
>   */
>  static void
> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
> +config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc, bool last_cw)
>  {
> -	if (nandc->props->is_bam)
> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> -			      NAND_BAM_NEXT_SGL);
> +	if (nandc->props->is_bam) {
> +		if (nandc->props->qpic_v2 && last_cw)
> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
> +				      NAND_BAM_NEXT_SGL);
> +		else
> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> +				      NAND_BAM_NEXT_SGL);

I guess write_reg_dma should be updated as well.


[...]

>  
> -	config_nand_cw_read(nandc, false);
> +	config_nand_cw_read(nandc, false, cw == ecc->steps - 1 ? true : false);
>  
>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>  	reg_off += data_size1;
> @@ -1873,18 +1938,31 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  
>  		if (nandc->props->is_bam) {
>  			if (data_buf && oob_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> -				nandc_set_read_loc(nandc, 1, data_size,
> -						   oob_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {

I would like the helper to handle this condition. I would prefer to
avoid yet an extra indentation level.

> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
> +					nandc_set_read_loc(chip, i, 1, data_size,
> +							   oob_size, 1);
> +				} else {
> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
> +					nandc_set_read_loc(chip, i, 1, data_size,
> +							   oob_size, 1);
> +				}
>  			} else if (data_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
> +				else
> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>  			} else {
> -				nandc_set_read_loc(nandc, 0, data_size,
> -						   oob_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> +					nandc_set_read_loc(chip, i, 0, data_size,
> +							   oob_size, 1);
> +				else
> +					nandc_set_read_loc(chip, i, 0, data_size,
> +							   oob_size, 1);
>  			}
>  		}
>  
> -		config_nand_cw_read(nandc, true);
> +		config_nand_cw_read(nandc, true, i == ecc->steps - 1 ? true : false);

	i == (ecc->steps - 1)

is already a boolean, you don't need

	"? true : false"

>  
>  		if (data_buf)
>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
> @@ -1946,7 +2024,7 @@ static int copy_last_cw(struct qcom_nand_host *host, int page)
>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>  	update_rw_regs(host, 1, true);
>  
> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
> +	config_nand_single_cw_page_read(nandc, host->use_ecc, true);

Maybe it's best to just forward the codeword and let the code that
needs to know if it is the last one or not do the comparison.

>  
>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>  

Thanks,
Miquèl

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-02-15 14:10, Miquel Raynal wrote:
> Hello,
> 
> Md Sadre Alam <mdalam@codeaurora.org> wrote on Mon, 15 Feb 2021
> 02:47:31 +0530:
> 
>> From QPIC version 2.0 onwards new register got added to
>> read last codeword. This change will add the READ_LOCATION_LAST_CW_n
>> register.
>> 
>> For first three code word READ_LOCATION_n register will be
>> use.For last code word READ_LOCATION_LAST_CW_n register will be
>> use.
>> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
>> [V5]
>>  * Added helper function to update location register value.
> 
> 
> Please don't forget the "v5" in the message object.
> 
>>  /*
>> @@ -1094,11 +1141,16 @@ static void config_nand_page_read(struct 
>> qcom_nand_controller *nandc)
>>   * before reading each codeword in NAND page.
>>   */
>>  static void
>> -config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>> +config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc, 
>> bool last_cw)
>>  {
>> -	if (nandc->props->is_bam)
>> -		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> -			      NAND_BAM_NEXT_SGL);
>> +	if (nandc->props->is_bam) {
>> +		if (nandc->props->qpic_v2 && last_cw)
>> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0, 4,
>> +				      NAND_BAM_NEXT_SGL);
>> +		else
>> +			write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> +				      NAND_BAM_NEXT_SGL);
> 
> I guess write_reg_dma should be updated as well.

   Updated in V6 patch , please check.
> 
> 
> [...]
> 
>> 
>> -	config_nand_cw_read(nandc, false);
>> +	config_nand_cw_read(nandc, false, cw == ecc->steps - 1 ? true : 
>> false);
>> 
>>  	read_data_dma(nandc, reg_off, data_buf, data_size1, 0);
>>  	reg_off += data_size1;
>> @@ -1873,18 +1938,31 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>> 
>>  		if (nandc->props->is_bam) {
>>  			if (data_buf && oob_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> -				nandc_set_read_loc(nandc, 1, data_size,
>> -						   oob_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
> 
> I would like the helper to handle this condition. I would prefer to
> avoid yet an extra indentation level.

   Updated in V6 patch , please check.
> 
>> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
>> +					nandc_set_read_loc(chip, i, 1, data_size,
>> +							   oob_size, 1);
>> +				} else {
>> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 0);
>> +					nandc_set_read_loc(chip, i, 1, data_size,
>> +							   oob_size, 1);
>> +				}
>>  			} else if (data_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>> +				else
>> +					nandc_set_read_loc(chip, i, 0, 0, data_size, 1);
>>  			} else {
>> -				nandc_set_read_loc(nandc, 0, data_size,
>> -						   oob_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> +					nandc_set_read_loc(chip, i, 0, data_size,
>> +							   oob_size, 1);
>> +				else
>> +					nandc_set_read_loc(chip, i, 0, data_size,
>> +							   oob_size, 1);
>>  			}
>>  		}
>> 
>> -		config_nand_cw_read(nandc, true);
>> +		config_nand_cw_read(nandc, true, i == ecc->steps - 1 ? true : 
>> false);
> 
> 	i == (ecc->steps - 1)
> 
> is already a boolean, you don't need
> 
> 	"? true : false"
> 

    Updated in V6 patch.

>> 
>>  		if (data_buf)
>>  			read_data_dma(nandc, FLASH_BUF_ACC, data_buf,
>> @@ -1946,7 +2024,7 @@ static int copy_last_cw(struct qcom_nand_host 
>> *host, int page)
>>  	set_address(host, host->cw_size * (ecc->steps - 1), page);
>>  	update_rw_regs(host, 1, true);
>> 
>> -	config_nand_single_cw_page_read(nandc, host->use_ecc);
>> +	config_nand_single_cw_page_read(nandc, host->use_ecc, true);
> 
> Maybe it's best to just forward the codeword and let the code that
> needs to know if it is the last one or not do the comparison.
> 

   Updated in V6 patch, please check.
>> 
>>  	read_data_dma(nandc, FLASH_BUF_ACC, nandc->data_buffer, size, 0);
>> 
> 
> Thanks,
> Miquèl

[PATCH] mtd: rawnand: qcom: update last code word register

[Md Sadre Alam]

From QPIC version 2.0 onwards new register got added to
read last codeword. This change will update the same.

For first three code word READ_LOCATION_n register will be
use.For last code wrod READ_LOCATION_LAST_CW_n register will be
use.

Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
 drivers/mtd/nand/raw/qcom_nandc.c | 79 +++++++++++++++++++++++++++++++++------
 1 file changed, 67 insertions(+), 12 deletions(-)

diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 667e4bf..eaef51d 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -48,6 +48,10 @@
 #define	NAND_READ_LOCATION_1		0xf24
 #define	NAND_READ_LOCATION_2		0xf28
 #define	NAND_READ_LOCATION_3		0xf2c
+#define NAND_READ_LOCATION_LAST_CW_0    0xf40
+#define NAND_READ_LOCATION_LAST_CW_1    0xf44
+#define NAND_READ_LOCATION_LAST_CW_2    0xf48
+#define NAND_READ_LOCATION_LAST_CW_3    0xf4c
 
 /* dummy register offsets, used by write_reg_dma */
 #define	NAND_DEV_CMD1_RESTORE		0xdead
@@ -187,6 +191,12 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
 	      ((size) << READ_LOCATION_SIZE) |			\
 	      ((is_last) << READ_LOCATION_LAST))
 
+#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
+nandc_set_reg(nandc, NAND_READ_LOCATION_LAST_CW_##reg,			\
+	      ((offset) << READ_LOCATION_OFFSET) |		\
+	      ((size) << READ_LOCATION_SIZE) |			\
+	      ((is_last) << READ_LOCATION_LAST))
+
 /*
  * Returns the actual register address for all NAND_DEV_ registers
  * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
@@ -316,6 +326,10 @@ struct nandc_regs {
 	__le32 read_location1;
 	__le32 read_location2;
 	__le32 read_location3;
+	__le32 read_location_last0;
+	__le32 read_location_last1;
+	__le32 read_location_last2;
+	__le32 read_location_last3;
 
 	__le32 erased_cw_detect_cfg_clr;
 	__le32 erased_cw_detect_cfg_set;
@@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
 		return &regs->read_location2;
 	case NAND_READ_LOCATION_3:
 		return &regs->read_location3;
+	case NAND_READ_LOCATION_LAST_CW_0:
+		return &regs->read_location_last0;
+	case NAND_READ_LOCATION_LAST_CW_1:
+		return &regs->read_location_last1;
+	case NAND_READ_LOCATION_LAST_CW_2:
+		return &regs->read_location_last2;
+	case NAND_READ_LOCATION_LAST_CW_3:
+		return &regs->read_location_last3;
 	default:
 		return NULL;
 	}
@@ -719,9 +741,13 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
 	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
 	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
 
-	if (read)
+	if (read) {
+		if (nandc->props->qpic_v2)
+			nandc_set_read_loc_last(nandc, 0, 0, host->use_ecc ?
+					host->cw_data : host->cw_size, 1);
 		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
 				   host->cw_data : host->cw_size, 1);
+	}
 }
 
 /*
@@ -1096,9 +1122,13 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
 static void
 config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
 {
-	if (nandc->props->is_bam)
+	if (nandc->props->is_bam) {
+		if (nandc->props->qpic_v2)
+			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
+				      4, NAND_BAM_NEXT_SGL);
 		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
 			      NAND_BAM_NEXT_SGL);
+	}
 
 	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
 	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
@@ -1633,16 +1663,28 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
 	}
 
 	if (nandc->props->is_bam) {
-		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+			nandc_set_read_loc_last(nandc, 0, read_loc, data_size1, 0);
+		else
+			nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
 		read_loc += data_size1;
 
-		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+			nandc_set_read_loc_last(nandc, 1, read_loc, oob_size1, 0);
+		else
+			nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
 		read_loc += oob_size1;
 
-		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+			nandc_set_read_loc_last(nandc, 2, read_loc, data_size2, 0);
+		else
+			nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
 		read_loc += data_size2;
 
-		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
+		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
+			nandc_set_read_loc_last(nandc, 3, read_loc, oob_size2, 0);
+		else
+			nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
 	}
 
 	config_nand_cw_read(nandc, false);
@@ -1873,14 +1915,27 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
 
 		if (nandc->props->is_bam) {
 			if (data_buf && oob_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
-				nandc_set_read_loc(nandc, 1, data_size,
-						   oob_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
+					nandc_set_read_loc_last(nandc, 0, 0, data_size, 0);
+					nandc_set_read_loc_last(nandc, 1, data_size,
+								oob_size, 1);
+				} else {
+					nandc_set_read_loc(nandc, 0, 0, data_size, 0);
+					nandc_set_read_loc(nandc, 1, data_size,
+							   oob_size, 1);
+				}
 			} else if (data_buf) {
-				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
+					nandc_set_read_loc_last(nandc, 0, 0, data_size, 1);
+				else
+					nandc_set_read_loc(nandc, 0, 0, data_size, 1);
 			} else {
-				nandc_set_read_loc(nandc, 0, data_size,
-						   oob_size, 1);
+				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
+					nandc_set_read_loc_last(nandc, 0, data_size,
+								oob_size, 1);
+				else
+					nandc_set_read_loc(nandc, 0, data_size,
+							   oob_size, 1);
 			}
 		}
 
-- 
2.7.4

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Manivannan Sadhasivam]

On Thu, Dec 17, 2020 at 07:32:56PM +0530, Md Sadre Alam wrote:
> From QPIC version 2.0 onwards new register got added to
> read last codeword. This change will update the same.
> 
> For first three code word READ_LOCATION_n register will be
> use.For last code wrod READ_LOCATION_LAST_CW_n register will be
> use.
> 
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> ---
>  drivers/mtd/nand/raw/qcom_nandc.c | 79 +++++++++++++++++++++++++++++++++------
>  1 file changed, 67 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index 667e4bf..eaef51d 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -48,6 +48,10 @@
>  #define	NAND_READ_LOCATION_1		0xf24
>  #define	NAND_READ_LOCATION_2		0xf28
>  #define	NAND_READ_LOCATION_3		0xf2c
> +#define NAND_READ_LOCATION_LAST_CW_0    0xf40
> +#define NAND_READ_LOCATION_LAST_CW_1    0xf44
> +#define NAND_READ_LOCATION_LAST_CW_2    0xf48
> +#define NAND_READ_LOCATION_LAST_CW_3    0xf4c

Please keep the alignment as before.

>  
>  /* dummy register offsets, used by write_reg_dma */
>  #define	NAND_DEV_CMD1_RESTORE		0xdead
> @@ -187,6 +191,12 @@ nandc_set_reg(nandc, NAND_READ_LOCATION_##reg,			\
>  	      ((size) << READ_LOCATION_SIZE) |			\
>  	      ((is_last) << READ_LOCATION_LAST))
>  
> +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
> +nandc_set_reg(nandc, NAND_READ_LOCATION_LAST_CW_##reg,			\
> +	      ((offset) << READ_LOCATION_OFFSET) |		\
> +	      ((size) << READ_LOCATION_SIZE) |			\
> +	      ((is_last) << READ_LOCATION_LAST))
> +
>  /*
>   * Returns the actual register address for all NAND_DEV_ registers
>   * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and NAND_DEV_CMD_VLD)
> @@ -316,6 +326,10 @@ struct nandc_regs {
>  	__le32 read_location1;
>  	__le32 read_location2;
>  	__le32 read_location3;
> +	__le32 read_location_last0;
> +	__le32 read_location_last1;
> +	__le32 read_location_last2;
> +	__le32 read_location_last3;
>  
>  	__le32 erased_cw_detect_cfg_clr;
>  	__le32 erased_cw_detect_cfg_set;
> @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct nandc_regs *regs, int offset)
>  		return &regs->read_location2;
>  	case NAND_READ_LOCATION_3:
>  		return &regs->read_location3;
> +	case NAND_READ_LOCATION_LAST_CW_0:
> +		return &regs->read_location_last0;
> +	case NAND_READ_LOCATION_LAST_CW_1:
> +		return &regs->read_location_last1;
> +	case NAND_READ_LOCATION_LAST_CW_2:
> +		return &regs->read_location_last2;
> +	case NAND_READ_LOCATION_LAST_CW_3:
> +		return &regs->read_location_last3;
>  	default:
>  		return NULL;
>  	}
> @@ -719,9 +741,13 @@ static void update_rw_regs(struct qcom_nand_host *host, int num_cw, bool read)
>  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>  
> -	if (read)
> +	if (read) {
> +		if (nandc->props->qpic_v2)
> +			nandc_set_read_loc_last(nandc, 0, 0, host->use_ecc ?
> +					host->cw_data : host->cw_size, 1);

Forgot to add else? Otherwise both NAND_READ_LOCATION_n and NAND_READ_LOCATION_LAST_CW_n
will be used.

>  		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
>  				   host->cw_data : host->cw_size, 1);
> +	}
>  }
>  
>  /*
> @@ -1096,9 +1122,13 @@ static void config_nand_page_read(struct qcom_nand_controller *nandc)
>  static void
>  config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>  {
> -	if (nandc->props->is_bam)
> +	if (nandc->props->is_bam) {
> +		if (nandc->props->qpic_v2)
> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
> +				      4, NAND_BAM_NEXT_SGL);
>  		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>  			      NAND_BAM_NEXT_SGL);

Don't you need to modify the number of registers to write? It can't be 4 all the
time if NAND_READ_LOCATION_LAST_CW_0 is used.

> +	}
>  
>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> @@ -1633,16 +1663,28 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, struct nand_chip *chip,
>  	}
>  
>  	if (nandc->props->is_bam) {
> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +			nandc_set_read_loc_last(nandc, 0, read_loc, data_size1, 0);
> +		else
> +			nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);

IIUC nandc_set_read_loc_last() is only needed to read the last codeword which is
handled by the last command in this function:

nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);

>  		read_loc += data_size1;
>  
> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +			nandc_set_read_loc_last(nandc, 1, read_loc, oob_size1, 0);
> +		else
> +			nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>  		read_loc += oob_size1;
>  
> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +			nandc_set_read_loc_last(nandc, 2, read_loc, data_size2, 0);
> +		else
> +			nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>  		read_loc += data_size2;
>  
> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> +			nandc_set_read_loc_last(nandc, 3, read_loc, oob_size2, 0);
> +		else
> +			nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>  	}
>  
>  	config_nand_cw_read(nandc, false);
> @@ -1873,14 +1915,27 @@ static int read_page_ecc(struct qcom_nand_host *host, u8 *data_buf,
>  
>  		if (nandc->props->is_bam) {
>  			if (data_buf && oob_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> -				nandc_set_read_loc(nandc, 1, data_size,
> -						   oob_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
> +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 0);

Why do you need this? Can't you use nandc_set_read_loc()? Same for below cases.

Thanks,
Mani

> +					nandc_set_read_loc_last(nandc, 1, data_size,
> +								oob_size, 1);
> +				} else {
> +					nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> +					nandc_set_read_loc(nandc, 1, data_size,
> +							   oob_size, 1);
> +				}
>  			} else if (data_buf) {
> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 1);
> +				else
> +					nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>  			} else {
> -				nandc_set_read_loc(nandc, 0, data_size,
> -						   oob_size, 1);
> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> +					nandc_set_read_loc_last(nandc, 0, data_size,
> +								oob_size, 1);
> +				else
> +					nandc_set_read_loc(nandc, 0, data_size,
> +							   oob_size, 1);
>  			}
>  		}
>  
> -- 
> 2.7.4
> 

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2020-12-31 16:23, Manivannan Sadhasivam wrote:
> On Thu, Dec 17, 2020 at 07:32:56PM +0530, Md Sadre Alam wrote:
>> From QPIC version 2.0 onwards new register got added to
>> read last codeword. This change will update the same.
>> 
>> For first three code word READ_LOCATION_n register will be
>> use.For last code wrod READ_LOCATION_LAST_CW_n register will be
>> use.
>> 
>> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> ---
>>  drivers/mtd/nand/raw/qcom_nandc.c | 79 
>> +++++++++++++++++++++++++++++++++------
>>  1 file changed, 67 insertions(+), 12 deletions(-)
>> 
>> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c 
>> b/drivers/mtd/nand/raw/qcom_nandc.c
>> index 667e4bf..eaef51d 100644
>> --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> @@ -48,6 +48,10 @@
>>  #define	NAND_READ_LOCATION_1		0xf24
>>  #define	NAND_READ_LOCATION_2		0xf28
>>  #define	NAND_READ_LOCATION_3		0xf2c
>> +#define NAND_READ_LOCATION_LAST_CW_0    0xf40
>> +#define NAND_READ_LOCATION_LAST_CW_1    0xf44
>> +#define NAND_READ_LOCATION_LAST_CW_2    0xf48
>> +#define NAND_READ_LOCATION_LAST_CW_3    0xf4c
> 
> Please keep the alignment as before.
> 
  Fixed alignment in V2 patch
>> 
>>  /* dummy register offsets, used by write_reg_dma */
>>  #define	NAND_DEV_CMD1_RESTORE		0xdead
>> @@ -187,6 +191,12 @@ nandc_set_reg(nandc, 
>> NAND_READ_LOCATION_##reg,			\
>>  	      ((size) << READ_LOCATION_SIZE) |			\
>>  	      ((is_last) << READ_LOCATION_LAST))
>> 
>> +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
>> +nandc_set_reg(nandc, NAND_READ_LOCATION_LAST_CW_##reg,			\
>> +	      ((offset) << READ_LOCATION_OFFSET) |		\
>> +	      ((size) << READ_LOCATION_SIZE) |			\
>> +	      ((is_last) << READ_LOCATION_LAST))
>> +
>>  /*
>>   * Returns the actual register address for all NAND_DEV_ registers
>>   * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and 
>> NAND_DEV_CMD_VLD)
>> @@ -316,6 +326,10 @@ struct nandc_regs {
>>  	__le32 read_location1;
>>  	__le32 read_location2;
>>  	__le32 read_location3;
>> +	__le32 read_location_last0;
>> +	__le32 read_location_last1;
>> +	__le32 read_location_last2;
>> +	__le32 read_location_last3;
>> 
>>  	__le32 erased_cw_detect_cfg_clr;
>>  	__le32 erased_cw_detect_cfg_set;
>> @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct 
>> nandc_regs *regs, int offset)
>>  		return &regs->read_location2;
>>  	case NAND_READ_LOCATION_3:
>>  		return &regs->read_location3;
>> +	case NAND_READ_LOCATION_LAST_CW_0:
>> +		return &regs->read_location_last0;
>> +	case NAND_READ_LOCATION_LAST_CW_1:
>> +		return &regs->read_location_last1;
>> +	case NAND_READ_LOCATION_LAST_CW_2:
>> +		return &regs->read_location_last2;
>> +	case NAND_READ_LOCATION_LAST_CW_3:
>> +		return &regs->read_location_last3;
>>  	default:
>>  		return NULL;
>>  	}
>> @@ -719,9 +741,13 @@ static void update_rw_regs(struct qcom_nand_host 
>> *host, int num_cw, bool read)
>>  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>>  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> 
>> -	if (read)
>> +	if (read) {
>> +		if (nandc->props->qpic_v2)
>> +			nandc_set_read_loc_last(nandc, 0, 0, host->use_ecc ?
>> +					host->cw_data : host->cw_size, 1);
> 
> Forgot to add else? Otherwise both NAND_READ_LOCATION_n and
> NAND_READ_LOCATION_LAST_CW_n
> will be used.

   Here else is not needed , because to read last code word we need to 
configure
   NAND_READ_LOCATION_LAST_CW_n register. Any way here we are doing only 
register configuration.
   for all the code words. Earlier version of QPIC we were using  
nandc_set_read_loc()
   for all the code words, but in qpic V2 onwards for last code word we 
have to use
   NAND_READ_LOCATION_LAST_CW_n register. So configuring here the same.


> 
>>  		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
>>  				   host->cw_data : host->cw_size, 1);
>> +	}
>>  }
>> 
>>  /*
>> @@ -1096,9 +1122,13 @@ static void config_nand_page_read(struct 
>> qcom_nand_controller *nandc)
>>  static void
>>  config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>>  {
>> -	if (nandc->props->is_bam)
>> +	if (nandc->props->is_bam) {
>> +		if (nandc->props->qpic_v2)
>> +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
>> +				      4, NAND_BAM_NEXT_SGL);
>>  		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>>  			      NAND_BAM_NEXT_SGL);
> 
> Don't you need to modify the number of registers to write? It can't be 
> 4 all the
> time if NAND_READ_LOCATION_LAST_CW_0 is used.

   Changed number of registers to write from 4 to 1 in V2 patch for 
register NAND_READ_LOCATION_LAST_CW_0 .
> 
>> +	}
>> 
>>  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> @@ -1633,16 +1663,28 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd, 
>> struct nand_chip *chip,
>>  	}
>> 
>>  	if (nandc->props->is_bam) {
>> -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +			nandc_set_read_loc_last(nandc, 0, read_loc, data_size1, 0);
>> +		else
>> +			nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> 
> IIUC nandc_set_read_loc_last() is only needed to read the last codeword 
> which is
> handled by the last command in this function:

   Function qcom_nandc_read_cw_raw() is getting called for each code word 
for raw read and its reading
   one code word at a time. So to read last code word when condition cw 
== (ecc->steps - 1) will match, we have
   to configure NAND_READ_LOCATION_LAST_CW_n register. Because below 
piece of code is doing one code word
   read for first three code word so same logic will also apply for last 
code word as well.

> 
> nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> 
>>  		read_loc += data_size1;
>> 
>> -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +			nandc_set_read_loc_last(nandc, 1, read_loc, oob_size1, 0);
>> +		else
>> +			nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>>  		read_loc += oob_size1;
>> 
>> -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +			nandc_set_read_loc_last(nandc, 2, read_loc, data_size2, 0);
>> +		else
>> +			nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>>  		read_loc += data_size2;
>> 
>> -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> +			nandc_set_read_loc_last(nandc, 3, read_loc, oob_size2, 0);
>> +		else
>> +			nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>>  	}
>> 
>>  	config_nand_cw_read(nandc, false);
>> @@ -1873,14 +1915,27 @@ static int read_page_ecc(struct qcom_nand_host 
>> *host, u8 *data_buf,
>> 
>>  		if (nandc->props->is_bam) {
>>  			if (data_buf && oob_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> -				nandc_set_read_loc(nandc, 1, data_size,
>> -						   oob_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
>> +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 0);
> 
> Why do you need this? Can't you use nandc_set_read_loc()? Same for 
> below cases.

   Here we are looping for all the code words and when we will do 
configuration for last
   code word we have to use NAND_READ_LOCATION_LAST_CW_n register that's 
why i am using
   nandc_set_read_loc_last() instead of nandc_set_read_loc().
> 
> Thanks,
> Mani
> 
>> +					nandc_set_read_loc_last(nandc, 1, data_size,
>> +								oob_size, 1);
>> +				} else {
>> +					nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> +					nandc_set_read_loc(nandc, 1, data_size,
>> +							   oob_size, 1);
>> +				}
>>  			} else if (data_buf) {
>> -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 1);
>> +				else
>> +					nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>>  			} else {
>> -				nandc_set_read_loc(nandc, 0, data_size,
>> -						   oob_size, 1);
>> +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> +					nandc_set_read_loc_last(nandc, 0, data_size,
>> +								oob_size, 1);
>> +				else
>> +					nandc_set_read_loc(nandc, 0, data_size,
>> +							   oob_size, 1);
>>  			}
>>  		}
>> 
>> --
>> 2.7.4
>> 

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[Manivannan Sadhasivam]

On Tue, Jan 05, 2021 at 12:24:45AM +0530, mdalam@codeaurora.org wrote:
> On 2020-12-31 16:23, Manivannan Sadhasivam wrote:
> > On Thu, Dec 17, 2020 at 07:32:56PM +0530, Md Sadre Alam wrote:
> > > From QPIC version 2.0 onwards new register got added to
> > > read last codeword. This change will update the same.
> > > 
> > > For first three code word READ_LOCATION_n register will be
> > > use.For last code wrod READ_LOCATION_LAST_CW_n register will be
> > > use.
> > > 
> > > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> > > ---
> > >  drivers/mtd/nand/raw/qcom_nandc.c | 79
> > > +++++++++++++++++++++++++++++++++------
> > >  1 file changed, 67 insertions(+), 12 deletions(-)
> > > 
> > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> > > b/drivers/mtd/nand/raw/qcom_nandc.c
> > > index 667e4bf..eaef51d 100644
> > > --- a/drivers/mtd/nand/raw/qcom_nandc.c
> > > +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> > > @@ -48,6 +48,10 @@
> > >  #define	NAND_READ_LOCATION_1		0xf24
> > >  #define	NAND_READ_LOCATION_2		0xf28
> > >  #define	NAND_READ_LOCATION_3		0xf2c
> > > +#define NAND_READ_LOCATION_LAST_CW_0    0xf40
> > > +#define NAND_READ_LOCATION_LAST_CW_1    0xf44
> > > +#define NAND_READ_LOCATION_LAST_CW_2    0xf48
> > > +#define NAND_READ_LOCATION_LAST_CW_3    0xf4c
> > 
> > Please keep the alignment as before.
> > 
>  Fixed alignment in V2 patch
> > > 
> > >  /* dummy register offsets, used by write_reg_dma */
> > >  #define	NAND_DEV_CMD1_RESTORE		0xdead
> > > @@ -187,6 +191,12 @@ nandc_set_reg(nandc,
> > > NAND_READ_LOCATION_##reg,			\
> > >  	      ((size) << READ_LOCATION_SIZE) |			\
> > >  	      ((is_last) << READ_LOCATION_LAST))
> > > 
> > > +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
> > > +nandc_set_reg(nandc, NAND_READ_LOCATION_LAST_CW_##reg,			\
> > > +	      ((offset) << READ_LOCATION_OFFSET) |		\
> > > +	      ((size) << READ_LOCATION_SIZE) |			\
> > > +	      ((is_last) << READ_LOCATION_LAST))
> > > +
> > >  /*
> > >   * Returns the actual register address for all NAND_DEV_ registers
> > >   * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and
> > > NAND_DEV_CMD_VLD)
> > > @@ -316,6 +326,10 @@ struct nandc_regs {
> > >  	__le32 read_location1;
> > >  	__le32 read_location2;
> > >  	__le32 read_location3;
> > > +	__le32 read_location_last0;
> > > +	__le32 read_location_last1;
> > > +	__le32 read_location_last2;
> > > +	__le32 read_location_last3;
> > > 
> > >  	__le32 erased_cw_detect_cfg_clr;
> > >  	__le32 erased_cw_detect_cfg_set;
> > > @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct
> > > nandc_regs *regs, int offset)
> > >  		return &regs->read_location2;
> > >  	case NAND_READ_LOCATION_3:
> > >  		return &regs->read_location3;
> > > +	case NAND_READ_LOCATION_LAST_CW_0:
> > > +		return &regs->read_location_last0;
> > > +	case NAND_READ_LOCATION_LAST_CW_1:
> > > +		return &regs->read_location_last1;
> > > +	case NAND_READ_LOCATION_LAST_CW_2:
> > > +		return &regs->read_location_last2;
> > > +	case NAND_READ_LOCATION_LAST_CW_3:
> > > +		return &regs->read_location_last3;
> > >  	default:
> > >  		return NULL;
> > >  	}
> > > @@ -719,9 +741,13 @@ static void update_rw_regs(struct
> > > qcom_nand_host *host, int num_cw, bool read)
> > >  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
> > >  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
> > > 
> > > -	if (read)
> > > +	if (read) {
> > > +		if (nandc->props->qpic_v2)
> > > +			nandc_set_read_loc_last(nandc, 0, 0, host->use_ecc ?
> > > +					host->cw_data : host->cw_size, 1);
> > 
> > Forgot to add else? Otherwise both NAND_READ_LOCATION_n and
> > NAND_READ_LOCATION_LAST_CW_n
> > will be used.
> 
>   Here else is not needed , because to read last code word we need to
> configure
>   NAND_READ_LOCATION_LAST_CW_n register. Any way here we are doing only
> register configuration.
>   for all the code words. Earlier version of QPIC we were using
> nandc_set_read_loc()
>   for all the code words, but in qpic V2 onwards for last code word we have
> to use
>   NAND_READ_LOCATION_LAST_CW_n register. So configuring here the same.
> 

nandc_set_read_loc() has the last argument "is_last". This is used to convey
whether we need to set READ_LOCATION_LAST bit or not. This is fine for QPIC
IP < 2, but for >=2 we need to use nandc_set_read_loc_last() only. My point
is why do you need to still use nandc_set_read_loc() here for QPIC v2? That's
why I asked you about using else().

> 
> > 
> > >  		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
> > >  				   host->cw_data : host->cw_size, 1);
> > > +	}
> > >  }
> > > 
> > >  /*
> > > @@ -1096,9 +1122,13 @@ static void config_nand_page_read(struct
> > > qcom_nand_controller *nandc)
> > >  static void
> > >  config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
> > >  {
> > > -	if (nandc->props->is_bam)
> > > +	if (nandc->props->is_bam) {
> > > +		if (nandc->props->qpic_v2)
> > > +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
> > > +				      4, NAND_BAM_NEXT_SGL);
> > >  		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
> > >  			      NAND_BAM_NEXT_SGL);
> > 
> > Don't you need to modify the number of registers to write? It can't be 4
> > all the
> > time if NAND_READ_LOCATION_LAST_CW_0 is used.
> 
>   Changed number of registers to write from 4 to 1 in V2 patch for register
> NAND_READ_LOCATION_LAST_CW_0 .
> > 
> > > +	}
> > > 
> > >  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
> > >  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
> > > @@ -1633,16 +1663,28 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd,
> > > struct nand_chip *chip,
> > >  	}
> > > 
> > >  	if (nandc->props->is_bam) {
> > > -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> > > +			nandc_set_read_loc_last(nandc, 0, read_loc, data_size1, 0);
> > > +		else
> > > +			nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
> > 
> > IIUC nandc_set_read_loc_last() is only needed to read the last codeword
> > which is
> > handled by the last command in this function:
> 
>   Function qcom_nandc_read_cw_raw() is getting called for each code word for
> raw read and its reading
>   one code word at a time. So to read last code word when condition cw ==
> (ecc->steps - 1) will match, we have
>   to configure NAND_READ_LOCATION_LAST_CW_n register. Because below piece of
> code is doing one code word
>   read for first three code word so same logic will also apply for last code
> word as well.
> 

Fine, but still "cw == (ecc->steps - 1)" will stay same for all comparisions
in this function, right? So why can't you use it only for the last command?

> > 
> > nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> > 
> > >  		read_loc += data_size1;
> > > 
> > > -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> > > +			nandc_set_read_loc_last(nandc, 1, read_loc, oob_size1, 0);
> > > +		else
> > > +			nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
> > >  		read_loc += oob_size1;
> > > 
> > > -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> > > +			nandc_set_read_loc_last(nandc, 2, read_loc, data_size2, 0);
> > > +		else
> > > +			nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
> > >  		read_loc += data_size2;
> > > 
> > > -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
> > > +			nandc_set_read_loc_last(nandc, 3, read_loc, oob_size2, 0);
> > > +		else
> > > +			nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
> > >  	}
> > > 
> > >  	config_nand_cw_read(nandc, false);
> > > @@ -1873,14 +1915,27 @@ static int read_page_ecc(struct
> > > qcom_nand_host *host, u8 *data_buf,
> > > 
> > >  		if (nandc->props->is_bam) {
> > >  			if (data_buf && oob_buf) {
> > > -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> > > -				nandc_set_read_loc(nandc, 1, data_size,
> > > -						   oob_size, 1);
> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
> > > +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 0);
> > 
> > Why do you need this? Can't you use nandc_set_read_loc()? Same for below
> > cases.
> 
>   Here we are looping for all the code words and when we will do
> configuration for last
>   code word we have to use NAND_READ_LOCATION_LAST_CW_n register that's why
> i am using
>   nandc_set_read_loc_last() instead of nandc_set_read_loc().
> > 

Sorry, confused! You are calling nandc_set_read_loc_last() twice and only the
last one has "is_last" flag set. Can you please clarify?

Thanks,
Mani

> > Thanks,
> > Mani
> > 
> > > +					nandc_set_read_loc_last(nandc, 1, data_size,
> > > +								oob_size, 1);
> > > +				} else {
> > > +					nandc_set_read_loc(nandc, 0, 0, data_size, 0);
> > > +					nandc_set_read_loc(nandc, 1, data_size,
> > > +							   oob_size, 1);
> > > +				}
> > >  			} else if (data_buf) {
> > > -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> > > +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 1);
> > > +				else
> > > +					nandc_set_read_loc(nandc, 0, 0, data_size, 1);
> > >  			} else {
> > > -				nandc_set_read_loc(nandc, 0, data_size,
> > > -						   oob_size, 1);
> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
> > > +					nandc_set_read_loc_last(nandc, 0, data_size,
> > > +								oob_size, 1);
> > > +				else
> > > +					nandc_set_read_loc(nandc, 0, data_size,
> > > +							   oob_size, 1);
> > >  			}
> > >  		}
> > > 
> > > --
> > > 2.7.4
> > > 

Re: [PATCH] mtd: rawnand: qcom: update last code word register

[mdalam]

On 2021-01-05 21:15, Manivannan Sadhasivam wrote:
> On Tue, Jan 05, 2021 at 12:24:45AM +0530, mdalam@codeaurora.org wrote:
>> On 2020-12-31 16:23, Manivannan Sadhasivam wrote:
>> > On Thu, Dec 17, 2020 at 07:32:56PM +0530, Md Sadre Alam wrote:
>> > > From QPIC version 2.0 onwards new register got added to
>> > > read last codeword. This change will update the same.
>> > >
>> > > For first three code word READ_LOCATION_n register will be
>> > > use.For last code wrod READ_LOCATION_LAST_CW_n register will be
>> > > use.
>> > >
>> > > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>> > > ---
>> > >  drivers/mtd/nand/raw/qcom_nandc.c | 79
>> > > +++++++++++++++++++++++++++++++++------
>> > >  1 file changed, 67 insertions(+), 12 deletions(-)
>> > >
>> > > diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
>> > > b/drivers/mtd/nand/raw/qcom_nandc.c
>> > > index 667e4bf..eaef51d 100644
>> > > --- a/drivers/mtd/nand/raw/qcom_nandc.c
>> > > +++ b/drivers/mtd/nand/raw/qcom_nandc.c
>> > > @@ -48,6 +48,10 @@
>> > >  #define	NAND_READ_LOCATION_1		0xf24
>> > >  #define	NAND_READ_LOCATION_2		0xf28
>> > >  #define	NAND_READ_LOCATION_3		0xf2c
>> > > +#define NAND_READ_LOCATION_LAST_CW_0    0xf40
>> > > +#define NAND_READ_LOCATION_LAST_CW_1    0xf44
>> > > +#define NAND_READ_LOCATION_LAST_CW_2    0xf48
>> > > +#define NAND_READ_LOCATION_LAST_CW_3    0xf4c
>> >
>> > Please keep the alignment as before.
>> >
>>  Fixed alignment in V2 patch
>> > >
>> > >  /* dummy register offsets, used by write_reg_dma */
>> > >  #define	NAND_DEV_CMD1_RESTORE		0xdead
>> > > @@ -187,6 +191,12 @@ nandc_set_reg(nandc,
>> > > NAND_READ_LOCATION_##reg,			\
>> > >  	      ((size) << READ_LOCATION_SIZE) |			\
>> > >  	      ((is_last) << READ_LOCATION_LAST))
>> > >
>> > > +#define nandc_set_read_loc_last(nandc, reg, offset, size, is_last)	\
>> > > +nandc_set_reg(nandc, NAND_READ_LOCATION_LAST_CW_##reg,			\
>> > > +	      ((offset) << READ_LOCATION_OFFSET) |		\
>> > > +	      ((size) << READ_LOCATION_SIZE) |			\
>> > > +	      ((is_last) << READ_LOCATION_LAST))
>> > > +
>> > >  /*
>> > >   * Returns the actual register address for all NAND_DEV_ registers
>> > >   * (i.e. NAND_DEV_CMD0, NAND_DEV_CMD1, NAND_DEV_CMD2 and
>> > > NAND_DEV_CMD_VLD)
>> > > @@ -316,6 +326,10 @@ struct nandc_regs {
>> > >  	__le32 read_location1;
>> > >  	__le32 read_location2;
>> > >  	__le32 read_location3;
>> > > +	__le32 read_location_last0;
>> > > +	__le32 read_location_last1;
>> > > +	__le32 read_location_last2;
>> > > +	__le32 read_location_last3;
>> > >
>> > >  	__le32 erased_cw_detect_cfg_clr;
>> > >  	__le32 erased_cw_detect_cfg_set;
>> > > @@ -644,6 +658,14 @@ static __le32 *offset_to_nandc_reg(struct
>> > > nandc_regs *regs, int offset)
>> > >  		return &regs->read_location2;
>> > >  	case NAND_READ_LOCATION_3:
>> > >  		return &regs->read_location3;
>> > > +	case NAND_READ_LOCATION_LAST_CW_0:
>> > > +		return &regs->read_location_last0;
>> > > +	case NAND_READ_LOCATION_LAST_CW_1:
>> > > +		return &regs->read_location_last1;
>> > > +	case NAND_READ_LOCATION_LAST_CW_2:
>> > > +		return &regs->read_location_last2;
>> > > +	case NAND_READ_LOCATION_LAST_CW_3:
>> > > +		return &regs->read_location_last3;
>> > >  	default:
>> > >  		return NULL;
>> > >  	}
>> > > @@ -719,9 +741,13 @@ static void update_rw_regs(struct
>> > > qcom_nand_host *host, int num_cw, bool read)
>> > >  	nandc_set_reg(nandc, NAND_READ_STATUS, host->clrreadstatus);
>> > >  	nandc_set_reg(nandc, NAND_EXEC_CMD, 1);
>> > >
>> > > -	if (read)
>> > > +	if (read) {
>> > > +		if (nandc->props->qpic_v2)
>> > > +			nandc_set_read_loc_last(nandc, 0, 0, host->use_ecc ?
>> > > +					host->cw_data : host->cw_size, 1);
>> >
>> > Forgot to add else? Otherwise both NAND_READ_LOCATION_n and
>> > NAND_READ_LOCATION_LAST_CW_n
>> > will be used.
>> 
>>   Here else is not needed , because to read last code word we need to
>> configure
>>   NAND_READ_LOCATION_LAST_CW_n register. Any way here we are doing 
>> only
>> register configuration.
>>   for all the code words. Earlier version of QPIC we were using
>> nandc_set_read_loc()
>>   for all the code words, but in qpic V2 onwards for last code word we 
>> have
>> to use
>>   NAND_READ_LOCATION_LAST_CW_n register. So configuring here the same.
>> 
> 
> nandc_set_read_loc() has the last argument "is_last". This is used to 
> convey
> whether we need to set READ_LOCATION_LAST bit or not. This is fine for 
> QPIC
> IP < 2, but for >=2 we need to use nandc_set_read_loc_last() only. My 
> point
> is why do you need to still use nandc_set_read_loc() here for QPIC v2? 
> That's
> why I asked you about using else().
> 
   Got it. I fixed this in V3 patch.
>> 
>> >
>> > >  		nandc_set_read_loc(nandc, 0, 0, host->use_ecc ?
>> > >  				   host->cw_data : host->cw_size, 1);
>> > > +	}
>> > >  }
>> > >
>> > >  /*
>> > > @@ -1096,9 +1122,13 @@ static void config_nand_page_read(struct
>> > > qcom_nand_controller *nandc)
>> > >  static void
>> > >  config_nand_cw_read(struct qcom_nand_controller *nandc, bool use_ecc)
>> > >  {
>> > > -	if (nandc->props->is_bam)
>> > > +	if (nandc->props->is_bam) {
>> > > +		if (nandc->props->qpic_v2)
>> > > +			write_reg_dma(nandc, NAND_READ_LOCATION_LAST_CW_0,
>> > > +				      4, NAND_BAM_NEXT_SGL);
>> > >  		write_reg_dma(nandc, NAND_READ_LOCATION_0, 4,
>> > >  			      NAND_BAM_NEXT_SGL);
>> >
>> > Don't you need to modify the number of registers to write? It can't be 4
>> > all the
>> > time if NAND_READ_LOCATION_LAST_CW_0 is used.
>> 
>>   Changed number of registers to write from 4 to 1 in V2 patch for 
>> register
>> NAND_READ_LOCATION_LAST_CW_0 .
>> >
>> > > +	}
>> > >
>> > >  	write_reg_dma(nandc, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>> > >  	write_reg_dma(nandc, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>> > > @@ -1633,16 +1663,28 @@ qcom_nandc_read_cw_raw(struct mtd_info *mtd,
>> > > struct nand_chip *chip,
>> > >  	}
>> > >
>> > >  	if (nandc->props->is_bam) {
>> > > -		nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> > > +			nandc_set_read_loc_last(nandc, 0, read_loc, data_size1, 0);
>> > > +		else
>> > > +			nandc_set_read_loc(nandc, 0, read_loc, data_size1, 0);
>> >
>> > IIUC nandc_set_read_loc_last() is only needed to read the last codeword
>> > which is
>> > handled by the last command in this function:
>> 
>>   Function qcom_nandc_read_cw_raw() is getting called for each code 
>> word for
>> raw read and its reading
>>   one code word at a time. So to read last code word when condition cw 
>> ==
>> (ecc->steps - 1) will match, we have
>>   to configure NAND_READ_LOCATION_LAST_CW_n register. Because below 
>> piece of
>> code is doing one code word
>>   read for first three code word so same logic will also apply for 
>> last code
>> word as well.
>> 
> 
> Fine, but still "cw == (ecc->steps - 1)" will stay same for all 
> comparisions
> in this function, right? So why can't you use it only for the last 
> command?
> 
    Yes I understand, but data_size1, oob_size1, data_size2 and oob_size2 
are the sizes
    to extract these many bytes of data from buff whose offset specified 
by the register
    QPIC_NAND_READ_LOCATION_LAST_CW_n. "read_loc" also changing. 
"is_last" is just a flag
    which indicate this is the last read location to process.For last 
code word also we  are
    updating data_size1, oob_size1, data_size2 and oob_size2 so condition 
should be applied for
    all command not only for last command.
>> >
>> > nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> >
>> > >  		read_loc += data_size1;
>> > >
>> > > -		nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> > > +			nandc_set_read_loc_last(nandc, 1, read_loc, oob_size1, 0);
>> > > +		else
>> > > +			nandc_set_read_loc(nandc, 1, read_loc, oob_size1, 0);
>> > >  		read_loc += oob_size1;
>> > >
>> > > -		nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> > > +			nandc_set_read_loc_last(nandc, 2, read_loc, data_size2, 0);
>> > > +		else
>> > > +			nandc_set_read_loc(nandc, 2, read_loc, data_size2, 0);
>> > >  		read_loc += data_size2;
>> > >
>> > > -		nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> > > +		if (nandc->props->qpic_v2 && cw == (ecc->steps - 1))
>> > > +			nandc_set_read_loc_last(nandc, 3, read_loc, oob_size2, 0);
>> > > +		else
>> > > +			nandc_set_read_loc(nandc, 3, read_loc, oob_size2, 1);
>> > >  	}
>> > >
>> > >  	config_nand_cw_read(nandc, false);
>> > > @@ -1873,14 +1915,27 @@ static int read_page_ecc(struct
>> > > qcom_nand_host *host, u8 *data_buf,
>> > >
>> > >  		if (nandc->props->is_bam) {
>> > >  			if (data_buf && oob_buf) {
>> > > -				nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> > > -				nandc_set_read_loc(nandc, 1, data_size,
>> > > -						   oob_size, 1);
>> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1)) {
>> > > +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 0);
>> >
>> > Why do you need this? Can't you use nandc_set_read_loc()? Same for below
>> > cases.
>> 
>>   Here we are looping for all the code words and when we will do
>> configuration for last
>>   code word we have to use NAND_READ_LOCATION_LAST_CW_n register 
>> that's why
>> i am using
>>   nandc_set_read_loc_last() instead of nandc_set_read_loc().
>> >
> 
> Sorry, confused! You are calling nandc_set_read_loc_last() twice and 
> only the
> last one has "is_last" flag set. Can you please clarify?

   For last code word , in first call of nandc_set_read_loc_last() 
"data_size" bytes will get extracted.
   and in the the second call of nandc_set_read_loc_last() "oob_size" 
bytes will get extracted and this
   is the last read location to process so I am setting "is_last" flag in 
the second call.
> 
> Thanks,
> Mani
> 
>> > Thanks,
>> > Mani
>> >
>> > > +					nandc_set_read_loc_last(nandc, 1, data_size,
>> > > +								oob_size, 1);
>> > > +				} else {
>> > > +					nandc_set_read_loc(nandc, 0, 0, data_size, 0);
>> > > +					nandc_set_read_loc(nandc, 1, data_size,
>> > > +							   oob_size, 1);
>> > > +				}
>> > >  			} else if (data_buf) {
>> > > -				nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> > > +					nandc_set_read_loc_last(nandc, 0, 0, data_size, 1);
>> > > +				else
>> > > +					nandc_set_read_loc(nandc, 0, 0, data_size, 1);
>> > >  			} else {
>> > > -				nandc_set_read_loc(nandc, 0, data_size,
>> > > -						   oob_size, 1);
>> > > +				if (nandc->props->qpic_v2 && i == (ecc->steps - 1))
>> > > +					nandc_set_read_loc_last(nandc, 0, data_size,
>> > > +								oob_size, 1);
>> > > +				else
>> > > +					nandc_set_read_loc(nandc, 0, data_size,
>> > > +							   oob_size, 1);
>> > >  			}
>> > >  		}
>> > >
>> > > --
>> > > 2.7.4
>> > >