* [PATCH v4 0/5] Add Microchip PolarFire Soc Support @ 2021-03-03 20:02 Atish Patra 2021-03-03 20:02 ` [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra ` (5 more replies) 0 siblings, 6 replies; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly This series adds minimal support for Microchip Polar Fire Soc Icicle kit. It is rebased on v5.12-rc1 and depends on clock support. Only MMC and ethernet drivers are enabled via this series. The idea here is to add the foundational patches so that other drivers can be added to on top of this. The device tree may change based on feedback on bindings of individual driver support patches. This series has been tested on Qemu and Polar Fire Soc Icicle kit. It depends on the updated clock-series[2] and macb fix[3]. The series is also tested by Lewis from Microchip. The series can also be found at. https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html [2] https://www.spinics.net/lists/linux-clk/msg54579.html Changes from v3->v4: 1. Fixed few DT specific issues. 2. Rebased on top of new clock driver. 3. SD card functionality is verified. Changes from v2->v3: 1. Fixed a typo in dt binding. 2. Included MAINTAINERS entry for PolarFire SoC. 3. Improved the dts file by using lowercase clock names and keeping phy details in board specific dts file. Changes from v1->v2: 1. Modified the DT to match the device tree in U-Boot. 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled as it allows larger storage option for linux distros. Atish Patra (4): RISC-V: Add Microchip PolarFire SoC kconfig option dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC RISC-V: Initial DTS for Microchip ICICLE board RISC-V: Enable Microchip PolarFire ICICLE SoC Conor Dooley (1): MAINTAINERS: add microchip polarfire soc support .../devicetree/bindings/riscv/microchip.yaml | 27 ++ MAINTAINERS | 8 + arch/riscv/Kconfig.socs | 7 + arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ arch/riscv/configs/defconfig | 4 + 8 files changed, 450 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi -- 2.25.1 ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra @ 2021-03-03 20:02 ` Atish Patra 2021-03-03 20:02 ` [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra ` (4 subsequent siblings) 5 siblings, 0 replies; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Bin Meng, Anup Patel, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Add Microchip PolarFire kconfig option which selects SoC specific and common drivers that is required for this SoC. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Anup Patel <anup@brainfault.org> --- arch/riscv/Kconfig.socs | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 7efcece8896c..82b298bfd3be 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -1,5 +1,12 @@ menu "SoC selection" +config SOC_MICROCHIP_POLARFIRE + bool "Microchip PolarFire SoCs" + select MCHP_CLK_MPFS + select SIFIVE_PLIC + help + This enables support for Microchip PolarFire SoC platforms. + config SOC_SIFIVE bool "SiFive SoCs" select SERIAL_SIFIVE if TTY -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra 2021-03-03 20:02 ` [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra @ 2021-03-03 20:02 ` Atish Patra 2021-03-08 20:11 ` Rob Herring 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra ` (3 subsequent siblings) 5 siblings, 1 reply; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Add YAML DT binding documentation for the Microchip PolarFire SoC. It is documented at: https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide Signed-off-by: Atish Patra <atish.patra@wdc.com> --- .../devicetree/bindings/riscv/microchip.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml new file mode 100644 index 000000000000..3f981e897126 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -0,0 +1,27 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/microchip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire SoC-based boards device tree bindings + +maintainers: + - Cyril Jean <Cyril.Jean@microchip.com> + - Lewis Hanly <lewis.hanly@microchip.com> + +description: + Microchip PolarFire SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + items: + - enum: + - microchip,mpfs-icicle-kit + - const: microchip,mpfs + +additionalProperties: true + +... -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC 2021-03-03 20:02 ` [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra @ 2021-03-08 20:11 ` Rob Herring 0 siblings, 0 replies; 20+ messages in thread From: Rob Herring @ 2021-03-08 20:11 UTC (permalink / raw) To: Atish Patra Cc: Ivan.Griffin, Anup Patel, Alistair Francis, linux-riscv, Albert Ou, Palmer Dabbelt, devicetree, Björn Töpel, Daire McNamara, Paul Walmsley, Conor.Dooley, linux-kernel, Lewis.Hanly, Rob Herring On Wed, 03 Mar 2021 12:02:50 -0800, Atish Patra wrote: > Add YAML DT binding documentation for the Microchip PolarFire SoC. > It is documented at: > > https://www.microsemi.com/products/fpga-soc/polarfire-soc-icicle-quick-start-guide > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > .../devicetree/bindings/riscv/microchip.yaml | 27 +++++++++++++++++++ > 1 file changed, 27 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra 2021-03-03 20:02 ` [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra 2021-03-03 20:02 ` [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra @ 2021-03-03 20:02 ` Atish Patra 2021-03-09 10:56 ` Ben Dooks ` (2 more replies) 2021-03-03 20:02 ` [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra ` (2 subsequent siblings) 5 siblings, 3 replies; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Add initial DTS for Microchip ICICLE board having only essential devices (clocks, sdhci, ethernet, serial, etc). The device tree is based on the U-Boot patch. https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ Signed-off-by: Atish Patra <atish.patra@wdc.com> --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/microchip/Makefile | 2 + .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ 4 files changed, 404 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/Makefile create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index 7ffd502e3e7b..fe996b88319e 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += sifive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan +subdir-y += microchip obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile new file mode 100644 index 000000000000..622b12771fd3 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts new file mode 100644 index 000000000000..ec79944065c9 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts @@ -0,0 +1,72 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +#include "microchip-mpfs.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit"; + + chosen { + stdout-path = &serial0; + }; + + cpus { + timebase-frequency = <RTCCLK_FREQ>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + clocks = <&clkcfg 26>; + }; + + soc { + }; +}; + +&serial0 { + status = "okay"; +}; + +&serial1 { + status = "okay"; +}; + +&serial2 { + status = "okay"; +}; + +&serial3 { + status = "okay"; +}; + +&sdcard { + status = "okay"; +}; + +&emac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@8 { + reg = <8>; + ti,fifo-depth = <0x01>; + }; +}; + +&emac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@9 { + reg = <9>; + ti,fifo-depth = <0x01>; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi new file mode 100644 index 000000000000..b9819570a7d1 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020 Microchip Technology Inc */ + +/dts-v1/; + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip MPFS Icicle Kit"; + compatible = "microchip,mpfs-icicle-kit"; + + chosen { + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + clock-frequency = <0>; + compatible = "sifive,e51", "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv64imac"; + status = "disabled"; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@1 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <1>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu1_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@2 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <2>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu2_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@3 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <3>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + + cpu3_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + + cpu@4 { + clock-frequency = <0>; + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; + d-cache-block-size = <64>; + d-cache-sets = <64>; + d-cache-size = <32768>; + d-tlb-sets = <1>; + d-tlb-size = <32>; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <64>; + i-cache-size = <32768>; + i-tlb-sets = <1>; + i-tlb-size = <32>; + mmu-type = "riscv,sv39"; + reg = <4>; + riscv,isa = "rv64imafdc"; + tlb-split; + status = "okay"; + cpu4_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + cache-controller@2010000 { + compatible = "sifive,fu540-c000-ccache", "cache"; + cache-block-size = <64>; + cache-level = <2>; + cache-sets = <1024>; + cache-size = <2097152>; + cache-unified; + interrupt-parent = <&plic>; + interrupts = <1 2 3>; + reg = <0x0 0x2010000 0x0 0x1000>; + }; + + clint@2000000 { + compatible = "sifive,clint0"; + reg = <0x0 0x2000000 0x0 0xC000>; + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 + &cpu1_intc 3 &cpu1_intc 7 + &cpu2_intc 3 &cpu2_intc 7 + &cpu3_intc 3 &cpu3_intc 7 + &cpu4_intc 3 &cpu4_intc 7>; + }; + + plic: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "sifive,plic-1.0.0"; + reg = <0x0 0xc000000 0x0 0x4000000>; + riscv,ndev = <186>; + interrupt-controller; + interrupts-extended = <&cpu0_intc 11 + &cpu1_intc 11 &cpu1_intc 9 + &cpu2_intc 11 &cpu2_intc 9 + &cpu3_intc 11 &cpu3_intc 9 + &cpu4_intc 11 &cpu4_intc 9>; + }; + + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + + refclk: refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <600000000>; + clock-output-names = "msspllclk"; + }; + + clkcfg: clkcfg@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + reg-names = "mss_sysreg"; + clocks = <&refclk>; + #clock-cells = <1>; + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ + "mac0", "mac1", "mmc", "timer", /* 4-7 */ + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ + "i2c1", "can0", "can1", "usb", /* 16-19 */ + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ + }; + + serial0: serial@20000000 { + compatible = "ns16550a"; + reg = <0x0 0x20000000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <90>; + current-speed = <115200>; + clocks = <&clkcfg 8>; + status = "disabled"; + }; + + serial1: serial@20100000 { + compatible = "ns16550a"; + reg = <0x0 0x20100000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <91>; + current-speed = <115200>; + clocks = <&clkcfg 9>; + status = "disabled"; + }; + + serial2: serial@20102000 { + compatible = "ns16550a"; + reg = <0x0 0x20102000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <92>; + current-speed = <115200>; + clocks = <&clkcfg 10>; + status = "disabled"; + }; + + serial3: serial@20104000 { + compatible = "ns16550a"; + reg = <0x0 0x20104000 0x0 0x400>; + reg-io-width = <4>; + reg-shift = <2>; + interrupt-parent = <&plic>; + interrupts = <93>; + current-speed = <115200>; + clocks = <&clkcfg 11>; + status = "disabled"; + }; + + emmc: mmc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88 89>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + cap-mmc-highspeed; + mmc-ddr-3_3v; + max-frequency = <200000000>; + non-removable; + no-sd; + no-sdio; + voltage-ranges = <3300 3300>; + status = "disabled"; + }; + + sdcard: sdhc@20008000 { + compatible = "cdns,sd4hc"; + reg = <0x0 0x20008000 0x0 0x1000>; + interrupt-parent = <&plic>; + interrupts = <88>; + pinctrl-names = "default"; + clocks = <&clkcfg 6>; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + card-detect-delay = <200>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + max-frequency = <200000000>; + status = "disabled"; + }; + + emac0: ethernet@20110000 { + compatible = "cdns,macb"; + reg = <0x0 0x20110000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <64 65 66 67>; + local-mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 4>, <&clkcfg 2>; + clock-names = "pclk", "hclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + emac1: ethernet@20112000 { + compatible = "cdns,macb"; + reg = <0x0 0x20112000 0x0 0x2000>; + interrupt-parent = <&plic>; + interrupts = <70 71 72 73>; + mac-address = [00 00 00 00 00 00]; + clocks = <&clkcfg 5>, <&clkcfg 2>; + status = "disabled"; + clock-names = "pclk", "hclk"; + #address-cells = <1>; + #size-cells = <0>; + }; + + }; +}; -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra @ 2021-03-09 10:56 ` Ben Dooks [not found] ` <DM6PR11MB3770E7FA8121AA91D9EDC4FEE5929@DM6PR11MB3770.namprd11.prod.outlook.com> 2021-03-22 6:04 ` Bin Meng 2021-03-27 17:22 ` Alex Ghiti 2 siblings, 1 reply; 20+ messages in thread From: Ben Dooks @ 2021-03-09 10:56 UTC (permalink / raw) To: Atish Patra, linux-kernel Cc: Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On 03/03/2021 20:02, Atish Patra wrote: > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > 4 files changed, 404 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index 7ffd502e3e7b..fe996b88319e 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > subdir-y += sifive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > +subdir-y += microchip > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > new file mode 100644 > index 000000000000..622b12771fd3 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > new file mode 100644 > index 000000000000..ec79944065c9 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microchip Technology Inc */ > + > +/dts-v1/; > + > +#include "microchip-mpfs.dtsi" > + > +/* Clock frequency (in Hz) of the rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "Microchip PolarFire-SoC Icicle Kit"; > + compatible = "microchip,mpfs-icicle-kit"; > + > + chosen { > + stdout-path = &serial0; > + }; > + > + cpus { > + timebase-frequency = <RTCCLK_FREQ>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x40000000>; > + clocks = <&clkcfg 26>; > + }; > + The latest Microchip releases have two memory nodes to provide the full 2GiB of memory space. > + soc { > + }; > +}; > + > +&serial0 { > + status = "okay"; > +}; > + > +&serial1 { > + status = "okay"; > +}; > + > +&serial2 { > + status = "okay"; > +}; > + > +&serial3 { > + status = "okay"; > +}; > + > +&sdcard { > + status = "okay"; > +}; > + > +&emac0 { > + phy-mode = "sgmii"; > + phy-handle = <&phy0>; > + phy0: ethernet-phy@8 { > + reg = <8>; > + ti,fifo-depth = <0x01>; > + }; > +}; > + > +&emac1 { > + status = "okay"; > + phy-mode = "sgmii"; > + phy-handle = <&phy1>; > + phy1: ethernet-phy@9 { > + reg = <9>; > + ti,fifo-depth = <0x01>; > + }; > +}; -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html ^ permalink raw reply [flat|nested] 20+ messages in thread
[parent not found: <DM6PR11MB3770E7FA8121AA91D9EDC4FEE5929@DM6PR11MB3770.namprd11.prod.outlook.com>]
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board [not found] ` <DM6PR11MB3770E7FA8121AA91D9EDC4FEE5929@DM6PR11MB3770.namprd11.prod.outlook.com> @ 2021-03-09 19:34 ` Atish Patra 0 siblings, 0 replies; 20+ messages in thread From: Atish Patra @ 2021-03-09 19:34 UTC (permalink / raw) To: ben.dooks, Lewis.Hanly, linux-kernel Cc: Cyril.Jean, linux-riscv, Alistair Francis, Anup Patel, Conor.Dooley, devicetree, bjorn, aou, palmer, paul.walmsley, Ivan.Griffin, Daire.McNamara, robh+dt On Tue, 2021-03-09 at 13:30 +0000, Lewis.Hanly@microchip.com wrote: > > > From: Ben Dooks <ben.dooks@codethink.co.uk> > Sent: Tuesday, March 9, 2021 10:56 AM > To: Atish Patra <atish.patra@wdc.com>; linux-kernel@vger.kernel.org < > linux-kernel@vger.kernel.org> > Cc: Albert Ou <aou@eecs.berkeley.edu>; Alistair Francis < > alistair.francis@wdc.com>; Anup Patel <anup.patel@wdc.com>; Björn > Töpel <bjorn@kernel.org>; devicetree@vger.kernel.org < > devicetree@vger.kernel.org>; linux-riscv@lists.infradead.org < > linux-riscv@lists.infradead.org>; Palmer Dabbelt > <palmer@dabbelt.com>; Paul Walmsley <paul.walmsley@sifive.com>; Rob > Herring < robh+dt@kernel.org>; Conor Dooley - M52691 < > Conor.Dooley@microchip.com>; Daire McNamara - X61553 < > Daire.McNamara@microchip.com>; Ivan Griffin - X61451 < > Ivan.Griffin@microchip.com>; Lewis Hanly - M34782 < > Lewis.Hanly@microchip.com> > Subject: Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE > board > EXTERNAL EMAIL: Do not click links or open attachments unless you > know the content is safe > > On 03/03/2021 20:02, Atish Patra wrote: > > Add initial DTS for Microchip ICICLE board having only > > essential devices (clocks, sdhci, ethernet, serial, etc). > > The device tree is based on the U-Boot patch. > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 > > ++++++++++++++++++ > > 4 files changed, 404 insertions(+) > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs- > > icicle-kit.dts > > create mode 100644 arch/riscv/boot/dts/microchip/microchip- > > mpfs.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile > > b/arch/riscv/boot/dts/Makefile > > index 7ffd502e3e7b..fe996b88319e 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,5 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0 > > subdir-y += sifive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > +subdir-y += microchip > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > > b/arch/riscv/boot/dts/microchip/Makefile > > new file mode 100644 > > index 000000000000..622b12771fd3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle- > > kit.dtb > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle- > > kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle- > > kit.dts > > new file mode 100644 > > index 000000000000..ec79944065c9 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > @@ -0,0 +1,72 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > + > > +/dts-v1/; > > + > > +#include "microchip-mpfs.dtsi" > > + > > +/* Clock frequency (in Hz) of the rtcclk */ > > +#define RTCCLK_FREQ 1000000 > > + > > +/ { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > + compatible = "microchip,mpfs-icicle-kit"; > > + > > + chosen { > > + stdout-path = &serial0; > > + }; > > + > > + cpus { > > + timebase-frequency = <RTCCLK_FREQ>; > > + }; > > + > > + memory@80000000 { > > + device_type = "memory"; > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > + clocks = <&clkcfg 26>; > > + }; > > + > > The latest Microchip releases have two memory nodes to provide the > full 2GiB of memory space. > > > For this release we want to leave it at 1GB, wip memory remapping > > > with the newer releases. > Thanks for the clarification. For some reason, your reply did not land in the mailing lists. > > + soc { > > + }; > > +}; > > + > > +&serial0 { > > + status = "okay"; > > +}; > > + > > +&serial1 { > > + status = "okay"; > > +}; > > + > > +&serial2 { > > + status = "okay"; > > +}; > > + > > +&serial3 { > > + status = "okay"; > > +}; > > + > > +&sdcard { > > + status = "okay"; > > +}; > > + > > +&emac0 { > > + phy-mode = "sgmii"; > > + phy-handle = <&phy0>; > > + phy0: ethernet-phy@8 { > > + reg = <8>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > + > > +&emac1 { > > + status = "okay"; > > + phy-mode = "sgmii"; > > + phy-handle = <&phy1>; > > + phy1: ethernet-phy@9 { > > + reg = <9>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > > > -- > Ben Dooks http://www.codethink.co.uk/ > Senior Engineer Codethink - Providing Genius > > https://www.codethink.co.uk/privacy.html -- Regards, Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra 2021-03-09 10:56 ` Ben Dooks @ 2021-03-22 6:04 ` Bin Meng 2021-03-27 17:22 ` Alex Ghiti 2 siblings, 0 replies; 20+ messages in thread From: Bin Meng @ 2021-03-22 6:04 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Thu, Mar 4, 2021 at 8:48 PM Atish Patra <atish.patra@wdc.com> wrote: > > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > 4 files changed, 404 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > Reviewed-by: Bin Meng <bin.meng@windriver.com> ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra 2021-03-09 10:56 ` Ben Dooks 2021-03-22 6:04 ` Bin Meng @ 2021-03-27 17:22 ` Alex Ghiti 2021-03-28 15:22 ` Vitaly Wool 2 siblings, 1 reply; 20+ messages in thread From: Alex Ghiti @ 2021-03-27 17:22 UTC (permalink / raw) To: Atish Patra, linux-kernel Cc: Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Hi Atish, Le 3/3/21 à 3:02 PM, Atish Patra a écrit : > Add initial DTS for Microchip ICICLE board having only > essential devices (clocks, sdhci, ethernet, serial, etc). > The device tree is based on the U-Boot patch. > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > --- > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > 4 files changed, 404 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > index 7ffd502e3e7b..fe996b88319e 100644 > --- a/arch/riscv/boot/dts/Makefile > +++ b/arch/riscv/boot/dts/Makefile > @@ -1,5 +1,6 @@ > # SPDX-License-Identifier: GPL-2.0 > subdir-y += sifive > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > +subdir-y += microchip > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > new file mode 100644 > index 000000000000..622b12771fd3 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -0,0 +1,2 @@ > +# SPDX-License-Identifier: GPL-2.0 > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb I'm playing (or trying to...) with XIP_KERNEL and I had to add the following to have the device tree actually builtin the kernel: diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 622b12771fd3..855c1502d912 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) Alex > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > new file mode 100644 > index 000000000000..ec79944065c9 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > @@ -0,0 +1,72 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microchip Technology Inc */ > + > +/dts-v1/; > + > +#include "microchip-mpfs.dtsi" > + > +/* Clock frequency (in Hz) of the rtcclk */ > +#define RTCCLK_FREQ 1000000 > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "Microchip PolarFire-SoC Icicle Kit"; > + compatible = "microchip,mpfs-icicle-kit"; > + > + chosen { > + stdout-path = &serial0; > + }; > + > + cpus { > + timebase-frequency = <RTCCLK_FREQ>; > + }; > + > + memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x40000000>; > + clocks = <&clkcfg 26>; > + }; > + > + soc { > + }; > +}; > + > +&serial0 { > + status = "okay"; > +}; > + > +&serial1 { > + status = "okay"; > +}; > + > +&serial2 { > + status = "okay"; > +}; > + > +&serial3 { > + status = "okay"; > +}; > + > +&sdcard { > + status = "okay"; > +}; > + > +&emac0 { > + phy-mode = "sgmii"; > + phy-handle = <&phy0>; > + phy0: ethernet-phy@8 { > + reg = <8>; > + ti,fifo-depth = <0x01>; > + }; > +}; > + > +&emac1 { > + status = "okay"; > + phy-mode = "sgmii"; > + phy-handle = <&phy1>; > + phy1: ethernet-phy@9 { > + reg = <9>; > + ti,fifo-depth = <0x01>; > + }; > +}; > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > new file mode 100644 > index 000000000000..b9819570a7d1 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > @@ -0,0 +1,329 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2020 Microchip Technology Inc */ > + > +/dts-v1/; > + > +/ { > + #address-cells = <2>; > + #size-cells = <2>; > + model = "Microchip MPFS Icicle Kit"; > + compatible = "microchip,mpfs-icicle-kit"; > + > + chosen { > + }; > + > + cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + > + cpu@0 { > + clock-frequency = <0>; > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <16384>; > + reg = <0>; > + riscv,isa = "rv64imac"; > + status = "disabled"; > + > + cpu0_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@1 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <1>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu1_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@2 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <2>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu2_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@3 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <3>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + > + cpu3_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + > + cpu@4 { > + clock-frequency = <0>; > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > + d-cache-block-size = <64>; > + d-cache-sets = <64>; > + d-cache-size = <32768>; > + d-tlb-sets = <1>; > + d-tlb-size = <32>; > + device_type = "cpu"; > + i-cache-block-size = <64>; > + i-cache-sets = <64>; > + i-cache-size = <32768>; > + i-tlb-sets = <1>; > + i-tlb-size = <32>; > + mmu-type = "riscv,sv39"; > + reg = <4>; > + riscv,isa = "rv64imafdc"; > + tlb-split; > + status = "okay"; > + cpu4_intc: interrupt-controller { > + #interrupt-cells = <1>; > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + }; > + }; > + }; > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + compatible = "simple-bus"; > + ranges; > + > + cache-controller@2010000 { > + compatible = "sifive,fu540-c000-ccache", "cache"; > + cache-block-size = <64>; > + cache-level = <2>; > + cache-sets = <1024>; > + cache-size = <2097152>; > + cache-unified; > + interrupt-parent = <&plic>; > + interrupts = <1 2 3>; > + reg = <0x0 0x2010000 0x0 0x1000>; > + }; > + > + clint@2000000 { > + compatible = "sifive,clint0"; > + reg = <0x0 0x2000000 0x0 0xC000>; > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > + &cpu1_intc 3 &cpu1_intc 7 > + &cpu2_intc 3 &cpu2_intc 7 > + &cpu3_intc 3 &cpu3_intc 7 > + &cpu4_intc 3 &cpu4_intc 7>; > + }; > + > + plic: interrupt-controller@c000000 { > + #interrupt-cells = <1>; > + compatible = "sifive,plic-1.0.0"; > + reg = <0x0 0xc000000 0x0 0x4000000>; > + riscv,ndev = <186>; > + interrupt-controller; > + interrupts-extended = <&cpu0_intc 11 > + &cpu1_intc 11 &cpu1_intc 9 > + &cpu2_intc 11 &cpu2_intc 9 > + &cpu3_intc 11 &cpu3_intc 9 > + &cpu4_intc 11 &cpu4_intc 9>; > + }; > + > + dma@3000000 { > + compatible = "sifive,fu540-c000-pdma"; > + reg = <0x0 0x3000000 0x0 0x8000>; > + interrupt-parent = <&plic>; > + interrupts = <23 24 25 26 27 28 29 30>; > + #dma-cells = <1>; > + }; > + > + refclk: refclk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <600000000>; > + clock-output-names = "msspllclk"; > + }; > + > + clkcfg: clkcfg@20002000 { > + compatible = "microchip,mpfs-clkcfg"; > + reg = <0x0 0x20002000 0x0 0x1000>; > + reg-names = "mss_sysreg"; > + clocks = <&refclk>; > + #clock-cells = <1>; > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > + }; > + > + serial0: serial@20000000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20000000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <90>; > + current-speed = <115200>; > + clocks = <&clkcfg 8>; > + status = "disabled"; > + }; > + > + serial1: serial@20100000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20100000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <91>; > + current-speed = <115200>; > + clocks = <&clkcfg 9>; > + status = "disabled"; > + }; > + > + serial2: serial@20102000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20102000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <92>; > + current-speed = <115200>; > + clocks = <&clkcfg 10>; > + status = "disabled"; > + }; > + > + serial3: serial@20104000 { > + compatible = "ns16550a"; > + reg = <0x0 0x20104000 0x0 0x400>; > + reg-io-width = <4>; > + reg-shift = <2>; > + interrupt-parent = <&plic>; > + interrupts = <93>; > + current-speed = <115200>; > + clocks = <&clkcfg 11>; > + status = "disabled"; > + }; > + > + emmc: mmc@20008000 { > + compatible = "cdns,sd4hc"; > + reg = <0x0 0x20008000 0x0 0x1000>; > + interrupt-parent = <&plic>; > + interrupts = <88 89>; > + pinctrl-names = "default"; > + clocks = <&clkcfg 6>; > + bus-width = <4>; > + cap-mmc-highspeed; > + mmc-ddr-3_3v; > + max-frequency = <200000000>; > + non-removable; > + no-sd; > + no-sdio; > + voltage-ranges = <3300 3300>; > + status = "disabled"; > + }; > + > + sdcard: sdhc@20008000 { > + compatible = "cdns,sd4hc"; > + reg = <0x0 0x20008000 0x0 0x1000>; > + interrupt-parent = <&plic>; > + interrupts = <88>; > + pinctrl-names = "default"; > + clocks = <&clkcfg 6>; > + bus-width = <4>; > + disable-wp; > + cap-sd-highspeed; > + card-detect-delay = <200>; > + sd-uhs-sdr12; > + sd-uhs-sdr25; > + sd-uhs-sdr50; > + sd-uhs-sdr104; > + max-frequency = <200000000>; > + status = "disabled"; > + }; > + > + emac0: ethernet@20110000 { > + compatible = "cdns,macb"; > + reg = <0x0 0x20110000 0x0 0x2000>; > + interrupt-parent = <&plic>; > + interrupts = <64 65 66 67>; > + local-mac-address = [00 00 00 00 00 00]; > + clocks = <&clkcfg 4>, <&clkcfg 2>; > + clock-names = "pclk", "hclk"; > + status = "disabled"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + emac1: ethernet@20112000 { > + compatible = "cdns,macb"; > + reg = <0x0 0x20112000 0x0 0x2000>; > + interrupt-parent = <&plic>; > + interrupts = <70 71 72 73>; > + mac-address = [00 00 00 00 00 00]; > + clocks = <&clkcfg 5>, <&clkcfg 2>; > + status = "disabled"; > + clock-names = "pclk", "hclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + }; > +}; > ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-27 17:22 ` Alex Ghiti @ 2021-03-28 15:22 ` Vitaly Wool 2021-04-18 3:36 ` Atish Patra 0 siblings, 1 reply; 20+ messages in thread From: Vitaly Wool @ 2021-03-28 15:22 UTC (permalink / raw) To: Alex Ghiti Cc: Atish Patra, LKML, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti <alex@ghiti.fr> wrote: > > Hi Atish, > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit : > > Add initial DTS for Microchip ICICLE board having only > > essential devices (clocks, sdhci, ethernet, serial, etc). > > The device tree is based on the U-Boot patch. > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > --- > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > 4 files changed, 404 insertions(+) > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > > index 7ffd502e3e7b..fe996b88319e 100644 > > --- a/arch/riscv/boot/dts/Makefile > > +++ b/arch/riscv/boot/dts/Makefile > > @@ -1,5 +1,6 @@ > > # SPDX-License-Identifier: GPL-2.0 > > subdir-y += sifive > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > +subdir-y += microchip > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > > new file mode 100644 > > index 000000000000..622b12771fd3 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > @@ -0,0 +1,2 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the > following to have the device tree actually builtin the kernel: > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > b/arch/riscv/boot/dts/microchip/Makefile > index 622b12771fd3..855c1502d912 100644 > --- a/arch/riscv/boot/dts/microchip/Makefile > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -1,2 +1,3 @@ > # SPDX-License-Identifier: GPL-2.0 > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > > Alex Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire, regardless of whether the kernel is XIP or not. Best regards, Vitaly > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > new file mode 100644 > > index 000000000000..ec79944065c9 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > @@ -0,0 +1,72 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > + > > +/dts-v1/; > > + > > +#include "microchip-mpfs.dtsi" > > + > > +/* Clock frequency (in Hz) of the rtcclk */ > > +#define RTCCLK_FREQ 1000000 > > + > > +/ { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > + compatible = "microchip,mpfs-icicle-kit"; > > + > > + chosen { > > + stdout-path = &serial0; > > + }; > > + > > + cpus { > > + timebase-frequency = <RTCCLK_FREQ>; > > + }; > > + > > + memory@80000000 { > > + device_type = "memory"; > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > + clocks = <&clkcfg 26>; > > + }; > > + > > + soc { > > + }; > > +}; > > + > > +&serial0 { > > + status = "okay"; > > +}; > > + > > +&serial1 { > > + status = "okay"; > > +}; > > + > > +&serial2 { > > + status = "okay"; > > +}; > > + > > +&serial3 { > > + status = "okay"; > > +}; > > + > > +&sdcard { > > + status = "okay"; > > +}; > > + > > +&emac0 { > > + phy-mode = "sgmii"; > > + phy-handle = <&phy0>; > > + phy0: ethernet-phy@8 { > > + reg = <8>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > + > > +&emac1 { > > + status = "okay"; > > + phy-mode = "sgmii"; > > + phy-handle = <&phy1>; > > + phy1: ethernet-phy@9 { > > + reg = <9>; > > + ti,fifo-depth = <0x01>; > > + }; > > +}; > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > new file mode 100644 > > index 000000000000..b9819570a7d1 > > --- /dev/null > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > @@ -0,0 +1,329 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > + > > +/dts-v1/; > > + > > +/ { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + model = "Microchip MPFS Icicle Kit"; > > + compatible = "microchip,mpfs-icicle-kit"; > > + > > + chosen { > > + }; > > + > > + cpus { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + cpu@0 { > > + clock-frequency = <0>; > > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <128>; > > + i-cache-size = <16384>; > > + reg = <0>; > > + riscv,isa = "rv64imac"; > > + status = "disabled"; > > + > > + cpu0_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@1 { > > + clock-frequency = <0>; > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <1>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu1_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@2 { > > + clock-frequency = <0>; > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <2>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu2_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@3 { > > + clock-frequency = <0>; > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <3>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + > > + cpu3_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + > > + cpu@4 { > > + clock-frequency = <0>; > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > + d-cache-block-size = <64>; > > + d-cache-sets = <64>; > > + d-cache-size = <32768>; > > + d-tlb-sets = <1>; > > + d-tlb-size = <32>; > > + device_type = "cpu"; > > + i-cache-block-size = <64>; > > + i-cache-sets = <64>; > > + i-cache-size = <32768>; > > + i-tlb-sets = <1>; > > + i-tlb-size = <32>; > > + mmu-type = "riscv,sv39"; > > + reg = <4>; > > + riscv,isa = "rv64imafdc"; > > + tlb-split; > > + status = "okay"; > > + cpu4_intc: interrupt-controller { > > + #interrupt-cells = <1>; > > + compatible = "riscv,cpu-intc"; > > + interrupt-controller; > > + }; > > + }; > > + }; > > + > > + soc { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + compatible = "simple-bus"; > > + ranges; > > + > > + cache-controller@2010000 { > > + compatible = "sifive,fu540-c000-ccache", "cache"; > > + cache-block-size = <64>; > > + cache-level = <2>; > > + cache-sets = <1024>; > > + cache-size = <2097152>; > > + cache-unified; > > + interrupt-parent = <&plic>; > > + interrupts = <1 2 3>; > > + reg = <0x0 0x2010000 0x0 0x1000>; > > + }; > > + > > + clint@2000000 { > > + compatible = "sifive,clint0"; > > + reg = <0x0 0x2000000 0x0 0xC000>; > > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > + &cpu1_intc 3 &cpu1_intc 7 > > + &cpu2_intc 3 &cpu2_intc 7 > > + &cpu3_intc 3 &cpu3_intc 7 > > + &cpu4_intc 3 &cpu4_intc 7>; > > + }; > > + > > + plic: interrupt-controller@c000000 { > > + #interrupt-cells = <1>; > > + compatible = "sifive,plic-1.0.0"; > > + reg = <0x0 0xc000000 0x0 0x4000000>; > > + riscv,ndev = <186>; > > + interrupt-controller; > > + interrupts-extended = <&cpu0_intc 11 > > + &cpu1_intc 11 &cpu1_intc 9 > > + &cpu2_intc 11 &cpu2_intc 9 > > + &cpu3_intc 11 &cpu3_intc 9 > > + &cpu4_intc 11 &cpu4_intc 9>; > > + }; > > + > > + dma@3000000 { > > + compatible = "sifive,fu540-c000-pdma"; > > + reg = <0x0 0x3000000 0x0 0x8000>; > > + interrupt-parent = <&plic>; > > + interrupts = <23 24 25 26 27 28 29 30>; > > + #dma-cells = <1>; > > + }; > > + > > + refclk: refclk { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <600000000>; > > + clock-output-names = "msspllclk"; > > + }; > > + > > + clkcfg: clkcfg@20002000 { > > + compatible = "microchip,mpfs-clkcfg"; > > + reg = <0x0 0x20002000 0x0 0x1000>; > > + reg-names = "mss_sysreg"; > > + clocks = <&refclk>; > > + #clock-cells = <1>; > > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > > + }; > > + > > + serial0: serial@20000000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20000000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <90>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 8>; > > + status = "disabled"; > > + }; > > + > > + serial1: serial@20100000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20100000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <91>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 9>; > > + status = "disabled"; > > + }; > > + > > + serial2: serial@20102000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20102000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <92>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 10>; > > + status = "disabled"; > > + }; > > + > > + serial3: serial@20104000 { > > + compatible = "ns16550a"; > > + reg = <0x0 0x20104000 0x0 0x400>; > > + reg-io-width = <4>; > > + reg-shift = <2>; > > + interrupt-parent = <&plic>; > > + interrupts = <93>; > > + current-speed = <115200>; > > + clocks = <&clkcfg 11>; > > + status = "disabled"; > > + }; > > + > > + emmc: mmc@20008000 { > > + compatible = "cdns,sd4hc"; > > + reg = <0x0 0x20008000 0x0 0x1000>; > > + interrupt-parent = <&plic>; > > + interrupts = <88 89>; > > + pinctrl-names = "default"; > > + clocks = <&clkcfg 6>; > > + bus-width = <4>; > > + cap-mmc-highspeed; > > + mmc-ddr-3_3v; > > + max-frequency = <200000000>; > > + non-removable; > > + no-sd; > > + no-sdio; > > + voltage-ranges = <3300 3300>; > > + status = "disabled"; > > + }; > > + > > + sdcard: sdhc@20008000 { > > + compatible = "cdns,sd4hc"; > > + reg = <0x0 0x20008000 0x0 0x1000>; > > + interrupt-parent = <&plic>; > > + interrupts = <88>; > > + pinctrl-names = "default"; > > + clocks = <&clkcfg 6>; > > + bus-width = <4>; > > + disable-wp; > > + cap-sd-highspeed; > > + card-detect-delay = <200>; > > + sd-uhs-sdr12; > > + sd-uhs-sdr25; > > + sd-uhs-sdr50; > > + sd-uhs-sdr104; > > + max-frequency = <200000000>; > > + status = "disabled"; > > + }; > > + > > + emac0: ethernet@20110000 { > > + compatible = "cdns,macb"; > > + reg = <0x0 0x20110000 0x0 0x2000>; > > + interrupt-parent = <&plic>; > > + interrupts = <64 65 66 67>; > > + local-mac-address = [00 00 00 00 00 00]; > > + clocks = <&clkcfg 4>, <&clkcfg 2>; > > + clock-names = "pclk", "hclk"; > > + status = "disabled"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + emac1: ethernet@20112000 { > > + compatible = "cdns,macb"; > > + reg = <0x0 0x20112000 0x0 0x2000>; > > + interrupt-parent = <&plic>; > > + interrupts = <70 71 72 73>; > > + mac-address = [00 00 00 00 00 00]; > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > + status = "disabled"; > > + clock-names = "pclk", "hclk"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + }; > > + > > + }; > > +}; > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-03-28 15:22 ` Vitaly Wool @ 2021-04-18 3:36 ` Atish Patra 2021-04-18 4:24 ` Atish Patra 2021-04-18 18:39 ` Vitaly Wool 0 siblings, 2 replies; 20+ messages in thread From: Atish Patra @ 2021-04-18 3:36 UTC (permalink / raw) To: Vitaly Wool Cc: Alex Ghiti, Atish Patra, LKML, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool <vitaly.wool@konsulko.com> wrote: > > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti <alex@ghiti.fr> wrote: > > > > Hi Atish, > > > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit : > > > Add initial DTS for Microchip ICICLE board having only > > > essential devices (clocks, sdhci, ethernet, serial, etc). > > > The device tree is based on the U-Boot patch. > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > > --- > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > > 4 files changed, 404 insertions(+) > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > > > index 7ffd502e3e7b..fe996b88319e 100644 > > > --- a/arch/riscv/boot/dts/Makefile > > > +++ b/arch/riscv/boot/dts/Makefile > > > @@ -1,5 +1,6 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > subdir-y += sifive > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > > +subdir-y += microchip > > > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > > > new file mode 100644 > > > index 000000000000..622b12771fd3 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > @@ -0,0 +1,2 @@ > > > +# SPDX-License-Identifier: GPL-2.0 > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the > > following to have the device tree actually builtin the kernel: > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > > b/arch/riscv/boot/dts/microchip/Makefile > > index 622b12771fd3..855c1502d912 100644 > > --- a/arch/riscv/boot/dts/microchip/Makefile > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > @@ -1,2 +1,3 @@ > > # SPDX-License-Identifier: GPL-2.0 > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > > > > Alex > > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire, > regardless of whether the kernel is XIP or not. > But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel. The bootloaders for polarfire is capable of providing a DTB to kernel. If XIP kernel is enabled, the following line in arch/riscv/boot/dts/Makefile should take care of things > Best regards, > Vitaly > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > new file mode 100644 > > > index 000000000000..ec79944065c9 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > @@ -0,0 +1,72 @@ > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > + > > > +/dts-v1/; > > > + > > > +#include "microchip-mpfs.dtsi" > > > + > > > +/* Clock frequency (in Hz) of the rtcclk */ > > > +#define RTCCLK_FREQ 1000000 > > > + > > > +/ { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > > + compatible = "microchip,mpfs-icicle-kit"; > > > + > > > + chosen { > > > + stdout-path = &serial0; > > > + }; > > > + > > > + cpus { > > > + timebase-frequency = <RTCCLK_FREQ>; > > > + }; > > > + > > > + memory@80000000 { > > > + device_type = "memory"; > > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > > + clocks = <&clkcfg 26>; > > > + }; > > > + > > > + soc { > > > + }; > > > +}; > > > + > > > +&serial0 { > > > + status = "okay"; > > > +}; > > > + > > > +&serial1 { > > > + status = "okay"; > > > +}; > > > + > > > +&serial2 { > > > + status = "okay"; > > > +}; > > > + > > > +&serial3 { > > > + status = "okay"; > > > +}; > > > + > > > +&sdcard { > > > + status = "okay"; > > > +}; > > > + > > > +&emac0 { > > > + phy-mode = "sgmii"; > > > + phy-handle = <&phy0>; > > > + phy0: ethernet-phy@8 { > > > + reg = <8>; > > > + ti,fifo-depth = <0x01>; > > > + }; > > > +}; > > > + > > > +&emac1 { > > > + status = "okay"; > > > + phy-mode = "sgmii"; > > > + phy-handle = <&phy1>; > > > + phy1: ethernet-phy@9 { > > > + reg = <9>; > > > + ti,fifo-depth = <0x01>; > > > + }; > > > +}; > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > new file mode 100644 > > > index 000000000000..b9819570a7d1 > > > --- /dev/null > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > @@ -0,0 +1,329 @@ > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > + > > > +/dts-v1/; > > > + > > > +/ { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + model = "Microchip MPFS Icicle Kit"; > > > + compatible = "microchip,mpfs-icicle-kit"; > > > + > > > + chosen { > > > + }; > > > + > > > + cpus { > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + > > > + cpu@0 { > > > + clock-frequency = <0>; > > > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > > > + device_type = "cpu"; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <128>; > > > + i-cache-size = <16384>; > > > + reg = <0>; > > > + riscv,isa = "rv64imac"; > > > + status = "disabled"; > > > + > > > + cpu0_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@1 { > > > + clock-frequency = <0>; > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <64>; > > > + d-cache-size = <32768>; > > > + d-tlb-sets = <1>; > > > + d-tlb-size = <32>; > > > + device_type = "cpu"; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <64>; > > > + i-cache-size = <32768>; > > > + i-tlb-sets = <1>; > > > + i-tlb-size = <32>; > > > + mmu-type = "riscv,sv39"; > > > + reg = <1>; > > > + riscv,isa = "rv64imafdc"; > > > + tlb-split; > > > + status = "okay"; > > > + > > > + cpu1_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@2 { > > > + clock-frequency = <0>; > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <64>; > > > + d-cache-size = <32768>; > > > + d-tlb-sets = <1>; > > > + d-tlb-size = <32>; > > > + device_type = "cpu"; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <64>; > > > + i-cache-size = <32768>; > > > + i-tlb-sets = <1>; > > > + i-tlb-size = <32>; > > > + mmu-type = "riscv,sv39"; > > > + reg = <2>; > > > + riscv,isa = "rv64imafdc"; > > > + tlb-split; > > > + status = "okay"; > > > + > > > + cpu2_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@3 { > > > + clock-frequency = <0>; > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <64>; > > > + d-cache-size = <32768>; > > > + d-tlb-sets = <1>; > > > + d-tlb-size = <32>; > > > + device_type = "cpu"; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <64>; > > > + i-cache-size = <32768>; > > > + i-tlb-sets = <1>; > > > + i-tlb-size = <32>; > > > + mmu-type = "riscv,sv39"; > > > + reg = <3>; > > > + riscv,isa = "rv64imafdc"; > > > + tlb-split; > > > + status = "okay"; > > > + > > > + cpu3_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + > > > + cpu@4 { > > > + clock-frequency = <0>; > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > + d-cache-block-size = <64>; > > > + d-cache-sets = <64>; > > > + d-cache-size = <32768>; > > > + d-tlb-sets = <1>; > > > + d-tlb-size = <32>; > > > + device_type = "cpu"; > > > + i-cache-block-size = <64>; > > > + i-cache-sets = <64>; > > > + i-cache-size = <32768>; > > > + i-tlb-sets = <1>; > > > + i-tlb-size = <32>; > > > + mmu-type = "riscv,sv39"; > > > + reg = <4>; > > > + riscv,isa = "rv64imafdc"; > > > + tlb-split; > > > + status = "okay"; > > > + cpu4_intc: interrupt-controller { > > > + #interrupt-cells = <1>; > > > + compatible = "riscv,cpu-intc"; > > > + interrupt-controller; > > > + }; > > > + }; > > > + }; > > > + > > > + soc { > > > + #address-cells = <2>; > > > + #size-cells = <2>; > > > + compatible = "simple-bus"; > > > + ranges; > > > + > > > + cache-controller@2010000 { > > > + compatible = "sifive,fu540-c000-ccache", "cache"; > > > + cache-block-size = <64>; > > > + cache-level = <2>; > > > + cache-sets = <1024>; > > > + cache-size = <2097152>; > > > + cache-unified; > > > + interrupt-parent = <&plic>; > > > + interrupts = <1 2 3>; > > > + reg = <0x0 0x2010000 0x0 0x1000>; > > > + }; > > > + > > > + clint@2000000 { > > > + compatible = "sifive,clint0"; > > > + reg = <0x0 0x2000000 0x0 0xC000>; > > > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > > + &cpu1_intc 3 &cpu1_intc 7 > > > + &cpu2_intc 3 &cpu2_intc 7 > > > + &cpu3_intc 3 &cpu3_intc 7 > > > + &cpu4_intc 3 &cpu4_intc 7>; > > > + }; > > > + > > > + plic: interrupt-controller@c000000 { > > > + #interrupt-cells = <1>; > > > + compatible = "sifive,plic-1.0.0"; > > > + reg = <0x0 0xc000000 0x0 0x4000000>; > > > + riscv,ndev = <186>; > > > + interrupt-controller; > > > + interrupts-extended = <&cpu0_intc 11 > > > + &cpu1_intc 11 &cpu1_intc 9 > > > + &cpu2_intc 11 &cpu2_intc 9 > > > + &cpu3_intc 11 &cpu3_intc 9 > > > + &cpu4_intc 11 &cpu4_intc 9>; > > > + }; > > > + > > > + dma@3000000 { > > > + compatible = "sifive,fu540-c000-pdma"; > > > + reg = <0x0 0x3000000 0x0 0x8000>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <23 24 25 26 27 28 29 30>; > > > + #dma-cells = <1>; > > > + }; > > > + > > > + refclk: refclk { > > > + compatible = "fixed-clock"; > > > + #clock-cells = <0>; > > > + clock-frequency = <600000000>; > > > + clock-output-names = "msspllclk"; > > > + }; > > > + > > > + clkcfg: clkcfg@20002000 { > > > + compatible = "microchip,mpfs-clkcfg"; > > > + reg = <0x0 0x20002000 0x0 0x1000>; > > > + reg-names = "mss_sysreg"; > > > + clocks = <&refclk>; > > > + #clock-cells = <1>; > > > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > > > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > > > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > > > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > > > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > > > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > > > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > > > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > > > + }; > > > + > > > + serial0: serial@20000000 { > > > + compatible = "ns16550a"; > > > + reg = <0x0 0x20000000 0x0 0x400>; > > > + reg-io-width = <4>; > > > + reg-shift = <2>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <90>; > > > + current-speed = <115200>; > > > + clocks = <&clkcfg 8>; > > > + status = "disabled"; > > > + }; > > > + > > > + serial1: serial@20100000 { > > > + compatible = "ns16550a"; > > > + reg = <0x0 0x20100000 0x0 0x400>; > > > + reg-io-width = <4>; > > > + reg-shift = <2>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <91>; > > > + current-speed = <115200>; > > > + clocks = <&clkcfg 9>; > > > + status = "disabled"; > > > + }; > > > + > > > + serial2: serial@20102000 { > > > + compatible = "ns16550a"; > > > + reg = <0x0 0x20102000 0x0 0x400>; > > > + reg-io-width = <4>; > > > + reg-shift = <2>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <92>; > > > + current-speed = <115200>; > > > + clocks = <&clkcfg 10>; > > > + status = "disabled"; > > > + }; > > > + > > > + serial3: serial@20104000 { > > > + compatible = "ns16550a"; > > > + reg = <0x0 0x20104000 0x0 0x400>; > > > + reg-io-width = <4>; > > > + reg-shift = <2>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <93>; > > > + current-speed = <115200>; > > > + clocks = <&clkcfg 11>; > > > + status = "disabled"; > > > + }; > > > + > > > + emmc: mmc@20008000 { > > > + compatible = "cdns,sd4hc"; > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <88 89>; > > > + pinctrl-names = "default"; > > > + clocks = <&clkcfg 6>; > > > + bus-width = <4>; > > > + cap-mmc-highspeed; > > > + mmc-ddr-3_3v; > > > + max-frequency = <200000000>; > > > + non-removable; > > > + no-sd; > > > + no-sdio; > > > + voltage-ranges = <3300 3300>; > > > + status = "disabled"; > > > + }; > > > + > > > + sdcard: sdhc@20008000 { > > > + compatible = "cdns,sd4hc"; > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <88>; > > > + pinctrl-names = "default"; > > > + clocks = <&clkcfg 6>; > > > + bus-width = <4>; > > > + disable-wp; > > > + cap-sd-highspeed; > > > + card-detect-delay = <200>; > > > + sd-uhs-sdr12; > > > + sd-uhs-sdr25; > > > + sd-uhs-sdr50; > > > + sd-uhs-sdr104; > > > + max-frequency = <200000000>; > > > + status = "disabled"; > > > + }; > > > + > > > + emac0: ethernet@20110000 { > > > + compatible = "cdns,macb"; > > > + reg = <0x0 0x20110000 0x0 0x2000>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <64 65 66 67>; > > > + local-mac-address = [00 00 00 00 00 00]; > > > + clocks = <&clkcfg 4>, <&clkcfg 2>; > > > + clock-names = "pclk", "hclk"; > > > + status = "disabled"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + }; > > > + > > > + emac1: ethernet@20112000 { > > > + compatible = "cdns,macb"; > > > + reg = <0x0 0x20112000 0x0 0x2000>; > > > + interrupt-parent = <&plic>; > > > + interrupts = <70 71 72 73>; > > > + mac-address = [00 00 00 00 00 00]; > > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > > + status = "disabled"; > > > + clock-names = "pclk", "hclk"; > > > + #address-cells = <1>; > > > + #size-cells = <0>; > > > + }; > > > + > > > + }; > > > +}; > > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Regards, Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-04-18 3:36 ` Atish Patra @ 2021-04-18 4:24 ` Atish Patra 2021-04-18 18:39 ` Vitaly Wool 1 sibling, 0 replies; 20+ messages in thread From: Atish Patra @ 2021-04-18 4:24 UTC (permalink / raw) To: Vitaly Wool Cc: Alex Ghiti, Atish Patra, LKML, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Sat, Apr 17, 2021 at 8:36 PM Atish Patra <atishp@atishpatra.org> wrote: > > On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool <vitaly.wool@konsulko.com> wrote: > > > > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti <alex@ghiti.fr> wrote: > > > > > > Hi Atish, > > > > > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit : > > > > Add initial DTS for Microchip ICICLE board having only > > > > essential devices (clocks, sdhci, ethernet, serial, etc). > > > > The device tree is based on the U-Boot patch. > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > > > --- > > > > arch/riscv/boot/dts/Makefile | 1 + > > > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > > > 4 files changed, 404 insertions(+) > > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > > > > index 7ffd502e3e7b..fe996b88319e 100644 > > > > --- a/arch/riscv/boot/dts/Makefile > > > > +++ b/arch/riscv/boot/dts/Makefile > > > > @@ -1,5 +1,6 @@ > > > > # SPDX-License-Identifier: GPL-2.0 > > > > subdir-y += sifive > > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > > > +subdir-y += microchip > > > > > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > > > > new file mode 100644 > > > > index 000000000000..622b12771fd3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > > @@ -0,0 +1,2 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > > > > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the > > > following to have the device tree actually builtin the kernel: > > > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > > > b/arch/riscv/boot/dts/microchip/Makefile > > > index 622b12771fd3..855c1502d912 100644 > > > --- a/arch/riscv/boot/dts/microchip/Makefile > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > @@ -1,2 +1,3 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > > > > > > Alex > > > > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire, > > regardless of whether the kernel is XIP or not. > > > > But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel. > The bootloaders for polarfire is capable of providing a DTB to kernel. > > If XIP kernel is enabled, the following line in > arch/riscv/boot/dts/Makefile should take care of things > (Sorry. The mail was sent by mistake earlier with incomplete response) Otherwise, we need a similar change for unleashed as well. No ? > > > Best regards, > > Vitaly > > > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > new file mode 100644 > > > > index 000000000000..ec79944065c9 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > @@ -0,0 +1,72 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > > + > > > > +/dts-v1/; > > > > + > > > > +#include "microchip-mpfs.dtsi" > > > > + > > > > +/* Clock frequency (in Hz) of the rtcclk */ > > > > +#define RTCCLK_FREQ 1000000 > > > > + > > > > +/ { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > > > + compatible = "microchip,mpfs-icicle-kit"; > > > > + > > > > + chosen { > > > > + stdout-path = &serial0; > > > > + }; > > > > + > > > > + cpus { > > > > + timebase-frequency = <RTCCLK_FREQ>; > > > > + }; > > > > + > > > > + memory@80000000 { > > > > + device_type = "memory"; > > > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > > > + clocks = <&clkcfg 26>; > > > > + }; > > > > + > > > > + soc { > > > > + }; > > > > +}; > > > > + > > > > +&serial0 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial1 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial2 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial3 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&sdcard { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&emac0 { > > > > + phy-mode = "sgmii"; > > > > + phy-handle = <&phy0>; > > > > + phy0: ethernet-phy@8 { > > > > + reg = <8>; > > > > + ti,fifo-depth = <0x01>; > > > > + }; > > > > +}; > > > > + > > > > +&emac1 { > > > > + status = "okay"; > > > > + phy-mode = "sgmii"; > > > > + phy-handle = <&phy1>; > > > > + phy1: ethernet-phy@9 { > > > > + reg = <9>; > > > > + ti,fifo-depth = <0x01>; > > > > + }; > > > > +}; > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > new file mode 100644 > > > > index 000000000000..b9819570a7d1 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > @@ -0,0 +1,329 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > > + > > > > +/dts-v1/; > > > > + > > > > +/ { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + model = "Microchip MPFS Icicle Kit"; > > > > + compatible = "microchip,mpfs-icicle-kit"; > > > > + > > > > + chosen { > > > > + }; > > > > + > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + cpu@0 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <128>; > > > > + i-cache-size = <16384>; > > > > + reg = <0>; > > > > + riscv,isa = "rv64imac"; > > > > + status = "disabled"; > > > > + > > > > + cpu0_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@1 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <1>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu1_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@2 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <2>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu2_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@3 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <3>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu3_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@4 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <4>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + cpu4_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > + soc { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + compatible = "simple-bus"; > > > > + ranges; > > > > + > > > > + cache-controller@2010000 { > > > > + compatible = "sifive,fu540-c000-ccache", "cache"; > > > > + cache-block-size = <64>; > > > > + cache-level = <2>; > > > > + cache-sets = <1024>; > > > > + cache-size = <2097152>; > > > > + cache-unified; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <1 2 3>; > > > > + reg = <0x0 0x2010000 0x0 0x1000>; > > > > + }; > > > > + > > > > + clint@2000000 { > > > > + compatible = "sifive,clint0"; > > > > + reg = <0x0 0x2000000 0x0 0xC000>; > > > > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > > > + &cpu1_intc 3 &cpu1_intc 7 > > > > + &cpu2_intc 3 &cpu2_intc 7 > > > > + &cpu3_intc 3 &cpu3_intc 7 > > > > + &cpu4_intc 3 &cpu4_intc 7>; > > > > + }; > > > > + > > > > + plic: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + compatible = "sifive,plic-1.0.0"; > > > > + reg = <0x0 0xc000000 0x0 0x4000000>; > > > > + riscv,ndev = <186>; > > > > + interrupt-controller; > > > > + interrupts-extended = <&cpu0_intc 11 > > > > + &cpu1_intc 11 &cpu1_intc 9 > > > > + &cpu2_intc 11 &cpu2_intc 9 > > > > + &cpu3_intc 11 &cpu3_intc 9 > > > > + &cpu4_intc 11 &cpu4_intc 9>; > > > > + }; > > > > + > > > > + dma@3000000 { > > > > + compatible = "sifive,fu540-c000-pdma"; > > > > + reg = <0x0 0x3000000 0x0 0x8000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <23 24 25 26 27 28 29 30>; > > > > + #dma-cells = <1>; > > > > + }; > > > > + > > > > + refclk: refclk { > > > > + compatible = "fixed-clock"; > > > > + #clock-cells = <0>; > > > > + clock-frequency = <600000000>; > > > > + clock-output-names = "msspllclk"; > > > > + }; > > > > + > > > > + clkcfg: clkcfg@20002000 { > > > > + compatible = "microchip,mpfs-clkcfg"; > > > > + reg = <0x0 0x20002000 0x0 0x1000>; > > > > + reg-names = "mss_sysreg"; > > > > + clocks = <&refclk>; > > > > + #clock-cells = <1>; > > > > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > > > > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > > > > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > > > > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > > > > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > > > > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > > > > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > > > > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > > > > + }; > > > > + > > > > + serial0: serial@20000000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20000000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <90>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 8>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial1: serial@20100000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20100000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <91>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 9>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial2: serial@20102000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20102000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <92>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 10>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial3: serial@20104000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20104000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <93>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 11>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + emmc: mmc@20008000 { > > > > + compatible = "cdns,sd4hc"; > > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <88 89>; > > > > + pinctrl-names = "default"; > > > > + clocks = <&clkcfg 6>; > > > > + bus-width = <4>; > > > > + cap-mmc-highspeed; > > > > + mmc-ddr-3_3v; > > > > + max-frequency = <200000000>; > > > > + non-removable; > > > > + no-sd; > > > > + no-sdio; > > > > + voltage-ranges = <3300 3300>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + sdcard: sdhc@20008000 { > > > > + compatible = "cdns,sd4hc"; > > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <88>; > > > > + pinctrl-names = "default"; > > > > + clocks = <&clkcfg 6>; > > > > + bus-width = <4>; > > > > + disable-wp; > > > > + cap-sd-highspeed; > > > > + card-detect-delay = <200>; > > > > + sd-uhs-sdr12; > > > > + sd-uhs-sdr25; > > > > + sd-uhs-sdr50; > > > > + sd-uhs-sdr104; > > > > + max-frequency = <200000000>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + emac0: ethernet@20110000 { > > > > + compatible = "cdns,macb"; > > > > + reg = <0x0 0x20110000 0x0 0x2000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <64 65 66 67>; > > > > + local-mac-address = [00 00 00 00 00 00]; > > > > + clocks = <&clkcfg 4>, <&clkcfg 2>; > > > > + clock-names = "pclk", "hclk"; > > > > + status = "disabled"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > + > > > > + emac1: ethernet@20112000 { > > > > + compatible = "cdns,macb"; > > > > + reg = <0x0 0x20112000 0x0 0x2000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <70 71 72 73>; > > > > + mac-address = [00 00 00 00 00 00]; > > > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > > > + status = "disabled"; > > > > + clock-names = "pclk", "hclk"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > + > > > > + }; > > > > +}; > > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Regards, > Atish -- Regards, Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board 2021-04-18 3:36 ` Atish Patra 2021-04-18 4:24 ` Atish Patra @ 2021-04-18 18:39 ` Vitaly Wool 1 sibling, 0 replies; 20+ messages in thread From: Vitaly Wool @ 2021-04-18 18:39 UTC (permalink / raw) To: Atish Patra Cc: Alex Ghiti, Atish Patra, LKML, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Hi Atish, On Sun, Apr 18, 2021 at 5:37 AM Atish Patra <atishp@atishpatra.org> wrote: > > On Mon, Mar 29, 2021 at 10:04 AM Vitaly Wool <vitaly.wool@konsulko.com> wrote: > > > > On Sat, Mar 27, 2021 at 6:24 PM Alex Ghiti <alex@ghiti.fr> wrote: > > > > > > Hi Atish, > > > > > > Le 3/3/21 à 3:02 PM, Atish Patra a écrit : > > > > Add initial DTS for Microchip ICICLE board having only > > > > essential devices (clocks, sdhci, ethernet, serial, etc). > > > > The device tree is based on the U-Boot patch. > > > > > > > > https://patchwork.ozlabs.org/project/uboot/patch/20201110103414.10142-6-padmarao.begari@microchip.com/ > > > > > > > > Signed-off-by: Atish Patra <atish.patra@wdc.com> > > > > --- > > > > arch/riscv/boot/dts/Makefile | 1 + > > > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > > > 4 files changed, 404 insertions(+) > > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > > > > > diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile > > > > index 7ffd502e3e7b..fe996b88319e 100644 > > > > --- a/arch/riscv/boot/dts/Makefile > > > > +++ b/arch/riscv/boot/dts/Makefile > > > > @@ -1,5 +1,6 @@ > > > > # SPDX-License-Identifier: GPL-2.0 > > > > subdir-y += sifive > > > > subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan > > > > +subdir-y += microchip > > > > > > > > obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > > > > new file mode 100644 > > > > index 000000000000..622b12771fd3 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > > @@ -0,0 +1,2 @@ > > > > +# SPDX-License-Identifier: GPL-2.0 > > > > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > > > > > I'm playing (or trying to...) with XIP_KERNEL and I had to add the > > > following to have the device tree actually builtin the kernel: > > > > > > diff --git a/arch/riscv/boot/dts/microchip/Makefile > > > b/arch/riscv/boot/dts/microchip/Makefile > > > index 622b12771fd3..855c1502d912 100644 > > > --- a/arch/riscv/boot/dts/microchip/Makefile > > > +++ b/arch/riscv/boot/dts/microchip/Makefile > > > @@ -1,2 +1,3 @@ > > > # SPDX-License-Identifier: GPL-2.0 > > > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb > > > +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > > > > > > Alex > > > > Yes, I believe this is necessary for BUILTIN_DTB to work on Polarfire, > > regardless of whether the kernel is XIP or not. > > > > But there is no usecase for BUILTIN_DTB for polarfire except XIP kernel. > The bootloaders for polarfire is capable of providing a DTB to kernel. I have hard time seeing an industrial application with a bootloader mounting a vfat partition to load a device tree file. So there has to be a less obscure and less time consuming alternative. And if the mainline kernel doesn't provide it (e. g. in the form of support for BUILTIN_DTB) it opens up for error prone custom solutions from various vendors. Is that really what we want? Best regards, Vitaly > If XIP kernel is enabled, the following line in > arch/riscv/boot/dts/Makefile should take care of things > > > > Best regards, > > Vitaly > > > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > new file mode 100644 > > > > index 000000000000..ec79944065c9 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > > @@ -0,0 +1,72 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > > + > > > > +/dts-v1/; > > > > + > > > > +#include "microchip-mpfs.dtsi" > > > > + > > > > +/* Clock frequency (in Hz) of the rtcclk */ > > > > +#define RTCCLK_FREQ 1000000 > > > > + > > > > +/ { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + model = "Microchip PolarFire-SoC Icicle Kit"; > > > > + compatible = "microchip,mpfs-icicle-kit"; > > > > + > > > > + chosen { > > > > + stdout-path = &serial0; > > > > + }; > > > > + > > > > + cpus { > > > > + timebase-frequency = <RTCCLK_FREQ>; > > > > + }; > > > > + > > > > + memory@80000000 { > > > > + device_type = "memory"; > > > > + reg = <0x0 0x80000000 0x0 0x40000000>; > > > > + clocks = <&clkcfg 26>; > > > > + }; > > > > + > > > > + soc { > > > > + }; > > > > +}; > > > > + > > > > +&serial0 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial1 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial2 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&serial3 { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&sdcard { > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&emac0 { > > > > + phy-mode = "sgmii"; > > > > + phy-handle = <&phy0>; > > > > + phy0: ethernet-phy@8 { > > > > + reg = <8>; > > > > + ti,fifo-depth = <0x01>; > > > > + }; > > > > +}; > > > > + > > > > +&emac1 { > > > > + status = "okay"; > > > > + phy-mode = "sgmii"; > > > > + phy-handle = <&phy1>; > > > > + phy1: ethernet-phy@9 { > > > > + reg = <9>; > > > > + ti,fifo-depth = <0x01>; > > > > + }; > > > > +}; > > > > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > new file mode 100644 > > > > index 000000000000..b9819570a7d1 > > > > --- /dev/null > > > > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > @@ -0,0 +1,329 @@ > > > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > > > +/* Copyright (c) 2020 Microchip Technology Inc */ > > > > + > > > > +/dts-v1/; > > > > + > > > > +/ { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + model = "Microchip MPFS Icicle Kit"; > > > > + compatible = "microchip,mpfs-icicle-kit"; > > > > + > > > > + chosen { > > > > + }; > > > > + > > > > + cpus { > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + > > > > + cpu@0 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,e51", "sifive,rocket0", "riscv"; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <128>; > > > > + i-cache-size = <16384>; > > > > + reg = <0>; > > > > + riscv,isa = "rv64imac"; > > > > + status = "disabled"; > > > > + > > > > + cpu0_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@1 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <1>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu1_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@2 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <2>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu2_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@3 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <3>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + > > > > + cpu3_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + > > > > + cpu@4 { > > > > + clock-frequency = <0>; > > > > + compatible = "sifive,u54-mc", "sifive,rocket0", "riscv"; > > > > + d-cache-block-size = <64>; > > > > + d-cache-sets = <64>; > > > > + d-cache-size = <32768>; > > > > + d-tlb-sets = <1>; > > > > + d-tlb-size = <32>; > > > > + device_type = "cpu"; > > > > + i-cache-block-size = <64>; > > > > + i-cache-sets = <64>; > > > > + i-cache-size = <32768>; > > > > + i-tlb-sets = <1>; > > > > + i-tlb-size = <32>; > > > > + mmu-type = "riscv,sv39"; > > > > + reg = <4>; > > > > + riscv,isa = "rv64imafdc"; > > > > + tlb-split; > > > > + status = "okay"; > > > > + cpu4_intc: interrupt-controller { > > > > + #interrupt-cells = <1>; > > > > + compatible = "riscv,cpu-intc"; > > > > + interrupt-controller; > > > > + }; > > > > + }; > > > > + }; > > > > + > > > > + soc { > > > > + #address-cells = <2>; > > > > + #size-cells = <2>; > > > > + compatible = "simple-bus"; > > > > + ranges; > > > > + > > > > + cache-controller@2010000 { > > > > + compatible = "sifive,fu540-c000-ccache", "cache"; > > > > + cache-block-size = <64>; > > > > + cache-level = <2>; > > > > + cache-sets = <1024>; > > > > + cache-size = <2097152>; > > > > + cache-unified; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <1 2 3>; > > > > + reg = <0x0 0x2010000 0x0 0x1000>; > > > > + }; > > > > + > > > > + clint@2000000 { > > > > + compatible = "sifive,clint0"; > > > > + reg = <0x0 0x2000000 0x0 0xC000>; > > > > + interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 > > > > + &cpu1_intc 3 &cpu1_intc 7 > > > > + &cpu2_intc 3 &cpu2_intc 7 > > > > + &cpu3_intc 3 &cpu3_intc 7 > > > > + &cpu4_intc 3 &cpu4_intc 7>; > > > > + }; > > > > + > > > > + plic: interrupt-controller@c000000 { > > > > + #interrupt-cells = <1>; > > > > + compatible = "sifive,plic-1.0.0"; > > > > + reg = <0x0 0xc000000 0x0 0x4000000>; > > > > + riscv,ndev = <186>; > > > > + interrupt-controller; > > > > + interrupts-extended = <&cpu0_intc 11 > > > > + &cpu1_intc 11 &cpu1_intc 9 > > > > + &cpu2_intc 11 &cpu2_intc 9 > > > > + &cpu3_intc 11 &cpu3_intc 9 > > > > + &cpu4_intc 11 &cpu4_intc 9>; > > > > + }; > > > > + > > > > + dma@3000000 { > > > > + compatible = "sifive,fu540-c000-pdma"; > > > > + reg = <0x0 0x3000000 0x0 0x8000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <23 24 25 26 27 28 29 30>; > > > > + #dma-cells = <1>; > > > > + }; > > > > + > > > > + refclk: refclk { > > > > + compatible = "fixed-clock"; > > > > + #clock-cells = <0>; > > > > + clock-frequency = <600000000>; > > > > + clock-output-names = "msspllclk"; > > > > + }; > > > > + > > > > + clkcfg: clkcfg@20002000 { > > > > + compatible = "microchip,mpfs-clkcfg"; > > > > + reg = <0x0 0x20002000 0x0 0x1000>; > > > > + reg-names = "mss_sysreg"; > > > > + clocks = <&refclk>; > > > > + #clock-cells = <1>; > > > > + clock-output-names = "cpu", "axi", "ahb", "envm", /* 0-3 */ > > > > + "mac0", "mac1", "mmc", "timer", /* 4-7 */ > > > > + "mmuart0", "mmuart1", "mmuart2", "mmuart3", /* 8-11 */ > > > > + "mmuart4", "spi0", "spi1", "i2c0", /* 12-15 */ > > > > + "i2c1", "can0", "can1", "usb", /* 16-19 */ > > > > + "rsvd", "rtc", "qspi", "gpio0", /* 20-23 */ > > > > + "gpio1", "gpio2", "ddrc", "fic0", /* 24-27 */ > > > > + "fic1", "fic2", "fic3", "athena", "cfm"; /* 28-32 */ > > > > + }; > > > > + > > > > + serial0: serial@20000000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20000000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <90>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 8>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial1: serial@20100000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20100000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <91>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 9>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial2: serial@20102000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20102000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <92>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 10>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + serial3: serial@20104000 { > > > > + compatible = "ns16550a"; > > > > + reg = <0x0 0x20104000 0x0 0x400>; > > > > + reg-io-width = <4>; > > > > + reg-shift = <2>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <93>; > > > > + current-speed = <115200>; > > > > + clocks = <&clkcfg 11>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + emmc: mmc@20008000 { > > > > + compatible = "cdns,sd4hc"; > > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <88 89>; > > > > + pinctrl-names = "default"; > > > > + clocks = <&clkcfg 6>; > > > > + bus-width = <4>; > > > > + cap-mmc-highspeed; > > > > + mmc-ddr-3_3v; > > > > + max-frequency = <200000000>; > > > > + non-removable; > > > > + no-sd; > > > > + no-sdio; > > > > + voltage-ranges = <3300 3300>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + sdcard: sdhc@20008000 { > > > > + compatible = "cdns,sd4hc"; > > > > + reg = <0x0 0x20008000 0x0 0x1000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <88>; > > > > + pinctrl-names = "default"; > > > > + clocks = <&clkcfg 6>; > > > > + bus-width = <4>; > > > > + disable-wp; > > > > + cap-sd-highspeed; > > > > + card-detect-delay = <200>; > > > > + sd-uhs-sdr12; > > > > + sd-uhs-sdr25; > > > > + sd-uhs-sdr50; > > > > + sd-uhs-sdr104; > > > > + max-frequency = <200000000>; > > > > + status = "disabled"; > > > > + }; > > > > + > > > > + emac0: ethernet@20110000 { > > > > + compatible = "cdns,macb"; > > > > + reg = <0x0 0x20110000 0x0 0x2000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <64 65 66 67>; > > > > + local-mac-address = [00 00 00 00 00 00]; > > > > + clocks = <&clkcfg 4>, <&clkcfg 2>; > > > > + clock-names = "pclk", "hclk"; > > > > + status = "disabled"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > + > > > > + emac1: ethernet@20112000 { > > > > + compatible = "cdns,macb"; > > > > + reg = <0x0 0x20112000 0x0 0x2000>; > > > > + interrupt-parent = <&plic>; > > > > + interrupts = <70 71 72 73>; > > > > + mac-address = [00 00 00 00 00 00]; > > > > + clocks = <&clkcfg 5>, <&clkcfg 2>; > > > > + status = "disabled"; > > > > + clock-names = "pclk", "hclk"; > > > > + #address-cells = <1>; > > > > + #size-cells = <0>; > > > > + }; > > > > + > > > > + }; > > > > +}; > > > > > > > > > > _______________________________________________ > > > linux-riscv mailing list > > > linux-riscv@lists.infradead.org > > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Regards, > Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (2 preceding siblings ...) 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra @ 2021-03-03 20:02 ` Atish Patra 2021-03-03 20:02 ` [PATCH v4 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra 2021-03-30 4:17 ` [PATCH v4 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 5 siblings, 0 replies; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Atish Patra, Anup Patel, Bin Meng, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly Enable Microchip PolarFire ICICLE soc config in defconfig. It allows the default upstream kernel to boot on PolarFire ICICLE board. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Bin Meng <bin.meng@windriver.com> --- arch/riscv/configs/defconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 6c0625aa96c7..1f2be234b11c 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -16,6 +16,7 @@ CONFIG_EXPERT=y CONFIG_BPF_SYSCALL=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_VIRT=y +CONFIG_SOC_MICROCHIP_POLARFIRE=y CONFIG_SMP=y CONFIG_HOTPLUG_CPU=y CONFIG_JUMP_LABEL=y @@ -82,6 +83,9 @@ CONFIG_USB_OHCI_HCD=y CONFIG_USB_OHCI_HCD_PLATFORM=y CONFIG_USB_STORAGE=y CONFIG_USB_UAS=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_CADENCE=y CONFIG_MMC=y CONFIG_MMC_SPI=y CONFIG_RTC_CLASS=y -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v4 5/5] MAINTAINERS: add microchip polarfire soc support 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (3 preceding siblings ...) 2021-03-03 20:02 ` [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra @ 2021-03-03 20:02 ` Atish Patra 2021-03-30 4:17 ` [PATCH v4 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 5 siblings, 0 replies; 20+ messages in thread From: Atish Patra @ 2021-03-03 20:02 UTC (permalink / raw) To: linux-kernel Cc: Conor Dooley, Albert Ou, Alistair Francis, Anup Patel, Atish Patra, Björn Töpel, devicetree, linux-riscv, Palmer Dabbelt, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly From: Conor Dooley <conor.dooley@microchip.com> Add Cyril Jean and Lewis Hanly as maintainers for the Microchip SoC directory Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d92f85ca831d..cf186eca1784 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -15358,6 +15358,14 @@ F: arch/riscv/ N: riscv K: riscv +RISC-V/MICROCHIP POLARFIRE SOC SUPPORT +M: Lewis Hanly <lewis.hanly@microchip.com> +M: Cyril Jean <cyril.jean@microchip.com> +L: linux-riscv@lists.infradead.org +S: Supported +F: drivers/soc/microchip/ +F: include/soc/microchip/mpfs.h + RNBD BLOCK DRIVERS M: Danil Kipnis <danil.kipnis@cloud.ionos.com> M: Jack Wang <jinpu.wang@cloud.ionos.com> -- 2.25.1 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/5] Add Microchip PolarFire Soc Support 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra ` (4 preceding siblings ...) 2021-03-03 20:02 ` [PATCH v4 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra @ 2021-03-30 4:17 ` Palmer Dabbelt 2021-04-18 3:26 ` Atish Patra 5 siblings, 1 reply; 20+ messages in thread From: Palmer Dabbelt @ 2021-03-30 4:17 UTC (permalink / raw) To: Atish Patra Cc: linux-kernel, Atish Patra, aou, Alistair Francis, Anup Patel, bjorn, devicetree, linux-riscv, Paul Walmsley, robh+dt, Conor.Dooley, daire.mcnamara, Ivan.Griffin, Lewis.Hanly On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote: > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. > It is rebased on v5.12-rc1 and depends on clock support. > Only MMC and ethernet drivers are enabled via this series. > The idea here is to add the foundational patches so that other drivers > can be added to on top of this. The device tree may change based on > feedback on bindings of individual driver support patches. > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. > It depends on the updated clock-series[2] and macb fix[3]. > The series is also tested by Lewis from Microchip. > > The series can also be found at. > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html > [2] https://www.spinics.net/lists/linux-clk/msg54579.html > > Changes from v3->v4: > 1. Fixed few DT specific issues. > 2. Rebased on top of new clock driver. > 3. SD card functionality is verified. > > Changes from v2->v3: > 1. Fixed a typo in dt binding. > 2. Included MAINTAINERS entry for PolarFire SoC. > 3. Improved the dts file by using lowercase clock names and keeping phy > details in board specific dts file. > > Changes from v1->v2: > 1. Modified the DT to match the device tree in U-Boot. > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled > as it allows larger storage option for linux distros. > > Atish Patra (4): > RISC-V: Add Microchip PolarFire SoC kconfig option > dt-bindings: riscv: microchip: Add YAML documentation for the > PolarFire SoC > RISC-V: Initial DTS for Microchip ICICLE board > RISC-V: Enable Microchip PolarFire ICICLE SoC > > Conor Dooley (1): > MAINTAINERS: add microchip polarfire soc support > > .../devicetree/bindings/riscv/microchip.yaml | 27 ++ > MAINTAINERS | 8 + > arch/riscv/Kconfig.socs | 7 + > arch/riscv/boot/dts/Makefile | 1 + > arch/riscv/boot/dts/microchip/Makefile | 2 + > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > arch/riscv/configs/defconfig | 4 + > 8 files changed, 450 insertions(+) > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi I had this left in my inbox waiting for either some reviews to come in or a v2, but I don't see any. Did I miss something? ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/5] Add Microchip PolarFire Soc Support 2021-03-30 4:17 ` [PATCH v4 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt @ 2021-04-18 3:26 ` Atish Patra 2021-04-22 22:33 ` Atish Patra 0 siblings, 1 reply; 20+ messages in thread From: Atish Patra @ 2021-04-18 3:26 UTC (permalink / raw) To: Palmer Dabbelt Cc: Atish Patra, linux-kernel@vger.kernel.org List, Albert Ou, Alistair Francis, Anup Patel, bjorn, devicetree, linux-riscv, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote: > > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. > > It is rebased on v5.12-rc1 and depends on clock support. > > Only MMC and ethernet drivers are enabled via this series. > > The idea here is to add the foundational patches so that other drivers > > can be added to on top of this. The device tree may change based on > > feedback on bindings of individual driver support patches. > > > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. > > It depends on the updated clock-series[2] and macb fix[3]. > > The series is also tested by Lewis from Microchip. > > > > The series can also be found at. > > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 > > > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html > > [2] https://www.spinics.net/lists/linux-clk/msg54579.html > > > > Changes from v3->v4: > > 1. Fixed few DT specific issues. > > 2. Rebased on top of new clock driver. > > 3. SD card functionality is verified. > > > > Changes from v2->v3: > > 1. Fixed a typo in dt binding. > > 2. Included MAINTAINERS entry for PolarFire SoC. > > 3. Improved the dts file by using lowercase clock names and keeping phy > > details in board specific dts file. > > > > Changes from v1->v2: > > 1. Modified the DT to match the device tree in U-Boot. > > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled > > as it allows larger storage option for linux distros. > > > > Atish Patra (4): > > RISC-V: Add Microchip PolarFire SoC kconfig option > > dt-bindings: riscv: microchip: Add YAML documentation for the > > PolarFire SoC > > RISC-V: Initial DTS for Microchip ICICLE board > > RISC-V: Enable Microchip PolarFire ICICLE SoC > > > > Conor Dooley (1): > > MAINTAINERS: add microchip polarfire soc support > > > > .../devicetree/bindings/riscv/microchip.yaml | 27 ++ > > MAINTAINERS | 8 + > > arch/riscv/Kconfig.socs | 7 + > > arch/riscv/boot/dts/Makefile | 1 + > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > arch/riscv/configs/defconfig | 4 + > > 8 files changed, 450 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > I had this left in my inbox waiting for either some reviews to come in or a v2, > but I don't see any. Did I miss something? > Sorry for the late reply. I am on vacation until May. I think I saw all the patches have already been reviewed. Let me know if it is not the case. > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv -- Regards, Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/5] Add Microchip PolarFire Soc Support 2021-04-18 3:26 ` Atish Patra @ 2021-04-22 22:33 ` Atish Patra 2021-04-23 1:37 ` Palmer Dabbelt 0 siblings, 1 reply; 20+ messages in thread From: Atish Patra @ 2021-04-22 22:33 UTC (permalink / raw) To: Palmer Dabbelt Cc: Atish Patra, linux-kernel@vger.kernel.org List, Albert Ou, Alistair Francis, Anup Patel, Björn Töpel, devicetree, linux-riscv, Paul Walmsley, Rob Herring, Conor.Dooley, Daire McNamara, Ivan.Griffin, Lewis.Hanly On Sat, Apr 17, 2021 at 8:26 PM Atish Patra <atishp@atishpatra.org> wrote: > > On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: > > > > On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote: > > > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. > > > It is rebased on v5.12-rc1 and depends on clock support. > > > Only MMC and ethernet drivers are enabled via this series. > > > The idea here is to add the foundational patches so that other drivers > > > can be added to on top of this. The device tree may change based on > > > feedback on bindings of individual driver support patches. > > > > > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. > > > It depends on the updated clock-series[2] and macb fix[3]. > > > The series is also tested by Lewis from Microchip. > > > > > > The series can also be found at. > > > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 > > > > > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html > > > [2] https://www.spinics.net/lists/linux-clk/msg54579.html > > > > > > Changes from v3->v4: > > > 1. Fixed few DT specific issues. > > > 2. Rebased on top of new clock driver. > > > 3. SD card functionality is verified. > > > > > > Changes from v2->v3: > > > 1. Fixed a typo in dt binding. > > > 2. Included MAINTAINERS entry for PolarFire SoC. > > > 3. Improved the dts file by using lowercase clock names and keeping phy > > > details in board specific dts file. > > > > > > Changes from v1->v2: > > > 1. Modified the DT to match the device tree in U-Boot. > > > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled > > > as it allows larger storage option for linux distros. > > > > > > Atish Patra (4): > > > RISC-V: Add Microchip PolarFire SoC kconfig option > > > dt-bindings: riscv: microchip: Add YAML documentation for the > > > PolarFire SoC > > > RISC-V: Initial DTS for Microchip ICICLE board > > > RISC-V: Enable Microchip PolarFire ICICLE SoC > > > > > > Conor Dooley (1): > > > MAINTAINERS: add microchip polarfire soc support > > > > > > .../devicetree/bindings/riscv/microchip.yaml | 27 ++ > > > MAINTAINERS | 8 + > > > arch/riscv/Kconfig.socs | 7 + > > > arch/riscv/boot/dts/Makefile | 1 + > > > arch/riscv/boot/dts/microchip/Makefile | 2 + > > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ > > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ > > > arch/riscv/configs/defconfig | 4 + > > > 8 files changed, 450 insertions(+) > > > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml > > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts > > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi > > > > I had this left in my inbox waiting for either some reviews to come in or a v2, > > but I don't see any. Did I miss something? > > > Sorry for the late reply. I am on vacation until May. I think I saw > all the patches have already been reviewed. > Let me know if it is not the case. > I cross checked and all the patches are reviewed-by. @palmer: Is it possible to take this series for 5.13 MW ? > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > -- > Regards, > Atish -- Regards, Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/5] Add Microchip PolarFire Soc Support 2021-04-22 22:33 ` Atish Patra @ 2021-04-23 1:37 ` Palmer Dabbelt 2021-04-23 8:44 ` Conor.Dooley 0 siblings, 1 reply; 20+ messages in thread From: Palmer Dabbelt @ 2021-04-23 1:37 UTC (permalink / raw) To: atishp Cc: Atish Patra, linux-kernel, aou, Alistair Francis, Anup Patel, bjorn, devicetree, linux-riscv, Paul Walmsley, robh+dt, Conor.Dooley, daire.mcnamara, Ivan.Griffin, Lewis.Hanly On Thu, 22 Apr 2021 15:33:39 PDT (-0700), atishp@atishpatra.org wrote: > On Sat, Apr 17, 2021 at 8:26 PM Atish Patra <atishp@atishpatra.org> wrote: >> >> On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt <palmer@dabbelt.com> wrote: >> > >> > On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote: >> > > This series adds minimal support for Microchip Polar Fire Soc Icicle kit. >> > > It is rebased on v5.12-rc1 and depends on clock support. >> > > Only MMC and ethernet drivers are enabled via this series. >> > > The idea here is to add the foundational patches so that other drivers >> > > can be added to on top of this. The device tree may change based on >> > > feedback on bindings of individual driver support patches. >> > > >> > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. >> > > It depends on the updated clock-series[2] and macb fix[3]. >> > > The series is also tested by Lewis from Microchip. >> > > >> > > The series can also be found at. >> > > https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 >> > > >> > > [1] https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html >> > > [2] https://www.spinics.net/lists/linux-clk/msg54579.html >> > > >> > > Changes from v3->v4: >> > > 1. Fixed few DT specific issues. >> > > 2. Rebased on top of new clock driver. >> > > 3. SD card functionality is verified. >> > > >> > > Changes from v2->v3: >> > > 1. Fixed a typo in dt binding. >> > > 2. Included MAINTAINERS entry for PolarFire SoC. >> > > 3. Improved the dts file by using lowercase clock names and keeping phy >> > > details in board specific dts file. >> > > >> > > Changes from v1->v2: >> > > 1. Modified the DT to match the device tree in U-Boot. >> > > 2. Added both eMMC & SDcard entries in DT. However, SD card is only enabled >> > > as it allows larger storage option for linux distros. >> > > >> > > Atish Patra (4): >> > > RISC-V: Add Microchip PolarFire SoC kconfig option >> > > dt-bindings: riscv: microchip: Add YAML documentation for the >> > > PolarFire SoC >> > > RISC-V: Initial DTS for Microchip ICICLE board >> > > RISC-V: Enable Microchip PolarFire ICICLE SoC >> > > >> > > Conor Dooley (1): >> > > MAINTAINERS: add microchip polarfire soc support >> > > >> > > .../devicetree/bindings/riscv/microchip.yaml | 27 ++ >> > > MAINTAINERS | 8 + >> > > arch/riscv/Kconfig.socs | 7 + >> > > arch/riscv/boot/dts/Makefile | 1 + >> > > arch/riscv/boot/dts/microchip/Makefile | 2 + >> > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ >> > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 ++++++++++++++++++ >> > > arch/riscv/configs/defconfig | 4 + >> > > 8 files changed, 450 insertions(+) >> > > create mode 100644 Documentation/devicetree/bindings/riscv/microchip.yaml >> > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile >> > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts >> > > create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi >> > >> > I had this left in my inbox waiting for either some reviews to come in or a v2, >> > but I don't see any. Did I miss something? >> > >> Sorry for the late reply. I am on vacation until May. I think I saw >> all the patches have already been reviewed. >> Let me know if it is not the case. >> > I cross checked and all the patches are reviewed-by. > @palmer: Is it possible to take this series for 5.13 MW ? I still don't see any reviews for the mailbox driver, did it just get lost on the way to me? > >> > _______________________________________________ >> > linux-riscv mailing list >> > linux-riscv@lists.infradead.org >> > http://lists.infradead.org/mailman/listinfo/linux-riscv >> >> >> >> -- >> Regards, >> Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v4 0/5] Add Microchip PolarFire Soc Support 2021-04-23 1:37 ` Palmer Dabbelt @ 2021-04-23 8:44 ` Conor.Dooley 0 siblings, 0 replies; 20+ messages in thread From: Conor.Dooley @ 2021-04-23 8:44 UTC (permalink / raw) To: palmer, atishp Cc: Atish.Patra, linux-kernel, aou, Alistair.Francis, Anup.Patel, bjorn, devicetree, linux-riscv, paul.walmsley, robh+dt, Daire.McNamara, Ivan.Griffin, Lewis.Hanly On 23/04/2021 02:37, Palmer Dabbelt wrote: > EXTERNAL EMAIL: Do not click links or open attachments unless you know > the content is safe > > On Thu, 22 Apr 2021 15:33:39 PDT (-0700), atishp@atishpatra.org wrote: >> On Sat, Apr 17, 2021 at 8:26 PM Atish Patra <atishp@atishpatra.org> >> wrote: >>> >>> On Mon, Mar 29, 2021 at 9:17 PM Palmer Dabbelt <palmer@dabbelt.com> >>> wrote: >>> > >>> > On Wed, 03 Mar 2021 12:02:48 PST (-0800), Atish Patra wrote: >>> > > This series adds minimal support for Microchip Polar Fire Soc >>> Icicle kit. >>> > > It is rebased on v5.12-rc1 and depends on clock support. >>> > > Only MMC and ethernet drivers are enabled via this series. >>> > > The idea here is to add the foundational patches so that other >>> drivers >>> > > can be added to on top of this. The device tree may change based on >>> > > feedback on bindings of individual driver support patches. >>> > > >>> > > This series has been tested on Qemu and Polar Fire Soc Icicle kit. >>> > > It depends on the updated clock-series[2] and macb fix[3]. >>> > > The series is also tested by Lewis from Microchip. >>> > > >>> > > The series can also be found at. >>> > > >>> https://github.com/atishp04/linux/tree/polarfire_support_upstream_v4 >>> > > >>> > > [1] >>> https://lists.nongnu.org/archive/html/qemu-devel/2020-10/msg08582.html >>> > > [2] https://www.spinics.net/lists/linux-clk/msg54579.html >>> > > >>> > > Changes from v3->v4: >>> > > 1. Fixed few DT specific issues. >>> > > 2. Rebased on top of new clock driver. >>> > > 3. SD card functionality is verified. >>> > > >>> > > Changes from v2->v3: >>> > > 1. Fixed a typo in dt binding. >>> > > 2. Included MAINTAINERS entry for PolarFire SoC. >>> > > 3. Improved the dts file by using lowercase clock names and >>> keeping phy >>> > > details in board specific dts file. >>> > > >>> > > Changes from v1->v2: >>> > > 1. Modified the DT to match the device tree in U-Boot. >>> > > 2. Added both eMMC & SDcard entries in DT. However, SD card is >>> only enabled >>> > > as it allows larger storage option for linux distros. >>> > > >>> > > Atish Patra (4): >>> > > RISC-V: Add Microchip PolarFire SoC kconfig option >>> > > dt-bindings: riscv: microchip: Add YAML documentation for the >>> > > PolarFire SoC >>> > > RISC-V: Initial DTS for Microchip ICICLE board >>> > > RISC-V: Enable Microchip PolarFire ICICLE SoC >>> > > >>> > > Conor Dooley (1): >>> > > MAINTAINERS: add microchip polarfire soc support >>> > > >>> > > .../devicetree/bindings/riscv/microchip.yaml | 27 ++ >>> > > MAINTAINERS | 8 + >>> > > arch/riscv/Kconfig.socs | 7 + >>> > > arch/riscv/boot/dts/Makefile | 1 + >>> > > arch/riscv/boot/dts/microchip/Makefile | 2 + >>> > > .../microchip/microchip-mpfs-icicle-kit.dts | 72 ++++ >>> > > .../boot/dts/microchip/microchip-mpfs.dtsi | 329 >>> ++++++++++++++++++ >>> > > arch/riscv/configs/defconfig | 4 + >>> > > 8 files changed, 450 insertions(+) >>> > > create mode 100644 >>> Documentation/devicetree/bindings/riscv/microchip.yaml >>> > > create mode 100644 arch/riscv/boot/dts/microchip/Makefile >>> > > create mode 100644 >>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts >>> > > create mode 100644 >>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi >>> > >>> > I had this left in my inbox waiting for either some reviews to >>> come in or a v2, >>> > but I don't see any. Did I miss something? >>> > >>> Sorry for the late reply. I am on vacation until May. I think I saw >>> all the patches have already been reviewed. >>> Let me know if it is not the case. >>> >> I cross checked and all the patches are reviewed-by. >> @palmer: Is it possible to take this series for 5.13 MW ? > > I still don't see any reviews for the mailbox driver, did it just get > lost on the way to me? the mailbox driver has reviewed-by tags on two of the five patches (rob on the dt-binding entries). v6 was set on the 23rd but hasn't got any attention on the other three patches yet however that's not in this patch set, only depends on it > >> >>> > _______________________________________________ >>> > linux-riscv mailing list >>> > linux-riscv@lists.infradead.org >>> > http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >>> >>> >>> -- >>> Regards, >>> Atish ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-04-23 8:44 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-03 20:02 [PATCH v4 0/5] Add Microchip PolarFire Soc Support Atish Patra 2021-03-03 20:02 ` [PATCH v4 1/5] RISC-V: Add Microchip PolarFire SoC kconfig option Atish Patra 2021-03-03 20:02 ` [PATCH v4 2/5] dt-bindings: riscv: microchip: Add YAML documentation for the PolarFire SoC Atish Patra 2021-03-08 20:11 ` Rob Herring 2021-03-03 20:02 ` [PATCH v4 3/5] RISC-V: Initial DTS for Microchip ICICLE board Atish Patra 2021-03-09 10:56 ` Ben Dooks [not found] ` <DM6PR11MB3770E7FA8121AA91D9EDC4FEE5929@DM6PR11MB3770.namprd11.prod.outlook.com> 2021-03-09 19:34 ` Atish Patra 2021-03-22 6:04 ` Bin Meng 2021-03-27 17:22 ` Alex Ghiti 2021-03-28 15:22 ` Vitaly Wool 2021-04-18 3:36 ` Atish Patra 2021-04-18 4:24 ` Atish Patra 2021-04-18 18:39 ` Vitaly Wool 2021-03-03 20:02 ` [PATCH v4 4/5] RISC-V: Enable Microchip PolarFire ICICLE SoC Atish Patra 2021-03-03 20:02 ` [PATCH v4 5/5] MAINTAINERS: add microchip polarfire soc support Atish Patra 2021-03-30 4:17 ` [PATCH v4 0/5] Add Microchip PolarFire Soc Support Palmer Dabbelt 2021-04-18 3:26 ` Atish Patra 2021-04-22 22:33 ` Atish Patra 2021-04-23 1:37 ` Palmer Dabbelt 2021-04-23 8:44 ` Conor.Dooley
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