* [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register
2021-06-04 10:57 [RESEND PATCH net-next v5 0/3] Enable 2.5Gbps speed for stmmac Michael Sit Wei Hong
@ 2021-06-04 10:57 ` Michael Sit Wei Hong
2021-06-04 11:51 ` Vladimir Oltean
2021-06-04 10:57 ` [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller Michael Sit Wei Hong
2021-06-04 10:57 ` [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed Michael Sit Wei Hong
2 siblings, 1 reply; 8+ messages in thread
From: Michael Sit Wei Hong @ 2021-06-04 10:57 UTC (permalink / raw)
To: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, michael.wei.hong.sit, linux-stm32,
linux-arm-kernel, linux-kernel, vladimir.oltean
From: Voon Weifeng <weifeng.voon@intel.com>
This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
a mdio ADHOC register which can be configured in the bios menu.
As PHY interface might be different for 1G and 2.5G, the mdio bus need be
ready to check the link speed and select the PHY interface before probing
the xPCS.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
---
drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
.../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 64 ++++++++++---------
3 files changed, 43 insertions(+), 29 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
index b6cd43eda7ac..fd7212afc543 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
@@ -311,6 +311,7 @@ enum stmmac_state {
int stmmac_mdio_unregister(struct net_device *ndev);
int stmmac_mdio_register(struct net_device *ndev);
int stmmac_mdio_reset(struct mii_bus *mii);
+int stmmac_xpcs_setup(struct mii_bus *mii);
void stmmac_set_ethtool_ops(struct net_device *netdev);
void stmmac_ptp_register(struct stmmac_priv *priv);
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6d41dd6f9f7a..c1331c07623d 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -6991,6 +6991,12 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->mdio_bus_data->has_xpcs) {
+ ret = stmmac_xpcs_setup(priv->mii);
+ if (ret)
+ goto error_xpcs_setup;
+ }
+
ret = stmmac_phy_setup(priv);
if (ret) {
netdev_err(ndev, "failed to setup phy (%d)\n", ret);
@@ -7027,6 +7033,7 @@ int stmmac_dvr_probe(struct device *device,
unregister_netdev(ndev);
error_netdev_register:
phylink_destroy(priv->phylink);
+error_xpcs_setup:
error_phy_setup:
if (priv->hw->pcs != STMMAC_PCS_TBI &&
priv->hw->pcs != STMMAC_PCS_RTBI)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index 6312a152c8ad..bc900e240da2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -397,6 +397,41 @@ int stmmac_mdio_reset(struct mii_bus *bus)
return 0;
}
+int stmmac_xpcs_setup(struct mii_bus *bus)
+{
+ int mode, addr;
+ struct net_device *ndev = bus->priv;
+ struct mdio_xpcs_args *xpcs;
+ struct stmmac_priv *priv;
+ struct mdio_device *mdiodev;
+
+ priv = netdev_priv(ndev);
+ mode = priv->plat->phy_interface;
+
+ /* Try to probe the XPCS by scanning all addresses. */
+ for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+ mdiodev = mdio_device_create(bus, addr);
+ if (IS_ERR(mdiodev))
+ continue;
+
+ xpcs = xpcs_create(mdiodev, mode);
+ if (IS_ERR_OR_NULL(xpcs)) {
+ mdio_device_free(mdiodev);
+ continue;
+ }
+
+ priv->hw->xpcs = xpcs;
+ break;
+ }
+
+ if (!priv->hw->xpcs) {
+ dev_warn(priv->device, "No xPCS found\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
/**
* stmmac_mdio_register
* @ndev: net device structure
@@ -501,40 +536,11 @@ int stmmac_mdio_register(struct net_device *ndev)
goto no_phy_found;
}
- /* Try to probe the XPCS by scanning all addresses. */
- if (mdio_bus_data->has_xpcs) {
- int mode = priv->plat->phy_interface;
- struct mdio_device *mdiodev;
- struct mdio_xpcs_args *xpcs;
-
- for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
- mdiodev = mdio_device_create(new_bus, addr);
- if (IS_ERR(mdiodev))
- continue;
-
- xpcs = xpcs_create(mdiodev, mode);
- if (IS_ERR_OR_NULL(xpcs)) {
- mdio_device_free(mdiodev);
- continue;
- }
-
- priv->hw->xpcs = xpcs;
- break;
- }
-
- if (!priv->hw->xpcs) {
- dev_warn(dev, "No XPCS found\n");
- err = -ENODEV;
- goto no_xpcs_found;
- }
- }
-
bus_register_done:
priv->mii = new_bus;
return 0;
-no_xpcs_found:
no_phy_found:
mdiobus_unregister(new_bus);
bus_register_fail:
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register
2021-06-04 10:57 ` [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register Michael Sit Wei Hong
@ 2021-06-04 11:51 ` Vladimir Oltean
2021-06-04 13:08 ` Vladimir Oltean
0 siblings, 1 reply; 8+ messages in thread
From: Vladimir Oltean @ 2021-06-04 11:51 UTC (permalink / raw)
To: Michael Sit Wei Hong
Cc: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, linux-stm32, linux-arm-kernel, linux-kernel
On Fri, Jun 04, 2021 at 06:57:31PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <weifeng.voon@intel.com>
>
> This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
> link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
> a mdio ADHOC register which can be configured in the bios menu.
> As PHY interface might be different for 1G and 2.5G, the mdio bus need be
> ready to check the link speed and select the PHY interface before probing
> the xPCS.
>
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> ---
> drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
> .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
> .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 64 ++++++++++---------
> 3 files changed, 43 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> index b6cd43eda7ac..fd7212afc543 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> @@ -311,6 +311,7 @@ enum stmmac_state {
> int stmmac_mdio_unregister(struct net_device *ndev);
> int stmmac_mdio_register(struct net_device *ndev);
> int stmmac_mdio_reset(struct mii_bus *mii);
> +int stmmac_xpcs_setup(struct mii_bus *mii);
> void stmmac_set_ethtool_ops(struct net_device *netdev);
>
> void stmmac_ptp_register(struct stmmac_priv *priv);
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> index 6d41dd6f9f7a..c1331c07623d 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> @@ -6991,6 +6991,12 @@ int stmmac_dvr_probe(struct device *device,
> }
> }
>
> + if (priv->plat->mdio_bus_data->has_xpcs) {
stmmac_mdio_register has:
if (!mdio_bus_data)
return 0;
which suggests that some platforms might not populate priv->plat->mdio_bus_data.
Are you sure it is safe to go straight to dereferencing mdio_bus_data->has_xpcs
in the common driver probe function?
> + ret = stmmac_xpcs_setup(priv->mii);
> + if (ret)
> + goto error_xpcs_setup;
> + }
> +
> ret = stmmac_phy_setup(priv);
> if (ret) {
> netdev_err(ndev, "failed to setup phy (%d)\n", ret);
> @@ -7027,6 +7033,7 @@ int stmmac_dvr_probe(struct device *device,
> unregister_netdev(ndev);
> error_netdev_register:
> phylink_destroy(priv->phylink);
> +error_xpcs_setup:
> error_phy_setup:
> if (priv->hw->pcs != STMMAC_PCS_TBI &&
> priv->hw->pcs != STMMAC_PCS_RTBI)
> diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> index 6312a152c8ad..bc900e240da2 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
> @@ -397,6 +397,41 @@ int stmmac_mdio_reset(struct mii_bus *bus)
> return 0;
> }
>
> +int stmmac_xpcs_setup(struct mii_bus *bus)
> +{
> + int mode, addr;
Can you please sort the variables in decreasing order of line length?
Also, "mode" can be of the phy_interface_t type.
> + struct net_device *ndev = bus->priv;
> + struct mdio_xpcs_args *xpcs;
> + struct stmmac_priv *priv;
> + struct mdio_device *mdiodev;
> +
> + priv = netdev_priv(ndev);
> + mode = priv->plat->phy_interface;
> +
> + /* Try to probe the XPCS by scanning all addresses. */
> + for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
> + mdiodev = mdio_device_create(bus, addr);
> + if (IS_ERR(mdiodev))
> + continue;
> +
> + xpcs = xpcs_create(mdiodev, mode);
> + if (IS_ERR_OR_NULL(xpcs)) {
> + mdio_device_free(mdiodev);
> + continue;
> + }
> +
> + priv->hw->xpcs = xpcs;
> + break;
> + }
> +
> + if (!priv->hw->xpcs) {
> + dev_warn(priv->device, "No xPCS found\n");
> + return -ENODEV;
> + }
> +
> + return 0;
> +}
> +
> /**
> * stmmac_mdio_register
> * @ndev: net device structure
> @@ -501,40 +536,11 @@ int stmmac_mdio_register(struct net_device *ndev)
> goto no_phy_found;
> }
>
> - /* Try to probe the XPCS by scanning all addresses. */
> - if (mdio_bus_data->has_xpcs) {
> - int mode = priv->plat->phy_interface;
> - struct mdio_device *mdiodev;
> - struct mdio_xpcs_args *xpcs;
> -
> - for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
> - mdiodev = mdio_device_create(new_bus, addr);
> - if (IS_ERR(mdiodev))
> - continue;
> -
> - xpcs = xpcs_create(mdiodev, mode);
> - if (IS_ERR_OR_NULL(xpcs)) {
> - mdio_device_free(mdiodev);
> - continue;
> - }
> -
> - priv->hw->xpcs = xpcs;
> - break;
> - }
> -
> - if (!priv->hw->xpcs) {
> - dev_warn(dev, "No XPCS found\n");
> - err = -ENODEV;
> - goto no_xpcs_found;
> - }
> - }
> -
> bus_register_done:
> priv->mii = new_bus;
>
> return 0;
>
> -no_xpcs_found:
> no_phy_found:
> mdiobus_unregister(new_bus);
> bus_register_fail:
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register
2021-06-04 11:51 ` Vladimir Oltean
@ 2021-06-04 13:08 ` Vladimir Oltean
0 siblings, 0 replies; 8+ messages in thread
From: Vladimir Oltean @ 2021-06-04 13:08 UTC (permalink / raw)
To: Michael Sit Wei Hong
Cc: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, linux-stm32, linux-arm-kernel, linux-kernel
On Fri, Jun 04, 2021 at 02:51:53PM +0300, Vladimir Oltean wrote:
> On Fri, Jun 04, 2021 at 06:57:31PM +0800, Michael Sit Wei Hong wrote:
> > From: Voon Weifeng <weifeng.voon@intel.com>
> >
> > This patch is a preparation patch for the enabling of Intel mGbE 2.5Gbps
> > link speed. The Intel mGbR link speed configuration (1G/2.5G) is depends on
> > a mdio ADHOC register which can be configured in the bios menu.
> > As PHY interface might be different for 1G and 2.5G, the mdio bus need be
> > ready to check the link speed and select the PHY interface before probing
> > the xPCS.
> >
> > Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> > Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> > ---
> > drivers/net/ethernet/stmicro/stmmac/stmmac.h | 1 +
> > .../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 ++
> > .../net/ethernet/stmicro/stmmac/stmmac_mdio.c | 64 ++++++++++---------
> > 3 files changed, 43 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac.h b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > index b6cd43eda7ac..fd7212afc543 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac.h
> > @@ -311,6 +311,7 @@ enum stmmac_state {
> > int stmmac_mdio_unregister(struct net_device *ndev);
> > int stmmac_mdio_register(struct net_device *ndev);
> > int stmmac_mdio_reset(struct mii_bus *mii);
> > +int stmmac_xpcs_setup(struct mii_bus *mii);
> > void stmmac_set_ethtool_ops(struct net_device *netdev);
> >
> > void stmmac_ptp_register(struct stmmac_priv *priv);
> > diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > index 6d41dd6f9f7a..c1331c07623d 100644
> > --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
> > @@ -6991,6 +6991,12 @@ int stmmac_dvr_probe(struct device *device,
> > }
> > }
> >
> > + if (priv->plat->mdio_bus_data->has_xpcs) {
>
> stmmac_mdio_register has:
>
> if (!mdio_bus_data)
> return 0;
>
> which suggests that some platforms might not populate priv->plat->mdio_bus_data.
>
> Are you sure it is safe to go straight to dereferencing mdio_bus_data->has_xpcs
> in the common driver probe function?
This patch seems to agree with me:
https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git/commit/?id=593f555fbc6091bbaec8dd2a38b47ee643412e61
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller
2021-06-04 10:57 [RESEND PATCH net-next v5 0/3] Enable 2.5Gbps speed for stmmac Michael Sit Wei Hong
2021-06-04 10:57 ` [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register Michael Sit Wei Hong
@ 2021-06-04 10:57 ` Michael Sit Wei Hong
2021-06-04 12:00 ` Vladimir Oltean
2021-06-04 10:57 ` [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed Michael Sit Wei Hong
2 siblings, 1 reply; 8+ messages in thread
From: Michael Sit Wei Hong @ 2021-06-04 10:57 UTC (permalink / raw)
To: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, michael.wei.hong.sit, linux-stm32,
linux-arm-kernel, linux-kernel, vladimir.oltean
From: Voon Weifeng <weifeng.voon@intel.com>
XPCS IP supports 2500BASEX as PHY interface. It is configured as
autonegotiation disable to cater for PHYs that does not supports 2500BASEX
autonegotiation.
v2: Add supported link speed masking.
v3: Restructure to introduce xpcs_config_2500basex() used to configure the
xpcs for 2.5G speeds. Added 2500BASEX specific information for
configuration.
v4: Fix indentation error
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
---
drivers/net/pcs/pcs-xpcs.c | 56 ++++++++++++++++++++++++++++++++++++
include/linux/pcs/pcs-xpcs.h | 1 +
2 files changed, 57 insertions(+)
diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
index 34164437c135..98c4a3973402 100644
--- a/drivers/net/pcs/pcs-xpcs.c
+++ b/drivers/net/pcs/pcs-xpcs.c
@@ -57,9 +57,12 @@
/* Clause 37 Defines */
/* VR MII MMD registers offsets */
+#define DW_VR_MII_MMD_CTRL 0x0000
#define DW_VR_MII_DIG_CTRL1 0x8000
#define DW_VR_MII_AN_CTRL 0x8001
#define DW_VR_MII_AN_INTR_STS 0x8002
+/* Enable 2.5G Mode */
+#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
/* EEE Mode Control Register */
#define DW_VR_MII_EEE_MCTRL0 0x8006
#define DW_VR_MII_EEE_MCTRL1 0x800b
@@ -86,6 +89,11 @@
#define DW_VR_MII_C37_ANSGM_SP_1000 0x2
#define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
+/* SR MII MMD Control defines */
+#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
+#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
+#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
+
/* VR MII EEE Control 0 defines */
#define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
#define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
@@ -161,6 +169,14 @@ static const int xpcs_sgmii_features[] = {
__ETHTOOL_LINK_MODE_MASK_NBITS,
};
+static const int xpcs_2500basex_features[] = {
+ ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ ETHTOOL_LINK_MODE_Autoneg_BIT,
+ ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
+ ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+ __ETHTOOL_LINK_MODE_MASK_NBITS,
+};
+
static const phy_interface_t xpcs_usxgmii_interfaces[] = {
PHY_INTERFACE_MODE_USXGMII,
};
@@ -177,11 +193,17 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = {
PHY_INTERFACE_MODE_SGMII,
};
+static const phy_interface_t xpcs_2500basex_interfaces[] = {
+ PHY_INTERFACE_MODE_2500BASEX,
+ PHY_INTERFACE_MODE_MAX,
+};
+
enum {
DW_XPCS_USXGMII,
DW_XPCS_10GKR,
DW_XPCS_XLGMII,
DW_XPCS_SGMII,
+ DW_XPCS_2500BASEX,
DW_XPCS_INTERFACE_MAX,
};
@@ -306,6 +328,7 @@ static int xpcs_soft_reset(struct mdio_xpcs_args *xpcs,
dev = MDIO_MMD_PCS;
break;
case DW_AN_C37_SGMII:
+ case DW_2500BASEX:
dev = MDIO_MMD_VEND2;
break;
default:
@@ -804,6 +827,28 @@ static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs)
return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
}
+static int xpcs_config_2500basex(struct mdio_xpcs_args *xpcs)
+{
+ int ret;
+
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
+ if (ret < 0)
+ return ret;
+ ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
+ ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
+ ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
+ if (ret < 0)
+ return ret;
+
+ ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
+ if (ret < 0)
+ return ret;
+ ret &= ~AN_CL37_EN;
+ ret |= SGMII_SPEED_SS6;
+ ret &= ~SGMII_SPEED_SS13;
+ return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
+}
+
static int xpcs_do_config(struct mdio_xpcs_args *xpcs,
phy_interface_t interface, unsigned int mode)
{
@@ -827,6 +872,11 @@ static int xpcs_do_config(struct mdio_xpcs_args *xpcs,
if (ret)
return ret;
break;
+ case DW_2500BASEX:
+ ret = xpcs_config_2500basex(xpcs);
+ if (ret)
+ return ret;
+ break;
default:
return -1;
}
@@ -1023,6 +1073,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
.num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
.an_mode = DW_AN_C37_SGMII,
},
+ [DW_XPCS_2500BASEX] = {
+ .supported = xpcs_2500basex_features,
+ .interface = xpcs_2500basex_interfaces,
+ .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
+ .an_mode = DW_2500BASEX,
+ },
};
static const struct xpcs_id xpcs_id_list[] = {
diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h
index 0860a5b59f10..4d815f03b4b2 100644
--- a/include/linux/pcs/pcs-xpcs.h
+++ b/include/linux/pcs/pcs-xpcs.h
@@ -13,6 +13,7 @@
/* AN mode */
#define DW_AN_C73 1
#define DW_AN_C37_SGMII 2
+#define DW_2500BASEX 3
struct xpcs_id;
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller
2021-06-04 10:57 ` [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller Michael Sit Wei Hong
@ 2021-06-04 12:00 ` Vladimir Oltean
0 siblings, 0 replies; 8+ messages in thread
From: Vladimir Oltean @ 2021-06-04 12:00 UTC (permalink / raw)
To: Michael Sit Wei Hong
Cc: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, linux-stm32, linux-arm-kernel, linux-kernel
On Fri, Jun 04, 2021 at 06:57:32PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <weifeng.voon@intel.com>
>
> XPCS IP supports 2500BASEX as PHY interface. It is configured as
> autonegotiation disable to cater for PHYs that does not supports 2500BASEX
> autonegotiation.
>
> v2: Add supported link speed masking.
> v3: Restructure to introduce xpcs_config_2500basex() used to configure the
> xpcs for 2.5G speeds. Added 2500BASEX specific information for
> configuration.
> v4: Fix indentation error
>
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> ---
> drivers/net/pcs/pcs-xpcs.c | 56 ++++++++++++++++++++++++++++++++++++
> include/linux/pcs/pcs-xpcs.h | 1 +
> 2 files changed, 57 insertions(+)
>
> diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c
> index 34164437c135..98c4a3973402 100644
> --- a/drivers/net/pcs/pcs-xpcs.c
> +++ b/drivers/net/pcs/pcs-xpcs.c
> @@ -57,9 +57,12 @@
>
> /* Clause 37 Defines */
> /* VR MII MMD registers offsets */
> +#define DW_VR_MII_MMD_CTRL 0x0000
> #define DW_VR_MII_DIG_CTRL1 0x8000
> #define DW_VR_MII_AN_CTRL 0x8001
> #define DW_VR_MII_AN_INTR_STS 0x8002
> +/* Enable 2.5G Mode */
> +#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
> /* EEE Mode Control Register */
> #define DW_VR_MII_EEE_MCTRL0 0x8006
> #define DW_VR_MII_EEE_MCTRL1 0x800b
> @@ -86,6 +89,11 @@
> #define DW_VR_MII_C37_ANSGM_SP_1000 0x2
> #define DW_VR_MII_C37_ANSGM_SP_LNKSTS BIT(4)
>
> +/* SR MII MMD Control defines */
> +#define AN_CL37_EN BIT(12) /* Enable Clause 37 auto-nego */
> +#define SGMII_SPEED_SS13 BIT(13) /* SGMII speed along with SS6 */
> +#define SGMII_SPEED_SS6 BIT(6) /* SGMII speed along with SS13 */
> +
> /* VR MII EEE Control 0 defines */
> #define DW_VR_MII_EEE_LTX_EN BIT(0) /* LPI Tx Enable */
> #define DW_VR_MII_EEE_LRX_EN BIT(1) /* LPI Rx Enable */
> @@ -161,6 +169,14 @@ static const int xpcs_sgmii_features[] = {
> __ETHTOOL_LINK_MODE_MASK_NBITS,
> };
>
> +static const int xpcs_2500basex_features[] = {
> + ETHTOOL_LINK_MODE_Asym_Pause_BIT,
> + ETHTOOL_LINK_MODE_Autoneg_BIT,
> + ETHTOOL_LINK_MODE_2500baseX_Full_BIT,
> + ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
> + __ETHTOOL_LINK_MODE_MASK_NBITS,
> +};
> +
This is a general design comment, perhaps you could address this later,
but do keep it in mind:
I don't think the PCS has anything to do with whether the link will
support flow control.
Similarly, Aquantia (now Marvell) PHYs operating in 2500base-x mode are
capable of negotiating the copper-side link to 10/100/1000/2500 even if
the system-side link is fixed at 2500. The way this is achieved is by
the PHY emitting PAUSE frames towards the MAC in order to achieve rate
adaptation with the external link speed.
This is not completely standardized in phylink at the moment, but we
have systems where this works. My point is that maybe the PCS driver
isn't the most appropriate place to implement the phylink_validate
method - the MAC driver is almost always in the position to know better.
If you could move the xpcs validation inside stmmac I think that would
be an improvement. For example with the NXP SJA1105 patches that I am
going to send out for review soon, I am not calling xpcs_validate() at
all.
> static const phy_interface_t xpcs_usxgmii_interfaces[] = {
> PHY_INTERFACE_MODE_USXGMII,
> };
> @@ -177,11 +193,17 @@ static const phy_interface_t xpcs_sgmii_interfaces[] = {
> PHY_INTERFACE_MODE_SGMII,
> };
>
> +static const phy_interface_t xpcs_2500basex_interfaces[] = {
> + PHY_INTERFACE_MODE_2500BASEX,
> + PHY_INTERFACE_MODE_MAX,
> +};
> +
> enum {
> DW_XPCS_USXGMII,
> DW_XPCS_10GKR,
> DW_XPCS_XLGMII,
> DW_XPCS_SGMII,
> + DW_XPCS_2500BASEX,
> DW_XPCS_INTERFACE_MAX,
> };
>
> @@ -306,6 +328,7 @@ static int xpcs_soft_reset(struct mdio_xpcs_args *xpcs,
> dev = MDIO_MMD_PCS;
> break;
> case DW_AN_C37_SGMII:
> + case DW_2500BASEX:
> dev = MDIO_MMD_VEND2;
> break;
> default:
> @@ -804,6 +827,28 @@ static int xpcs_config_aneg_c37_sgmii(struct mdio_xpcs_args *xpcs)
> return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
> }
>
> +static int xpcs_config_2500basex(struct mdio_xpcs_args *xpcs)
> +{
> + int ret;
> +
> + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1);
> + if (ret < 0)
> + return ret;
> + ret |= DW_VR_MII_DIG_CTRL1_2G5_EN;
> + ret &= ~DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW;
> + ret = xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_DIG_CTRL1, ret);
> + if (ret < 0)
> + return ret;
> +
> + ret = xpcs_read(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL);
> + if (ret < 0)
> + return ret;
> + ret &= ~AN_CL37_EN;
> + ret |= SGMII_SPEED_SS6;
> + ret &= ~SGMII_SPEED_SS13;
> + return xpcs_write(xpcs, MDIO_MMD_VEND2, DW_VR_MII_MMD_CTRL, ret);
> +}
> +
> static int xpcs_do_config(struct mdio_xpcs_args *xpcs,
> phy_interface_t interface, unsigned int mode)
> {
> @@ -827,6 +872,11 @@ static int xpcs_do_config(struct mdio_xpcs_args *xpcs,
> if (ret)
> return ret;
> break;
> + case DW_2500BASEX:
> + ret = xpcs_config_2500basex(xpcs);
> + if (ret)
> + return ret;
> + break;
> default:
> return -1;
> }
> @@ -1023,6 +1073,12 @@ static const struct xpcs_compat synopsys_xpcs_compat[DW_XPCS_INTERFACE_MAX] = {
> .num_interfaces = ARRAY_SIZE(xpcs_sgmii_interfaces),
> .an_mode = DW_AN_C37_SGMII,
> },
> + [DW_XPCS_2500BASEX] = {
> + .supported = xpcs_2500basex_features,
> + .interface = xpcs_2500basex_interfaces,
> + .num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
> + .an_mode = DW_2500BASEX,
> + },
> };
>
> static const struct xpcs_id xpcs_id_list[] = {
> diff --git a/include/linux/pcs/pcs-xpcs.h b/include/linux/pcs/pcs-xpcs.h
> index 0860a5b59f10..4d815f03b4b2 100644
> --- a/include/linux/pcs/pcs-xpcs.h
> +++ b/include/linux/pcs/pcs-xpcs.h
> @@ -13,6 +13,7 @@
> /* AN mode */
> #define DW_AN_C73 1
> #define DW_AN_C37_SGMII 2
> +#define DW_2500BASEX 3
>
> struct xpcs_id;
>
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed
2021-06-04 10:57 [RESEND PATCH net-next v5 0/3] Enable 2.5Gbps speed for stmmac Michael Sit Wei Hong
2021-06-04 10:57 ` [RESEND PATCH net-next v5 1/3] net: stmmac: split xPCS setup from mdio register Michael Sit Wei Hong
2021-06-04 10:57 ` [RESEND PATCH net-next v5 2/3] net: pcs: add 2500BASEX support for Intel mGbE controller Michael Sit Wei Hong
@ 2021-06-04 10:57 ` Michael Sit Wei Hong
2021-06-04 12:02 ` Vladimir Oltean
2 siblings, 1 reply; 8+ messages in thread
From: Michael Sit Wei Hong @ 2021-06-04 10:57 UTC (permalink / raw)
To: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, michael.wei.hong.sit, linux-stm32,
linux-arm-kernel, linux-kernel, vladimir.oltean
From: Voon Weifeng <weifeng.voon@intel.com>
The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by
2.5 times of the original rate. In this mode, the serdes/PHY operates at a
serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of
the MAC operate at 312.5 MHz instead of 125 MHz.
For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is
only able to be configured in the BIOS during boot time. Kernel driver has
no access to modify the clock rate for 1Gbps/2.5G mode. The way to
determined the current 1G/2.5G mode is by reading a dedicated adhoc
register through mdio bus. In short, after the system boot up, it is either
in 1G mode or 2.5G mode which not able to be changed on the fly.
Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and
disables the xpcs_an_inband. This is to cater for some PHYs that only
supports 2500BASEX PHY interface with no autonegotiation.
v2: remove MAC supported link speed masking
v3: Restructure to introduce intel_speed_mode_2500() to read serdes registers
for max speed supported and select the appropritate configuration.
Use max_speed to determine the supported link speed mask.
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
---
.../net/ethernet/stmicro/stmmac/dwmac-intel.c | 48 ++++++++++++++++++-
.../net/ethernet/stmicro/stmmac/dwmac-intel.h | 13 +++++
.../net/ethernet/stmicro/stmmac/dwmac4_core.c | 1 +
.../net/ethernet/stmicro/stmmac/stmmac_main.c | 7 +++
include/linux/stmmac.h | 1 +
5 files changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 2ecf93c84b9d..6a9a19b0844c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -102,6 +102,22 @@ static int intel_serdes_powerup(struct net_device *ndev, void *priv_data)
serdes_phy_addr = intel_priv->mdio_adhoc_addr;
+ /* Set the serdes rate and the PCLK rate */
+ data = mdiobus_read(priv->mii, serdes_phy_addr,
+ SERDES_GCR0);
+
+ data &= ~SERDES_RATE_MASK;
+ data &= ~SERDES_PCLK_MASK;
+
+ if (priv->plat->max_speed == 2500)
+ data |= SERDES_RATE_PCIE_GEN2 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_37p5MHZ << SERDES_PCLK_SHIFT;
+ else
+ data |= SERDES_RATE_PCIE_GEN1 << SERDES_RATE_PCIE_SHIFT |
+ SERDES_PCLK_70MHZ << SERDES_PCLK_SHIFT;
+
+ mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data);
+
/* assert clk_req */
data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0);
data |= SERDES_PLL_CLK;
@@ -230,6 +246,32 @@ static void intel_serdes_powerdown(struct net_device *ndev, void *intel_data)
}
}
+static void intel_speed_mode_2500(struct net_device *ndev, void *intel_data)
+{
+ struct intel_priv_data *intel_priv = intel_data;
+ struct stmmac_priv *priv = netdev_priv(ndev);
+ int serdes_phy_addr = 0;
+ u32 data = 0;
+
+ serdes_phy_addr = intel_priv->mdio_adhoc_addr;
+
+ /* Determine the link speed mode: 2.5Gbps/1Gbps */
+ data = mdiobus_read(priv->mii, serdes_phy_addr,
+ SERDES_GCR);
+
+ if (((data & SERDES_LINK_MODE_MASK) >> SERDES_LINK_MODE_SHIFT) ==
+ SERDES_LINK_MODE_2G5) {
+ dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n");
+ priv->plat->max_speed = 2500;
+ priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX;
+ priv->plat->mdio_bus_data->xpcs_an_inband = false;
+ } else {
+ priv->plat->max_speed = 1000;
+ priv->plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ priv->plat->mdio_bus_data->xpcs_an_inband = true;
+ }
+}
+
/* Program PTP Clock Frequency for different variant of
* Intel mGBE that has slightly different GPO mapping
*/
@@ -586,7 +628,7 @@ static int ehl_sgmii_data(struct pci_dev *pdev,
{
plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
-
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
@@ -639,6 +681,7 @@ static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return ehl_pse0_common_data(pdev, plat);
@@ -677,6 +720,7 @@ static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return ehl_pse1_common_data(pdev, plat);
@@ -711,6 +755,7 @@ static int tgl_sgmii_phy0_data(struct pci_dev *pdev,
{
plat->bus_id = 1;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return tgl_common_data(pdev, plat);
@@ -725,6 +770,7 @@ static int tgl_sgmii_phy1_data(struct pci_dev *pdev,
{
plat->bus_id = 2;
plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ plat->speed_mode_2500 = intel_speed_mode_2500;
plat->serdes_powerup = intel_serdes_powerup;
plat->serdes_powerdown = intel_serdes_powerdown;
return tgl_common_data(pdev, plat);
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
index 542acb8ce467..20d14e588044 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.h
@@ -9,6 +9,7 @@
#define POLL_DELAY_US 8
/* SERDES Register */
+#define SERDES_GCR 0x0 /* Global Conguration */
#define SERDES_GSR0 0x5 /* Global Status Reg0 */
#define SERDES_GCR0 0xb /* Global Configuration Reg0 */
@@ -17,8 +18,20 @@
#define SERDES_PHY_RX_CLK BIT(1) /* PSE SGMII PHY rx clk */
#define SERDES_RST BIT(2) /* Serdes Reset */
#define SERDES_PWR_ST_MASK GENMASK(6, 4) /* Serdes Power state*/
+#define SERDES_RATE_MASK GENMASK(9, 8)
+#define SERDES_PCLK_MASK GENMASK(14, 12) /* PCLK rate to PHY */
+#define SERDES_LINK_MODE_MASK GENMASK(2, 1)
+#define SERDES_LINK_MODE_SHIFT 1
#define SERDES_PWR_ST_SHIFT 4
#define SERDES_PWR_ST_P0 0x0
#define SERDES_PWR_ST_P3 0x3
+#define SERDES_LINK_MODE_2G5 0x3
+#define SERSED_LINK_MODE_1G 0x2
+#define SERDES_PCLK_37p5MHZ 0x0
+#define SERDES_PCLK_70MHZ 0x1
+#define SERDES_RATE_PCIE_GEN1 0x0
+#define SERDES_RATE_PCIE_GEN2 0x1
+#define SERDES_RATE_PCIE_SHIFT 8
+#define SERDES_PCLK_SHIFT 12
#endif /* __DWMAC_INTEL_H__ */
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
index f35c03c9f91e..67ba083eb90c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac4_core.c
@@ -1358,6 +1358,7 @@ int dwmac4_setup(struct stmmac_priv *priv)
mac->link.speed10 = GMAC_CONFIG_PS;
mac->link.speed100 = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
mac->link.speed1000 = 0;
+ mac->link.speed2500 = GMAC_CONFIG_FES;
mac->link.speed_mask = GMAC_CONFIG_FES | GMAC_CONFIG_PS;
mac->mii.addr = GMAC_MDIO_ADDR;
mac->mii.data = GMAC_MDIO_DATA;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index c1331c07623d..8d5ac268ad65 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -931,6 +931,10 @@ static void stmmac_validate(struct phylink_config *config,
if ((max_speed > 0) && (max_speed < 1000)) {
phylink_set(mask, 1000baseT_Full);
phylink_set(mask, 1000baseX_Full);
+ } else if (priv->plat->has_gmac4) {
+ if (!max_speed || max_speed >= 2500)
+ phylink_set(mac_supported, 2500baseT_Full);
+ phylink_set(mac_supported, 2500baseX_Full);
} else if (priv->plat->has_xgmac) {
if (!max_speed || (max_speed >= 2500)) {
phylink_set(mac_supported, 2500baseT_Full);
@@ -6991,6 +6995,9 @@ int stmmac_dvr_probe(struct device *device,
}
}
+ if (priv->plat->speed_mode_2500)
+ priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv);
+
if (priv->plat->mdio_bus_data->has_xpcs) {
ret = stmmac_xpcs_setup(priv->mii);
if (ret)
diff --git a/include/linux/stmmac.h b/include/linux/stmmac.h
index e55a4807e3ea..b10be3385a30 100644
--- a/include/linux/stmmac.h
+++ b/include/linux/stmmac.h
@@ -223,6 +223,7 @@ struct plat_stmmacenet_data {
void (*fix_mac_speed)(void *priv, unsigned int speed);
int (*serdes_powerup)(struct net_device *ndev, void *priv);
void (*serdes_powerdown)(struct net_device *ndev, void *priv);
+ void (*speed_mode_2500)(struct net_device *ndev, void *priv);
void (*ptp_clk_freq_config)(void *priv);
int (*init)(struct platform_device *pdev, void *priv);
void (*exit)(struct platform_device *pdev, void *priv);
--
2.17.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed
2021-06-04 10:57 ` [RESEND PATCH net-next v5 3/3] net: stmmac: enable Intel mGbE 2.5Gbps link speed Michael Sit Wei Hong
@ 2021-06-04 12:02 ` Vladimir Oltean
0 siblings, 0 replies; 8+ messages in thread
From: Vladimir Oltean @ 2021-06-04 12:02 UTC (permalink / raw)
To: Michael Sit Wei Hong
Cc: Jose.Abreu, andrew, hkallweit1, linux, kuba, netdev,
peppe.cavallaro, alexandre.torgue, davem, mcoquelin.stm32,
weifeng.voon, boon.leong.ong, tee.min.tan, vee.khee.wong,
vee.khee.wong, linux-stm32, linux-arm-kernel, linux-kernel
On Fri, Jun 04, 2021 at 06:57:33PM +0800, Michael Sit Wei Hong wrote:
> From: Voon Weifeng <weifeng.voon@intel.com>
>
> The Intel mGbE supports 2.5Gbps link speed by increasing the clock rate by
> 2.5 times of the original rate. In this mode, the serdes/PHY operates at a
> serial baud rate of 3.125 Gbps and the PCS data path and GMII interface of
> the MAC operate at 312.5 MHz instead of 125 MHz.
>
> For Intel mGbE, the overclocking of 2.5 times clock rate to support 2.5G is
> only able to be configured in the BIOS during boot time. Kernel driver has
> no access to modify the clock rate for 1Gbps/2.5G mode. The way to
> determined the current 1G/2.5G mode is by reading a dedicated adhoc
> register through mdio bus. In short, after the system boot up, it is either
> in 1G mode or 2.5G mode which not able to be changed on the fly.
>
> Compared to 1G mode, the 2.5G mode selects the 2500BASEX as PHY interface and
> disables the xpcs_an_inband. This is to cater for some PHYs that only
> supports 2500BASEX PHY interface with no autonegotiation.
>
> v2: remove MAC supported link speed masking
> v3: Restructure to introduce intel_speed_mode_2500() to read serdes registers
> for max speed supported and select the appropritate configuration.
> Use max_speed to determine the supported link speed mask.
>
> Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
> Signed-off-by: Michael Sit Wei Hong <michael.wei.hong.sit@intel.com>
> ---
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
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