arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes

arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes

[Tinghan Shen]

This series is a collection of device nodes for Mediatek SoC MT8195 and
depends on patches[1][2][3].

The dependency list is not complete.
some dependencies are still under working.

[1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
    https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/

[2] dt-bindings: power: Add MT8195 power domains
    https://patchwork.kernel.org/project/linux-mediatek/patch/20210610023614.5375-3-chun-jie.chen@mediatek.com/

[3] dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
    https://patchwork.kernel.org/project/linux-mediatek/patch/20210413055702.27535-2-zhiyong.tao@mediatek.com/

[PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node

[Tinghan Shen]

From: Crystal Guo <crystal.guo@mediatek.com>

add infracfg_rst node which is for MT8195 platform

Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 629cd883facf..8cda62f736b3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/ti-syscon.h>
 
 / {
 	compatible = "mediatek,mt8195";
@@ -273,6 +274,20 @@
 			};
 		};
 
+		infracfg: syscon@10001000 {
+			compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd";
+			reg = <0 0x10001000 0 0x1000>;
+			#clock-cells = <1>;
+
+			infracfg_rst: reset-controller {
+				compatible = "ti,syscon-reset";
+				#reset-cells = <1>;
+				ti,reset-bits = <
+					0x140 26 0x144 26 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
+				>;
+			};
+		};
+
 		watchdog: watchdog@10007000 {
 			compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt";
 			reg = <0 0x10007000 0 0x100>;
-- 
2.18.0

Re: [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node

[Chen-Yu Tsai]

Hi,

On Wed, Jun 16, 2021 at 01:32:08AM +0800, Tinghan Shen wrote:
> From: Crystal Guo <crystal.guo@mediatek.com>
> 
> add infracfg_rst node which is for MT8195 platform
> 
> Signed-off-by: Crystal Guo <crystal.guo@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 629cd883facf..8cda62f736b3 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -8,6 +8,7 @@
>  
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/reset/ti-syscon.h>
>  
>  / {
>  	compatible = "mediatek,mt8195";
> @@ -273,6 +274,20 @@
>  			};
>  		};
>  
> +		infracfg: syscon@10001000 {
> +			compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd";

This block is named infracfg_ao in the datasheet. You seem to rename it
in the clock patch. Maybe you squashed the change into the wrong commit?

> +			reg = <0 0x10001000 0 0x1000>;

The address range matches the datasheet.

> +			#clock-cells = <1>;
> +
> +			infracfg_rst: reset-controller {
> +				compatible = "ti,syscon-reset";
> +				#reset-cells = <1>;
> +				ti,reset-bits = <
> +					0x140 26 0x144 26 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE)
> +				>;
> +			};

This node doesn't seem to be used anywhere. Is it really needed?


ChenYu

[PATCH 02/27] arm64: dts: mt8195: add pinctrl node

[Tinghan Shen]

From: Zhiqiang Ma <zhiqiang.ma@mediatek.com>

add support of pinctrl for mt8195 soc.

Signed-off-by: Zhiqiang Ma <zhiqiang.ma@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8cda62f736b3..640f09100bb7 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -288,6 +289,27 @@
 			};
 		};
 
+		pio: pinctrl@10005000 {
+			compatible = "mediatek,mt8195-pinctrl";
+			reg = <0 0x10005000 0 0x1000>,
+			      <0 0x11d10000 0 0x1000>,
+			      <0 0x11d30000 0 0x1000>,
+			      <0 0x11d40000 0 0x1000>,
+			      <0 0x11e20000 0 0x1000>,
+			      <0 0x11eb0000 0 0x1000>,
+			      <0 0x11f40000 0 0x1000>,
+			      <0 0x1000b000 0 0x1000>;
+			reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+				    "iocfg_br", "iocfg_lm", "iocfg_rb",
+				    "iocfg_tl", "eint";
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-ranges = <&pio 0 0 144>;
+			interrupt-controller;
+			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+			#interrupt-cells = <2>;
+		};
+
 		watchdog: watchdog@10007000 {
 			compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt";
 			reg = <0 0x10007000 0 0x100>;
-- 
2.18.0

[PATCH 03/27] arm64: dts: mt8195: add pwrap node

[Tinghan Shen]

From: Henry Chen <henryc.chen@mediatek.com>

Add pwrap node to SOC MT8195.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 640f09100bb7..bbb1e008e522 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -322,6 +322,18 @@
 			clocks = <&clk26m>;
 		};
 
+		pwrap: pwrap@10024000 {
+			compatible = "mediatek,mt8195-pwrap", "syscon";
+			reg = <0 0x10024000 0 0x1000>;
+			reg-names = "pwrap";
+			interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+			clock-names = "spi", "wrap";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
+		};
+
 		uart0: serial@11001100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
-- 
2.18.0

[PATCH 05/27] arm64: dts: mt8195: add spmi node

[Tinghan Shen]

From: Henry Chen <henryc.chen@mediatek.com>

Add spmi node to SOC MT8195.

Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index bbb1e008e522..965445d07e92 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -334,6 +334,21 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
 		};
 
+		spmi: spmi@10027000 {
+			compatible = "mediatek,mt8195-spmi";
+			reg = <0 0x10027000 0 0x000e00>,
+			      <0 0x10029000 0 0x000100>;
+			reg-names = "pmif", "spmimst";
+			clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+				 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+				 <&topckgen CLK_TOP_SPMI_M_MST_SEL>;
+			clock-names = "pmif_sys_ck",
+				      "pmif_tmr_ck",
+				      "spmimst_clk_mux";
+			assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
+		};
+
 		uart0: serial@11001100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
-- 
2.18.0

[PATCH 06/27] arm64: dts: mt8195: add clock controllers

[Tinghan Shen]

From: Weiyi Lu <weiyi.lu@mediatek.com>

Add clock controller nodes for SoC mt8195

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 215 ++++++++++++++++++++++-
 1 file changed, 213 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 965445d07e92..7946a13fcbc3 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/clock/mt8195-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
@@ -275,8 +276,14 @@
 			};
 		};
 
-		infracfg: syscon@10001000 {
-			compatible = "mediatek,mt8195-infracfg", "syscon", "simple-mfd";
+		topckgen: syscon@10000000 {
+			compatible = "mediatek,mt8195-topckgen", "syscon";
+			reg = <0 0x10000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		infracfg_ao: infracfg_ao@10001000 {
+			compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
 			reg = <0 0x10001000 0 0x1000>;
 			#clock-cells = <1>;
 
@@ -315,6 +322,12 @@
 			reg = <0 0x10007000 0 0x100>;
 		};
 
+		apmixedsys: syscon@1000c000 {
+			compatible = "mediatek,mt8195-apmixedsys", "syscon";
+			reg = <0 0x1000c000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		systimer: timer@10017000 {
 			compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer";
 			reg = <0 0x10017000 0 0x1000>;
@@ -349,6 +362,30 @@
 			assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC_D10>;
 		};
 
+		nnasys: syscon@10211000 {
+			compatible = "mediatek,mt8195-nnasys", "syscon";
+			reg = <0 0x10211000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		scp_adsp: syscon@10720000 {
+			compatible = "mediatek,mt8195-scp_adsp", "syscon";
+			reg = <0 0x10720000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		audsys: syscon@10890000 {
+			compatible = "mediatek,mt8195-audsys", "syscon";
+			reg = <0 0x10890000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		audsys_src: syscon@108a0000 {
+			compatible = "mediatek,mt8195-audsys_src", "syscon";
+			reg = <0 0x108a0000 0 0x2000>;
+			#clock-cells = <1>;
+		};
+
 		uart0: serial@11001100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
@@ -411,6 +448,12 @@
 			status = "disabled";
 		};
 
+		pericfg_ao: syscon@11003000 {
+			compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+			reg = <0 0x11003000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
@@ -472,6 +515,18 @@
 			};
 		};
 
+		imp_iic_wrap_s: syscon@11d03000 {
+			compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon";
+			reg = <0 0x11d03000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		imp_iic_wrap_w: syscon@11e05000 {
+			compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon";
+			reg = <0 0x11e05000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		u3phy1: t-phy@11e30000 {
 			compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";
 			#address-cells = <1>;
@@ -524,5 +579,161 @@
 			#phy-cells = <0>;
 			status = "disabled";
 		};
+
+		mfgcfg: syscon@13fbf000 {
+			compatible = "mediatek,mt8195-mfgcfg", "syscon";
+			reg = <0 0x13fbf000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vppsys0: syscon@14000000 {
+			compatible = "mediatek,mt8195-vppsys0", "syscon";
+			reg = <0 0x14000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		wpesys: syscon@14e00000 {
+			compatible = "mediatek,mt8195-wpesys", "syscon";
+			reg = <0 0x14e00000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		wpesys_vpp0: syscon@14e02000 {
+			compatible = "mediatek,mt8195-wpesys_vpp0", "syscon";
+			reg = <0 0x14e02000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		wpesys_vpp1: syscon@14e03000 {
+			compatible = "mediatek,mt8195-wpesys_vpp1", "syscon";
+			reg = <0 0x14e03000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vppsys1: syscon@14f00000 {
+			compatible = "mediatek,mt8195-vppsys1", "syscon";
+			reg = <0 0x14f00000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		imgsys: syscon@15000000 {
+			compatible = "mediatek,mt8195-imgsys", "syscon";
+			reg = <0 0x15000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		imgsys1_dip_top: syscon@15110000 {
+			compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon";
+			reg = <0 0x15110000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		imgsys1_dip_nr: syscon@15130000 {
+			compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon";
+			reg = <0 0x15130000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		imgsys1_wpe: syscon@15220000 {
+			compatible = "mediatek,mt8195-imgsys1_wpe", "syscon";
+			reg = <0 0x15220000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		ipesys: syscon@15330000 {
+			compatible = "mediatek,mt8195-ipesys", "syscon";
+			reg = <0 0x15330000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys: syscon@16000000 {
+			compatible = "mediatek,mt8195-camsys", "syscon";
+			reg = <0 0x16000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys_rawa: syscon@1604f000 {
+			compatible = "mediatek,mt8195-camsys_rawa", "syscon";
+			reg = <0 0x1604f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys_yuva: syscon@1606f000 {
+			compatible = "mediatek,mt8195-camsys_yuva", "syscon";
+			reg = <0 0x1606f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys_rawb: syscon@1608f000 {
+			compatible = "mediatek,mt8195-camsys_rawb", "syscon";
+			reg = <0 0x1608f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys_yuvb: syscon@160af000 {
+			compatible = "mediatek,mt8195-camsys_yuvb", "syscon";
+			reg = <0 0x160af000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		camsys_mraw: syscon@16140000 {
+			compatible = "mediatek,mt8195-camsys_mraw", "syscon";
+			reg = <0 0x16140000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		ccusys: syscon@17200000 {
+			compatible = "mediatek,mt8195-ccusys", "syscon";
+			reg = <0 0x17200000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vdecsys_soc: syscon@1800f000 {
+			compatible = "mediatek,mt8195-vdecsys_soc", "syscon";
+			reg = <0 0x1800f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vdecsys: syscon@1802f000 {
+			compatible = "mediatek,mt8195-vdecsys", "syscon";
+			reg = <0 0x1802f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vdecsys_core1: syscon@1803f000 {
+			compatible = "mediatek,mt8195-vdecsys_core1", "syscon";
+			reg = <0 0x1803f000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		apusys_pll: syscon@190f3000 {
+			compatible = "mediatek,mt8195-apusys_pll", "syscon";
+			reg = <0 0x190f3000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vencsys: syscon@1a000000 {
+			compatible = "mediatek,mt8195-vencsys", "syscon";
+			reg = <0 0x1a000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vencsys_core1: syscon@1b000000 {
+			compatible = "mediatek,mt8195-vencsys_core1", "syscon";
+			reg = <0 0x1b000000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vdosys0: syscon@1c01a000 {
+			compatible = "mediatek,mt8195-vdosys0", "syscon";
+			reg = <0 0x1c01a000 0 0x1000>;
+			#clock-cells = <1>;
+		};
+
+		vdosys1: syscon@1c100000 {
+			compatible = "mediatek,mt8195-vdosys1", "syscon";
+			reg = <0 0x1c100000 0 0x1000>;
+			#clock-cells = <1>;
+		};
 	};
 };
-- 
2.18.0

[PATCH 07/27] arm64: dts: mt8195: add power domains controller

[Tinghan Shen]

From: Weiyi Lu <weiyi.lu@mediatek.com>

Add power domains controller node for SoC mt8195

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 364 +++++++++++++++++++++++
 1 file changed, 364 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7946a13fcbc3..5463e7ba1061 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/power/mt8195-power.h>
 #include <dt-bindings/reset/ti-syscon.h>
 
 / {
@@ -317,6 +318,369 @@
 			#interrupt-cells = <2>;
 		};
 
+		scpsys: syscon@10006000 {
+			compatible = "syscon", "simple-mfd";
+			reg = <0 0x10006000 0 0x1000>;
+			#power-domain-cells = <1>;
+
+			/* System Power Manager */
+			spm: power-controller {
+				compatible = "mediatek,mt8195-power-controller";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#power-domain-cells = <1>;
+
+				/* power domain of the SoC */
+				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
+					reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+					mediatek,infracfg = <&infracfg_ao>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
+					reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+					mediatek,infracfg = <&infracfg_ao>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+					reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+					reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
+					reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
+					clocks = <&topckgen CLK_TOP_SENINF_SEL>,
+						 <&topckgen CLK_TOP_SENINF2_SEL>;
+					clock-names = "csi_rx_top", "csi_rx_top1";
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_ETHER {
+					reg = <MT8195_POWER_DOMAIN_ETHER>;
+					clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+					clock-names = "ether";
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_ADSP {
+					reg = <MT8195_POWER_DOMAIN_ADSP>;
+					clocks = <&topckgen CLK_TOP_ADSP_SEL>;
+					clock-names = "adsp";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <1>;
+
+					power-domain@MT8195_POWER_DOMAIN_AUDIO {
+						reg = <MT8195_POWER_DOMAIN_AUDIO>;
+						clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+							 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+							 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
+							 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
+						clock-names = "audio", "audio1", "audio2",
+							      "audio3";
+						mediatek,infracfg = <&infracfg_ao>;
+						#power-domain-cells = <0>;
+					};
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_AUDIO_ASRC {
+					reg = <MT8195_POWER_DOMAIN_AUDIO_ASRC>;
+					clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
+						 <&topckgen CLK_TOP_ASM_L_SEL>,
+						 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
+					clock-names = "audio_asrc", "audio_asrc1", "audio_asrc2";
+					mediatek,infracfg = <&infracfg_ao>;
+					#power-domain-cells = <0>;
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_NNA {
+					reg = <MT8195_POWER_DOMAIN_NNA>;
+					clocks = <&topckgen CLK_TOP_NNA0_SEL>;
+					clock-names = "nna";
+					mediatek,infracfg = <&infracfg_ao>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <1>;
+
+					power-domain@MT8195_POWER_DOMAIN_NNA0 {
+						reg = <MT8195_POWER_DOMAIN_NNA0>;
+						mediatek,infracfg = <&infracfg_ao>;
+						#power-domain-cells = <0>;
+					};
+
+					power-domain@MT8195_POWER_DOMAIN_NNA1 {
+						reg = <MT8195_POWER_DOMAIN_NNA1>;
+						mediatek,infracfg = <&infracfg_ao>;
+						#power-domain-cells = <0>;
+					};
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_MFG0 {
+					reg = <MT8195_POWER_DOMAIN_MFG0>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <1>;
+
+					power-domain@MT8195_POWER_DOMAIN_MFG1 {
+						reg = <MT8195_POWER_DOMAIN_MFG1>;
+						clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
+						clock-names = "mfg";
+						mediatek,infracfg = <&infracfg_ao>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#power-domain-cells = <1>;
+
+						power-domain@MT8195_POWER_DOMAIN_MFG2 {
+							reg = <MT8195_POWER_DOMAIN_MFG2>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_MFG3 {
+							reg = <MT8195_POWER_DOMAIN_MFG3>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_MFG4 {
+							reg = <MT8195_POWER_DOMAIN_MFG4>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_MFG5 {
+							reg = <MT8195_POWER_DOMAIN_MFG5>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_MFG6 {
+							reg = <MT8195_POWER_DOMAIN_MFG6>;
+							#power-domain-cells = <0>;
+						};
+					};
+				};
+
+				power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
+					reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
+					clocks = <&topckgen CLK_TOP_VPP_SEL>,
+						 <&topckgen CLK_TOP_CAM_SEL>,
+						 <&topckgen CLK_TOP_CCU_SEL>,
+						 <&topckgen CLK_TOP_IMG_SEL>,
+						 <&topckgen CLK_TOP_VENC_SEL>,
+						 <&topckgen CLK_TOP_VDEC_SEL>,
+						 <&topckgen CLK_TOP_WPE_VPP_SEL>,
+						 <&topckgen CLK_TOP_CFG_VPP0>,
+						 <&vppsys0 CLK_VPP0_SMI_COMMON>,
+						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
+						 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
+						 <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
+						 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
+						 <&vppsys0 CLK_VPP0_GALS_INFRA>,
+						 <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
+						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
+						 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
+						 <&vppsys0 CLK_VPP0_SMI_REORDER>,
+						 <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+						 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+						 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+						 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+						 <&vppsys0 CLK_VPP0_SMI_RSI>,
+						 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+						 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+						 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+						 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+					clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
+						      "vppsys4", "vppsys5", "vppsys6", "vppsys7",
+						      "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
+						      "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
+						      "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
+						      "vppsys0-12", "vppsys0-13", "vppsys0-14",
+						      "vppsys0-15", "vppsys0-16", "vppsys0-17",
+						      "vppsys0-18";
+					mediatek,infracfg = <&infracfg_ao>;
+					#address-cells = <1>;
+					#size-cells = <0>;
+					#power-domain-cells = <1>;
+
+					power-domain@MT8195_POWER_DOMAIN_VDEC1 {
+						reg = <MT8195_POWER_DOMAIN_VDEC1>;
+						clocks = <&vdecsys CLK_VDEC_LARB1>;
+						clock-names = "vdec1-0";
+						mediatek,infracfg = <&infracfg_ao>;
+						#power-domain-cells = <0>;
+					};
+
+					power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
+						reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
+						mediatek,infracfg = <&infracfg_ao>;
+						#power-domain-cells = <0>;
+					};
+
+					power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
+						reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
+						clocks = <&topckgen CLK_TOP_CFG_VDO0>,
+							 <&vdosys0 CLK_VDO0_SMI_GALS>,
+							 <&vdosys0 CLK_VDO0_SMI_COMMON>,
+							 <&vdosys0 CLK_VDO0_SMI_EMI>,
+							 <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+							 <&vdosys0 CLK_VDO0_SMI_LARB>,
+							 <&vdosys0 CLK_VDO0_SMI_RSI>;
+						clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
+							      "vdosys0-2", "vdosys0-3",
+							      "vdosys0-4", "vdosys0-5";
+						mediatek,infracfg = <&infracfg_ao>;
+						#address-cells = <1>;
+						#size-cells = <0>;
+						#power-domain-cells = <1>;
+
+						power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
+							reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
+							clocks = <&topckgen CLK_TOP_CFG_VPP1>,
+								 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+								 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
+							clock-names = "vppsys1", "vppsys1-0",
+								      "vppsys1-1";
+							mediatek,infracfg = <&infracfg_ao>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_WPESYS {
+							reg = <MT8195_POWER_DOMAIN_WPESYS>;
+							clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+								 <&wpesys CLK_WPE_SMI_LARB8>,
+								 <&wpesys CLK_WPE_SMI_LARB7_P>,
+								 <&wpesys CLK_WPE_SMI_LARB8_P>;
+							clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
+								      "wepsys-3";
+							mediatek,infracfg = <&infracfg_ao>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_VDEC0 {
+							reg = <MT8195_POWER_DOMAIN_VDEC0>;
+							clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+							clock-names = "vdec0-0";
+							mediatek,infracfg = <&infracfg_ao>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_VDEC2 {
+							reg = <MT8195_POWER_DOMAIN_VDEC2>;
+							clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+							clock-names = "vdec2-0";
+							mediatek,infracfg = <&infracfg_ao>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_VENC {
+							reg = <MT8195_POWER_DOMAIN_VENC>;
+							mediatek,infracfg = <&infracfg_ao>;
+							#power-domain-cells = <0>;
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
+							reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
+							clocks = <&topckgen CLK_TOP_CFG_VDO1>,
+								 <&vdosys1 CLK_VDO1_SMI_LARB2>,
+								 <&vdosys1 CLK_VDO1_SMI_LARB3>,
+								 <&vdosys1 CLK_VDO1_GALS>;
+							clock-names = "vdosys1", "vdosys1-0",
+								      "vdosys1-1", "vdosys1-2";
+							mediatek,infracfg = <&infracfg_ao>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <1>;
+
+							power-domain@MT8195_POWER_DOMAIN_DP_TX {
+								reg = <MT8195_POWER_DOMAIN_DP_TX>;
+								mediatek,infracfg = <&infracfg_ao>;
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_EPD_TX {
+								reg = <MT8195_POWER_DOMAIN_EPD_TX>;
+								mediatek,infracfg = <&infracfg_ao>;
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
+								reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
+								clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>;
+								clock-names = "hdmi_tx";
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_HDMI_RX {
+								reg = <MT8195_POWER_DOMAIN_HDMI_RX>;
+								clocks = <&topckgen CLK_TOP_HDMI_APB_SEL>;
+								clock-names = "hdmi_rx";
+								#power-domain-cells = <0>;
+							};
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_IMG {
+							reg = <MT8195_POWER_DOMAIN_IMG>;
+							clocks = <&imgsys CLK_IMG_LARB9>,
+								 <&imgsys CLK_IMG_GALS>;
+							clock-names = "img-0", "img-1";
+							mediatek,infracfg = <&infracfg_ao>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <1>;
+
+							power-domain@MT8195_POWER_DOMAIN_DIP {
+								reg = <MT8195_POWER_DOMAIN_DIP>;
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_IPE {
+								reg = <MT8195_POWER_DOMAIN_IPE>;
+								clocks = <&topckgen CLK_TOP_IPE_SEL>,
+									 <&imgsys CLK_IMG_IPE>,
+									 <&ipesys CLK_IPE_SMI_LARB12>;
+								clock-names = "ipe", "ipe-0", "ipe-1";
+								mediatek,infracfg = <&infracfg_ao>;
+								#power-domain-cells = <0>;
+							};
+						};
+
+						power-domain@MT8195_POWER_DOMAIN_CAM {
+							reg = <MT8195_POWER_DOMAIN_CAM>;
+							clocks = <&camsys CLK_CAM_LARB13>,
+								 <&camsys CLK_CAM_LARB14>,
+								 <&camsys CLK_CAM_CAM2MM0_GALS>,
+								 <&camsys CLK_CAM_CAM2MM1_GALS>,
+								 <&camsys CLK_CAM_CAM2SYS_GALS>;
+							clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
+								      "cam-4";
+							mediatek,infracfg = <&infracfg_ao>;
+							#address-cells = <1>;
+							#size-cells = <0>;
+							#power-domain-cells = <1>;
+
+							power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
+								reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
+								reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
+								#power-domain-cells = <0>;
+							};
+
+							power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
+								reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
+								#power-domain-cells = <0>;
+							};
+						};
+					};
+				};
+			};
+		};
+
 		watchdog: watchdog@10007000 {
 			compatible = "mediatek,mt8195-wdt", "mediatek,mt6589-wdt";
 			reg = <0 0x10007000 0 0x100>;
-- 
2.18.0

[PATCH 08/27] arm64: dts: mt8195: add i2c dts

[Tinghan Shen]

From: Kewei Xu <kewei.xu@mediatek.com>

add i2c dts config for mt8195 soc.

Signed-off-by: Kewei Xu <kewei.xu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 105 +++++++++++++++++++++++
 1 file changed, 105 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5463e7ba1061..9b002bb6d344 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -879,12 +879,117 @@
 			};
 		};
 
+		i2c5: i2c@11d00000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11d00000 0 0x1000>,
+			      <0 0x10220580 0 0x80>;
+			interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c7: i2c@11d02000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11d02000 0 0x1000>,
+			      <0 0x10220680 0 0x80>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		imp_iic_wrap_s: syscon@11d03000 {
 			compatible = "mediatek,mt8195-imp_iic_wrap_s", "syscon";
 			reg = <0 0x11d03000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		i2c0: i2c@11e00000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11e00000 0 0x1000>,
+			      <0 0x10220080 0 0x80>;
+			interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+		};
+
+		i2c1: i2c@11e01000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11e01000 0 0x1000>,
+			      <0 0x10220200 0 0x80>;
+			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@11e02000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11e02000 0 0x1000>,
+			      <0 0x10220380 0 0x80>;
+			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@11e03000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11e03000 0 0x1000>,
+			      <0 0x10220480 0 0x80>;
+			interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@11e04000 {
+			compatible = "mediatek,mt8195-i2c",
+				     "mediatek,mt8192-i2c";
+			reg = <0 0x11e04000 0 0x1000>,
+			      <0 0x10220500 0 0x80>;
+			interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+			clock-div = <1>;
+			clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+				 <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+			clock-names = "main", "dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		imp_iic_wrap_w: syscon@11e05000 {
 			compatible = "mediatek,mt8195-imp_iic_wrap_w", "syscon";
 			reg = <0 0x11e05000 0 0x1000>;
-- 
2.18.0

[PATCH 09/27] arm64: dts: mt8195: add spi controller

[Tinghan Shen]

From: Leilk Liu <leilk.liu@mediatek.com>

add spi controller node into mt8195 SoC

Signed-off-by: Leilk Liu <leilk.liu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 106 +++++++++++++++++++++++
 1 file changed, 106 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 9b002bb6d344..80a272703879 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -818,6 +818,112 @@
 			#clock-cells = <1>;
 		};
 
+		spi0: spi@1100a000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x1100a000 0 0x100>;
+			interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI0>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi1: spi@11010000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11010000 0 0x100>;
+			interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI1>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi2: spi@11012000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11012000 0 0x100>;
+			interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI2>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi3: spi@11013000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11013000 0 0x100>;
+			interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI3>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi4: spi@11018000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11018000 0 0x100>;
+			interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI4>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spi5: spi@11019000 {
+			compatible = "mediatek,mt8195-spi",
+				     "mediatek,mt6765-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0x11019000 0 0x100>;
+			interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+				 <&topckgen CLK_TOP_SPI_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_SPI5>;
+			clock-names = "parent-clk", "sel-clk", "spi-clk";
+			status = "disabled";
+		};
+
+		spis0: spi@1101d000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101d000 0 0x100>;
+			interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
+		spis1: spi@1101e000 {
+			compatible = "mediatek,mt8195-spi-slave";
+			reg = <0 0x1101e000 0 0x100>;
+			interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+			clock-names = "spi";
+			assigned-clocks = <&topckgen CLK_TOP_SPIS_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
-- 
2.18.0

[PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node

[Tinghan Shen]

From: Jianjun Wang <jianjun.wang@mediatek.com>

Add PCIe phy device node for mt8195 SoC.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 80a272703879..dd5644410fea 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1107,6 +1107,7 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0 0 0x11e30000 0xe00>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
 			status = "disabled";
 
 			u2port1: usb-phy@0 {
@@ -1146,6 +1147,19 @@
 			};
 		};
 
+		pciephy: phy@11e80000 {
+			compatible = "mediatek,mt8195-pcie-phy";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			#phy-cells = <0>;
+			reg = <0 0x11e80000 0 0x10000>,
+			      <0 0x11e90000 0 0x10000>;
+			reg-names = "phy-sif", "phy-ckm";
+
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
+			status = "disabled";
+		};
+
 		ufsphy: phy@11fa0000 {
 			compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
 			reg = <0 0x11fa0000 0 0xc000>;
-- 
2.18.0

[PATCH 11/27] arm64: dts: mt8195: add PCIe device node

[Tinghan Shen]

From: Jianjun Wang <jianjun.wang@mediatek.com>

Add PCIe device node for mt8195.

Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 74 ++++++++++++++++++++++++
 1 file changed, 74 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index dd5644410fea..539f405a4f3d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/mt8195-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/power/mt8195-power.h>
 #include <dt-bindings/reset/ti-syscon.h>
@@ -944,6 +945,79 @@
 			status = "disabled";
 		};
 
+		pcie0: pcie@112f0000 {
+			device_type = "pci";
+			compatible = "mediatek,mt8195-pcie";
+			reg = <0 0x112f0000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x20000000
+				  0x0 0x20000000 0 0x4000000>;
+
+			status = "disabled";
+
+			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>,
+				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+
+			phys = <&pciephy>;
+			phy-names = "pcie-phy";
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc0 0>,
+					<0 0 0 2 &pcie_intc0 1>,
+					<0 0 0 3 &pcie_intc0 2>,
+					<0 0 0 4 &pcie_intc0 3>;
+			pcie_intc0: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		pcie1: pcie@112f8000 {
+			device_type = "pci";
+			compatible = "mediatek,mt8195-pcie";
+			reg = <0 0x112f8000 0 0x2000>;
+			reg-names = "pcie-mac";
+			#address-cells = <3>;
+			#size-cells = <2>;
+			interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>;
+			bus-range = <0x00 0xff>;
+			ranges = <0x82000000 0 0x24000000
+				  0x0 0x24000000 0 0x4000000>;
+
+			status = "disabled";
+			clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>,
+				 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>,
+				 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>;
+
+			phys = <&u3port1 PHY_TYPE_PCIE>;
+			phy-names = "pcie-phy";
+			power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0 0 0 1 &pcie_intc1 0>,
+					<0 0 0 2 &pcie_intc1 1>,
+					<0 0 0 3 &pcie_intc1 2>,
+					<0 0 0 4 &pcie_intc1 3>;
+			pcie_intc1: interrupt-controller {
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+
 		nor_flash: nor@1132c000 {
 			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
 			reg = <0 0x1132c000 0 0x1000>;
-- 
2.18.0

[PATCH 12/27] arm64: dts: mt8195: fix mmc driver

[Tinghan Shen]

From: Wenbin Mei <wenbin.mei@mediatek.com>

fix mmc driver with proper clock for mt8195 SoC.

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 539f405a4f3d..327ff1b856d2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -926,22 +926,32 @@
 		};
 
 		mmc0: mmc@11230000 {
-			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+			compatible = "mediatek,mt8195-mmc",
+				     "mediatek,mt8192-mmc",
+				     "mediatek,mt8183-mmc";
 			reg = <0 0x11230000 0 0x10000>,
 			      <0 0x11f50000 0 0x1000>;
 			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
 			clock-names = "source", "hclk", "source_cg";
 			status = "disabled";
 		};
 
 		mmc1: mmc@11240000 {
-			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
+			compatible = "mediatek,mt8195-mmc",
+				     "mediatek,mt8192-mmc",
+				     "mediatek,mt8183-mmc";
 			reg = <0 0x11240000 0 0x1000>,
 			      <0 0x11c70000 0 0x1000>;
 			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&clk26m>, <&clk26m>, <&clk26m>;
+			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
 			clock-names = "source", "hclk", "source_cg";
+			assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
 			status = "disabled";
 		};
 
-- 
2.18.0

Re: [PATCH 12/27] arm64: dts: mt8195: fix mmc driver

[Wenbin Mei]

On Wed, 2021-06-16 at 01:32 +0800, Tinghan Shen wrote:
> From: Wenbin Mei <wenbin.mei@mediatek.com>
> 
> fix mmc driver with proper clock for mt8195 SoC.
> 
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 539f405a4f3d..327ff1b856d2 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -926,22 +926,32 @@
>  		};
>  
>  		mmc0: mmc@11230000 {
> -			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
> +			compatible = "mediatek,mt8195-mmc",
> +				     "mediatek,mt8192-mmc",
> +				     "mediatek,mt8183-mmc";
I have submitted a patch to fix the
dt-bindings(http://lists.infradead.org/pipermail/linux-mediatek/2021-June/025456.html), Now which should be:
	compatible = "mediatek,mt8195-mmc", "mediatek,mt8183-mmc";
>  			reg = <0 0x11230000 0 0x10000>,
>  			      <0 0x11f50000 0 0x1000>;
>  			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
> +				 <&infracfg_ao CLK_INFRA_AO_MSDC0>,
> +				 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
>  			clock-names = "source", "hclk", "source_cg";
>  			status = "disabled";
>  		};
>  
>  		mmc1: mmc@11240000 {
> -			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
> +			compatible = "mediatek,mt8195-mmc",
> +				     "mediatek,mt8192-mmc",
> +				     "mediatek,mt8183-mmc";
Ditto, this should be:
	compatible = "mediatek,mt8195-mmc", "mediatek,mt8183-mmc";
>  			reg = <0 0x11240000 0 0x1000>,
>  			      <0 0x11c70000 0 0x1000>;
>  			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
> -			clocks = <&clk26m>, <&clk26m>, <&clk26m>;
> +			clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
> +				 <&infracfg_ao CLK_INFRA_AO_MSDC1>,
> +				 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
>  			clock-names = "source", "hclk", "source_cg";
> +			assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
>  			status = "disabled";
>  		};
>  

[PATCH 13/27] arm64: dts: mt8195: add hdmi nodes

[Tinghan Shen]

From: James Zheng <james.zheng@mediatek.com>

Add HDMI support for mt8195 SoC.

Signed-off-by: James Zheng <james.zheng@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 84 ++++++++++++++++++++++++
 1 file changed, 84 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 327ff1b856d2..1a281551d011 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -20,6 +20,10 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	aliases {
+		dpi1 = &disp_dpi1;
+	};
+
 	clocks {
 		clk26m: oscillator0 {
 			compatible = "fixed-clock";
@@ -317,6 +321,28 @@
 			interrupt-controller;
 			interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
 			#interrupt-cells = <2>;
+
+			hdmi_pin: hdmipinctrl {
+				hdmi_hotplug {
+					pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>;
+					bias-pull-down;
+				};
+				hdmi_ddc {
+					pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>,
+						<PINMUX_GPIO35__FUNC_HDMITX20_SDA>;
+					mediatek,drive-strength-adv = <0>;
+					drive-strength = <MTK_DRIVE_10mA>;
+				};
+				hdmi_cec {
+					pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>;
+					bias-disable;
+				};
+				hdmi_5vctrl {
+					pinmux = <PINMUX_GPIO31__FUNC_GPIO31>;
+					slew-rate = <1>;
+					output-high;
+				};
+			};
 		};
 
 		scpsys: syscon@10006000 {
@@ -693,6 +719,12 @@
 			#clock-cells = <1>;
 		};
 
+		cec: cec@10014000 {
+			compatible = "mediatek,mt8195-cec";
+			reg = <0 0x10014000 0 0x100>;
+			interrupts = <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		systimer: timer@10017000 {
 			compatible = "mediatek,mt8195-timer", "mediatek,mt6765-timer";
 			reg = <0 0x10017000 0 0x1000>;
@@ -1105,6 +1137,22 @@
 			#clock-cells = <1>;
 		};
 
+		hdmi_phy: hdmi-phy@11d5f000 {
+			compatible = "mediatek,mt8195-hdmi-phy";
+			reg = <0 0x11d5f000 0 0x100>;
+			clocks = <&topckgen CLK_TOP_HDMI_XTAL_SEL>,
+				 <&infracfg_ao CLK_INFRA_AO_HDMI_26M>,
+				 <&apmixedsys CLK_APMIXED_HDMIPLL1>,
+				 <&apmixedsys CLK_APMIXED_HDMIPLL2>;
+			clock-names = "hdmi_xtal_sel",
+				      "hdmi_26m",
+				      "hdmi_pll1",
+				      "hdmi_pll2";
+			clock-output-names = "hdmi_txpll";
+			#clock-cells = <0>;
+			#phy-cells = <0>;
+		};
+
 		i2c0: i2c@11e00000 {
 			compatible = "mediatek,mt8195-i2c",
 				     "mediatek,mt8192-i2c";
@@ -1408,5 +1456,41 @@
 			reg = <0 0x1c100000 0 0x1000>;
 			#clock-cells = <1>;
 		};
+
+		disp_dpi1: disp_dpi1@1c112000 {
+			compatible = "mediatek,mt8195-dpi";
+			reg = <0 0x1c112000 0 0x1000>;
+			interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "pixel", "engine";
+			status = "disabled";
+		};
+
+		hdmi0: hdmi@1c300000 {
+			compatible = "mediatek,mt8195-hdmi";
+			reg = <0 0x1c300000 0 0x1000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_HDMI_TX>;
+			clocks = <&topckgen CLK_TOP_HDCP_SEL>,
+					<&topckgen CLK_TOP_HDCP_24M_SEL>,
+					<&topckgen CLK_TOP_HD20_HDCP_C_SEL>,
+					<&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>;
+			clock-names = "hdcp_sel",
+				      "hdcp24_sel",
+				      "hd20_hdcp_sel",
+				      "split_hdmi";
+			interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&hdmi_pin>;
+			phys = <&hdmi_phy>;
+			phy-names = "hdmi";
+			cec = <&cec>;
+			ddc-i2c-bus = <&hdmiddc0>;
+			status = "disabled";
+		};
+	};
+
+	hdmiddc0: ddc_i2c {
+		compatible = "mediatek,mt8195-hdmi-ddc";
+		clocks = <&clk26m>;
+		clock-names = "ddc-i2c";
 	};
 };
-- 
2.18.0

[PATCH 14/27] arm64: dts: mt8195: add usb support

[Tinghan Shen]

From: Tianping Fang <tianping.fang@mediatek.com>

Add usb support for mt8195 SoC.

Signed-off-by: Tianping Fang <tianping.fang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 110 ++++++++++++++++++++---
 1 file changed, 100 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 1a281551d011..41d9f167701f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -957,6 +957,28 @@
 			status = "disabled";
 		};
 
+		xhci: xhci@11200000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>,
+			      <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port0 PHY_TYPE_USB2>,
+			       <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc",
 				     "mediatek,mt8192-mmc",
@@ -987,6 +1009,70 @@
 			status = "disabled";
 		};
 
+		xhci1: xhci1@11290000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x11290000 0 0x1000>,
+			      <0 0x11293e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port1 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_1P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_1P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P1_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
+		xhci2: xhci2@112a0000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x112a0000 0 0x1000>,
+			      <0 0x112a3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port2 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_2P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_2P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
+		xhci3: xhci3@112b0000 {
+			compatible = "mediatek,mt8195-xhci",
+				     "mediatek,mtk-xhci";
+			reg = <0 0x112b0000 0 0x1000>,
+			      <0 0x112b3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port3 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_3P_SEL>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_3P_SEL>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			usb2-lpm-disable;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			status = "disabled";
+		};
+
 		pcie0: pcie@112f0000 {
 			device_type = "pci";
 			compatible = "mediatek,mt8195-pcie";
@@ -1080,7 +1166,7 @@
 
 			u2port2: usb-phy@0 {
 				reg = <0x0 0x700>;
-				clocks = <&clk26m>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
@@ -1095,7 +1181,7 @@
 
 			u2port3: usb-phy@0 {
 				reg = <0x0 0x700>;
-				clocks = <&clk26m>;
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
 				clock-names = "ref";
 				#phy-cells = <1>;
 			};
@@ -1244,15 +1330,17 @@
 
 			u2port1: usb-phy@0 {
 				reg = <0x0 0x700>;
-				clocks = <&clk26m>;
-				clock-names = "ref";
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+					 <&apmixedsys CLK_APMIXED_USB1PLL>;
+				clock-names = "ref", "da_ref";
 				#phy-cells = <1>;
 			};
 
 			u3port1: usb-phy@700 {
 				reg = <0x700 0x700>;
-				clocks = <&clk26m>;
-				clock-names = "ref";
+				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+					 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+				clock-names = "ref", "da_ref";
 				#phy-cells = <1>;
 			};
 		};
@@ -1266,15 +1354,17 @@
 
 			u2port0: usb-phy@0 {
 				reg = <0x0 0x700>;
-				clocks = <&clk26m>;
-				clock-names = "ref";
+				clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+					 <&apmixedsys CLK_APMIXED_USB1PLL>;
+				clock-names = "ref", "da_ref";
 				#phy-cells = <1>;
 			};
 
 			u3port0: usb-phy@700 {
 				reg = <0x700 0x700>;
-				clocks = <&clk26m>;
-				clock-names = "ref";
+				clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+					 <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+				clock-names = "ref", "da_ref";
 				#phy-cells = <1>;
 			};
 		};
-- 
2.18.0

[PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes

[Tinghan Shen]

From: Yong Wu <yong.wu@mediatek.com>

add smi support for mt8195 SoC.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 445 +++++++++++++++++++++++
 1 file changed, 445 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 41d9f167701f..856b0e938009 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/clock/mt8195-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
 #include <dt-bindings/phy/phy.h>
 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
 #include <dt-bindings/power/mt8195-power.h>
@@ -765,6 +766,17 @@
 			#clock-cells = <1>;
 		};
 
+		iommu_infra: infra-iommu@10315000 {
+			compatible = "mediatek,mt8195-iommu-infra";
+			reg = <0 0x10315000 0 0x1000>,
+			      <0 0x11003000 0 0x1000>;
+			interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>;
+			clock-names = "bclk";
+			#iommu-cells = <1>;
+			status = "disabled";
+		};
+
 		scp_adsp: syscon@10720000 {
 			compatible = "mediatek,mt8195-scp_adsp", "syscon";
 			reg = <0 0x10720000 0 0x1000>;
@@ -1403,6 +1415,55 @@
 			#clock-cells = <1>;
 		};
 
+		smi_common2: smi@1400e000 {
+			compatible = "mediatek,mt8195-smi-common";
+			mediatek,common-id = <2>;
+			reg = <0 0x1400e000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_COMMON>,
+				 <&vppsys0 CLK_VPP0_SMI_COMMON>,
+				 <&vppsys0 CLK_VPP0_GALS_INFRA>,
+				 <&vppsys0 CLK_VPP0_GALS_CAMSYS>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
+		smi_common1: smi@14012000 {
+			compatible = "mediatek,mt8195-smi-common";
+			mediatek,common-id = <1>;
+			reg = <0 0x14012000 0 0x1000>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+				 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+				 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+				 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
+		larb4: larb@14013000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x14013000 0 0x1000>;
+			mediatek,larb-id = <4>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+				 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
+		iommu_vpp: iommu@14018000 {
+			compatible = "mediatek,mt8195-iommu-vpp";
+			reg = <0 0x14018000 0 0x1000>;
+			mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
+					  &larb12 &larb14 &larb16 &larb18
+					  &larb20 &larb22 &larb23 &larb26
+					  &larb27>;
+			interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+			clock-names = "bclk";
+			#iommu-cells = <1>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+		};
+
 		wpesys: syscon@14e00000 {
 			compatible = "mediatek,mt8195-wpesys", "syscon";
 			reg = <0 0x14e00000 0 0x1000>;
@@ -1421,24 +1482,97 @@
 			#clock-cells = <1>;
 		};
 
+		larb7: larb@14e04000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x14e04000 0 0x1000>;
+			mediatek,larb-id = <7>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+				 <&wpesys CLK_WPE_SMI_LARB7>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+		};
+
+		larb8: larb@14e05000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x14e05000 0 0x1000>;
+			mediatek,larb-id = <8>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&wpesys CLK_WPE_SMI_LARB8>,
+				 <&wpesys CLK_WPE_SMI_LARB8>,
+				 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+		};
+
 		vppsys1: syscon@14f00000 {
 			compatible = "mediatek,mt8195-vppsys1", "syscon";
 			reg = <0 0x14f00000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb5: larb@14f02000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x14f02000 0 0x1000>;
+			mediatek,larb-id = <5>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+				 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+		};
+
+		larb6: larb@14f03000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x14f03000 0 0x1000>;
+			mediatek,larb-id = <6>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+				 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+				 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+		};
+
 		imgsys: syscon@15000000 {
 			compatible = "mediatek,mt8195-imgsys", "syscon";
 			reg = <0 0x15000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb9: larb@15001000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x15001000 0 0x1000>;
+			mediatek,larb-id = <9>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+		};
+
 		imgsys1_dip_top: syscon@15110000 {
 			compatible = "mediatek,mt8195-imgsys1_dip_top", "syscon";
 			reg = <0 0x15110000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb10: larb@15120000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x15120000 0 0x1000>;
+			mediatek,larb-id = <10>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&imgsys CLK_IMG_DIP0>,
+				 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>,
+				 <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_GALS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+		};
+
 		imgsys1_dip_nr: syscon@15130000 {
 			compatible = "mediatek,mt8195-imgsys1_dip_nr", "syscon";
 			reg = <0 0x15130000 0 0x1000>;
@@ -1451,18 +1585,122 @@
 			#clock-cells = <1>;
 		};
 
+		larb11: larb@15230000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x15230000 0 0x1000>;
+			mediatek,larb-id = <11>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&imgsys CLK_IMG_WPE0>,
+				 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>,
+				 <&imgsys CLK_IMG_LARB9>,
+				 <&imgsys CLK_IMG_GALS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+		};
+
 		ipesys: syscon@15330000 {
 			compatible = "mediatek,mt8195-ipesys", "syscon";
 			reg = <0 0x15330000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb12: larb@15340000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x15340000 0 0x1000>;
+			mediatek,larb-id = <12>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&imgsys CLK_IMG_IPE>,
+				 <&ipesys CLK_IPE_SMI_LARB12>,
+				 <&imgsys CLK_IMG_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
+		};
+
 		camsys: syscon@16000000 {
 			compatible = "mediatek,mt8195-camsys", "syscon";
 			reg = <0 0x16000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb13: larb@16001000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16001000 0 0x1000>;
+			mediatek,larb-id = <13>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&camsys CLK_CAM_LARB13>,
+				 <&camsys CLK_CAM_LARB13>,
+				 <&camsys CLK_CAM_CAM2MM0_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+		};
+
+		larb14: larb@16002000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16002000 0 0x1000>;
+			mediatek,larb-id = <14>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&camsys CLK_CAM_LARB14>,
+				 <&camsys CLK_CAM_LARB14>,
+				 <&camsys CLK_CAM_CAM2MM1_GALS>,
+				 <&camsys CLK_CAM_CAM2SYS_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1", "gals2";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+		};
+
+		larb16: larb@16012000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16012000 0 0x1000>;
+			mediatek,larb-id = <16>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&camsys CLK_CAM_LARB14>,
+				 <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+				 <&camsys CLK_CAM_CAM2MM1_GALS>,
+				 <&camsys CLK_CAM_CAM2SYS_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1", "gals2";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+		};
+
+		larb17: larb@16013000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16013000 0 0x1000>;
+			mediatek,larb-id = <17>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&camsys CLK_CAM_LARB13>,
+				 <&camsys_yuva CLK_CAM_YUVA_LARBX>,
+				 <&camsys CLK_CAM_CAM2MM0_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+		};
+
+		larb27: larb@16014000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16014000 0 0x1000>;
+			mediatek,larb-id = <27>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&camsys CLK_CAM_LARB14>,
+				 <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+				 <&camsys CLK_CAM_CAM2MM1_GALS>,
+				 <&camsys CLK_CAM_CAM2SYS_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1", "gals2";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+		};
+
+		larb28: larb@16015000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16015000 0 0x1000>;
+			mediatek,larb-id = <28>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&camsys CLK_CAM_LARB13>,
+				 <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+				 <&camsys CLK_CAM_CAM2MM0_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+		};
+
 		camsys_rawa: syscon@1604f000 {
 			compatible = "mediatek,mt8195-camsys_rawa", "syscon";
 			reg = <0 0x1604f000 0 0x1000>;
@@ -1493,30 +1731,135 @@
 			#clock-cells = <1>;
 		};
 
+		larb25: larb@16141000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16141000 0 0x1000>;
+			mediatek,larb-id = <25>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&camsys CLK_CAM_LARB13>,
+				 <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+				 <&camsys CLK_CAM_CAM2MM0_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+		};
+
+		larb26: larb@16142000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x16142000 0 0x1000>;
+			mediatek,larb-id = <26>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&camsys CLK_CAM_LARB14>,
+				<&camsys_mraw CLK_CAM_MRAW_LARBX>,
+				<&camsys CLK_CAM_CAM2MM1_GALS>,
+				<&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+
+		};
+
 		ccusys: syscon@17200000 {
 			compatible = "mediatek,mt8195-ccusys", "syscon";
 			reg = <0 0x17200000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb18: larb@17201000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x17201000 0 0x1000>;
+			mediatek,larb-id = <18>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&camsys CLK_CAM_LARB14>,
+				 <&ccusys CLK_CCU_LARB18>,
+				 <&camsys CLK_CAM_CAM2MM1_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+		};
+
+		larb24: larb@1800d000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1800d000 0 0x1000>;
+			mediatek,larb-id = <24>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+		};
+
+		larb23: larb@1800e000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1800e000 0 0x1000>;
+			mediatek,larb-id = <23>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+				 <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+		};
+
 		vdecsys_soc: syscon@1800f000 {
 			compatible = "mediatek,mt8195-vdecsys_soc", "syscon";
 			reg = <0 0x1800f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb21: larb@1802e000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1802e000 0 0x1000>;
+			mediatek,larb-id = <21>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vdecsys CLK_VDEC_LARB1>,
+				 <&vdecsys CLK_VDEC_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+		};
+
 		vdecsys: syscon@1802f000 {
 			compatible = "mediatek,mt8195-vdecsys", "syscon";
 			reg = <0 0x1802f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb22: larb@1803e000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1803e000 0 0x1000>;
+			mediatek,larb-id = <22>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+				 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+			clock-names = "apb", "smi";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+		};
+
 		vdecsys_core1: syscon@1803f000 {
 			compatible = "mediatek,mt8195-vdecsys_core1", "syscon";
 			reg = <0 0x1803f000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		iommu_apu0: iommu@19010000 {
+			compatible = "mediatek,mt8195-iommu-apu";
+			reg = <0 0x19010000 0 0x1000>;
+			interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>;
+			clock-names = "bclk";
+			#iommu-cells = <1>;
+			/* power-domains = <&apuspm MT8195_POWER_DOMAIN_APUSYS_TOP>; */
+			status = "disabled";
+		};
+
+		iommu_apu1: iommu@19015000 {
+			compatible = "mediatek,mt8195-iommu-apu";
+			reg = <0 0x19015000 0 0x1000>;
+			interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&clk26m>;
+			clock-names = "bclk";
+			#iommu-cells = <1>;
+			/* power-domains = <&apuspm MT8195_POWER_DOMAIN_APUSYS_TOP>; */
+			status = "disabled";
+		};
+
 		apusys_pll: syscon@190f3000 {
 			compatible = "mediatek,mt8195-apusys_pll", "syscon";
 			reg = <0 0x190f3000 0 0x1000>;
@@ -1529,24 +1872,126 @@
 			#clock-cells = <1>;
 		};
 
+		larb19: larb@1a010000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1a010000 0 0x1000>;
+			mediatek,larb-id = <19>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vencsys CLK_VENC_VENC>,
+				 <&vencsys CLK_VENC_LARB>,
+				 <&vencsys CLK_VENC_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_VENCSYS>;
+			clock-names = "apb", "smi", "gals", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+		};
+
 		vencsys_core1: syscon@1b000000 {
 			compatible = "mediatek,mt8195-vencsys_core1", "syscon";
 			reg = <0 0x1b000000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb20: larb@1b010000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1b010000 0 0x1000>;
+			mediatek,larb-id = <20>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>,
+				 <&vencsys_core1 CLK_VENC_CORE1_LARB>,
+				 <&vencsys_core1 CLK_VENC_CORE1_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
+				 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>;
+			clock-names = "apb", "smi", "gals", "gals1", "gals2";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+		};
+
 		vdosys0: syscon@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys0", "syscon";
 			reg = <0 0x1c01a000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		smi_common0: smi@1c01b000 {
+			compatible = "mediatek,mt8195-smi-common";
+			mediatek,common-id = <0>;
+			reg = <0 0x1c01b000 0 0x1000>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+				 <&vdosys0 CLK_VDO0_SMI_COMMON>,
+				 <&vdosys0 CLK_VDO0_SMI_EMI>,
+				 <&vdosys0 CLK_VDO0_SMI_GALS>;
+			clock-names = "apb", "smi", "gals0", "gals1";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+
+		};
+
+		iommu_vdo: iommu@1c01f000 {
+			compatible = "mediatek,mt8195-iommu-vdo";
+			reg = <0 0x1c01f000 0 0x1000>;
+			mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
+					  &larb10 &larb11 &larb13 &larb17
+					  &larb19 &larb21 &larb24 &larb25
+					  &larb28>;
+			interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
+			#iommu-cells = <1>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+			clock-names = "bclk";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		larb0: larb@1c018000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1c018000 0 0x1000>;
+			mediatek,larb-id = <0>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+				 <&vdosys0 CLK_VDO0_SMI_LARB>,
+				 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		larb1: larb@1c019000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1c019000 0 0x1000>;
+			mediatek,larb-id = <1>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
+				 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		vdosys1: syscon@1c100000 {
 			compatible = "mediatek,mt8195-vdosys1", "syscon";
 			reg = <0 0x1c100000 0 0x1000>;
 			#clock-cells = <1>;
 		};
 
+		larb2: larb@1c102000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1c102000 0 0x1000>;
+			mediatek,larb-id = <2>;
+			mediatek,smi = <&smi_common0>;
+			clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+				 <&vdosys1 CLK_VDO1_SMI_LARB2>,
+				 <&vdosys1 CLK_VDO1_GALS>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+		};
+
+		larb3: larb@1c103000 {
+			compatible = "mediatek,mt8195-smi-larb";
+			reg = <0 0x1c103000 0 0x1000>;
+			mediatek,larb-id = <3>;
+			mediatek,smi = <&smi_common1>;
+			clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+				 <&vdosys1 CLK_VDO1_GALS>,
+				 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+			clock-names = "apb", "smi", "gals";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+		};
+
 		disp_dpi1: disp_dpi1@1c112000 {
 			compatible = "mediatek,mt8195-dpi";
 			reg = <0 0x1c112000 0 0x1000>;
-- 
2.18.0

[PATCH 16/27] arm64: dts: mt8195: add display node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add display node.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 856b0e938009..f362288ad828 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1911,6 +1911,82 @@
 			#clock-cells = <1>;
 		};
 
+		vdosys_config@1c01a000 {
+			compatible = "mediatek,mt8195-vdosys";
+			reg = <0 0x1c01a000 0 0x1000>;
+			reg-names = "vdosys0_config";
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		mutex: disp_mutex0@1c016000 {
+			compatible = "mediatek,mt8195-disp-mutex";
+			reg = <0 0x1c016000 0 0x1000>;
+			reg-names = "vdo0_mutex";
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			clock-names = "vdo0_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
+
+		ovl0: disp_ovl@1c000000 {
+			compatible = "mediatek,mt8195-disp-ovl";
+			reg = <0 0x1c000000 0 0x1000>;
+			interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+		};
+
+		rdma0: disp_rdma@1c002000 {
+			compatible = "mediatek,mt8195-disp-rdma";
+			reg = <0 0x1c002000 0 0x1000>;
+			interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+		};
+
+		color0: disp_color@1c003000 {
+			compatible = "mediatek,mt8195-disp-color";
+			reg = <0 0x1c003000 0 0x1000>;
+			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		ccorr0: disp_ccorr@1c004000 {
+			compatible = "mediatek,mt8195-disp-ccorr";
+			reg = <0 0x1c004000 0 0x1000>;
+			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		aal0: disp_aal@1c005000 {
+			compatible = "mediatek,mt8195-disp-aal";
+			reg = <0 0x1c005000 0 0x1000>;
+			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		gamma0: disp_gamma@1c006000 {
+			compatible = "mediatek,mt8195-disp-gamma";
+			reg = <0 0x1c006000 0 0x1000>;
+			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
+		dither0: disp_dither@1c007000 {
+			compatible = "mediatek,mt8195-disp-dither";
+			reg = <0 0x1c007000 0 0x1000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0

Re: [PATCH 16/27] arm64: dts: mt8195: add display node

[Chun-Kuang Hu]

Hi, Tinghan:

Tinghan Shen <tinghan.shen@mediatek.com> 於 2021年6月16日 週三 上午5:37寫道：
>
> From: Jason-JH Lin <jason-jh.lin@mediatek.com>
>
> add display node.
>
> Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 76 ++++++++++++++++++++++++
>  1 file changed, 76 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 856b0e938009..f362288ad828 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -1911,6 +1911,82 @@
>                         #clock-cells = <1>;
>                 };
>
> +               vdosys_config@1c01a000 {
> +                       compatible = "mediatek,mt8195-vdosys";

Where is the definition of this compatible?

> +                       reg = <0 0x1c01a000 0 0x1000>;
> +                       reg-names = "vdosys0_config";
> +                       iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
> +               mutex: disp_mutex0@1c016000 {
> +                       compatible = "mediatek,mt8195-disp-mutex";

Ditto.

> +                       reg = <0 0x1c016000 0 0x1000>;
> +                       reg-names = "vdo0_mutex";
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +                       clock-names = "vdo0_mutex";
> +                       interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
> +               };
> +
> +               ovl0: disp_ovl@1c000000 {
> +                       compatible = "mediatek,mt8195-disp-ovl";

Ditto.

> +                       reg = <0 0x1c000000 0 0x1000>;
> +                       interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +                       iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
> +               };
> +
> +               rdma0: disp_rdma@1c002000 {
> +                       compatible = "mediatek,mt8195-disp-rdma";

Ditto.

> +                       reg = <0 0x1c002000 0 0x1000>;
> +                       interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +                       iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
> +               };
> +
> +               color0: disp_color@1c003000 {
> +                       compatible = "mediatek,mt8195-disp-color";

Ditto.

> +                       reg = <0 0x1c003000 0 0x1000>;
> +                       interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
> +               ccorr0: disp_ccorr@1c004000 {
> +                       compatible = "mediatek,mt8195-disp-ccorr";

Ditto.

> +                       reg = <0 0x1c004000 0 0x1000>;
> +                       interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
> +               aal0: disp_aal@1c005000 {
> +                       compatible = "mediatek,mt8195-disp-aal";

Ditto.

> +                       reg = <0 0x1c005000 0 0x1000>;
> +                       interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
> +               gamma0: disp_gamma@1c006000 {
> +                       compatible = "mediatek,mt8195-disp-gamma";

Ditto.

> +                       reg = <0 0x1c006000 0 0x1000>;
> +                       interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
> +               dither0: disp_dither@1c007000 {
> +                       compatible = "mediatek,mt8195-disp-dither";

Ditto.

> +                       reg = <0 0x1c007000 0 0x1000>;
> +                       interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +               };
> +
>                 smi_common0: smi@1c01b000 {
>                         compatible = "mediatek,mt8195-smi-common";

Ditto.

Regards,
Chun-Kuang.

>                         mediatek,common-id = <0>;
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 17/27] arm64: dts: mt8195: add merge node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add merge node

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index f362288ad828..34f7e99d1fd2 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1987,6 +1987,14 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 		};
 
+		merge0: disp_vpp_merge0@1c014000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c014000 0 0x1000>;
+			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0

[PATCH 18/27] arm64: dts: mt8195: add dsc node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add dsc node

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 34f7e99d1fd2..0399aa8cf994 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1995,6 +1995,14 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 		};
 
+		dsc0: disp_dsc_wrap@1c009000 {
+			compatible = "mediatek,mt8195-disp-dsc";
+			reg = <0 0x1c009000 0 0x1000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
-- 
2.18.0

[PATCH 19/27] arm64: dts: mt8195: add dp_intf node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add dp_intf cnode

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 0399aa8cf994..560a0583ca0b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2003,6 +2003,29 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 		};
 
+		dp_intf0: dp_intf0@1c015000 {
+			status = "disabled";
+			compatible = "mediatek,mt8195-dpintf";
+			reg = <0 0x1c015000 0 0x1000>;
+			interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys0  CLK_VDO0_DP_INTF0>,
+				<&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>,
+				<&topckgen CLK_TOP_EDP_SEL>,
+				<&topckgen CLK_TOP_TVDPLL1_D2>,
+				<&topckgen CLK_TOP_TVDPLL1_D4>,
+				<&topckgen CLK_TOP_TVDPLL1_D8>,
+				<&topckgen CLK_TOP_TVDPLL1_D16>,
+				<&topckgen CLK_TOP_TVDPLL1>;
+			clock-names = "hf_fmm_ck",
+				      "hf_fdp_ck",
+				      "MUX_DP",
+				      "TVDPLL_D2",
+				      "TVDPLL_D4",
+				      "TVDPLL_D8",
+				      "TVDPLL_D16",
+				      "DPI_CK";
+		};
+
 		smi_common0: smi@1c01b000 {
 			compatible = "mediatek,mt8195-smi-common";
 			mediatek,common-id = <0>;
@@ -2113,6 +2136,14 @@
 			ddc-i2c-bus = <&hdmiddc0>;
 			status = "disabled";
 		};
+
+		edp_tx: edp_tx@1c500000 {
+			status = "disabled";
+			compatible = "mediatek,mt8195-dp_tx";
+			reg = <0 0x1c500000 0 0x8000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
+			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
+		};
 	};
 
 	hdmiddc0: ddc_i2c {
-- 
2.18.0

[PATCH 20/27] arm64: dts: mt8195: fix nor_flash node

[Tinghan Shen]

From: Dong Huang <Dong.Huang@mediatek.com>

Fix nor_flash with proper clock for mt8195

Signed-off-by: Dong Huang <Dong.Huang@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 560a0583ca0b..d78cd4d4201b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1162,8 +1162,12 @@
 			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
 			reg = <0 0x1132c000 0 0x1000>;
 			interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
-			clocks = <&clk26m>, <&clk26m>;
-			clock-names = "spi", "sf";
+			clocks = <&topckgen CLK_TOP_SPINOR_SEL>,
+				 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+				 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+			clock-names = "spi", "sf", "axi";
+			assigned-clocks = <&topckgen CLK_TOP_SPINOR_SEL>;
+			assigned-clock-parents = <&clk26m>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-- 
2.18.0

[PATCH 21/27] arm64: dts: mt8195: add audio related nodes

[Tinghan Shen]

From: Trevor Wu <trevor.wu@mediatek.com>

add audio related nodes on dts and dtsi

Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 286 ++++++++++++++++++++++-
 1 file changed, 285 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d78cd4d4201b..256818c4c0bf 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -230,6 +230,12 @@
 		       <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
 	};
 
+	dmic_codec: dmic-codec {
+		compatible = "dmic-codec";
+		num-channels = <2>;
+		wakeup-delay-ms = <50>;
+	};
+
 	pmu-a55 {
 		compatible = "arm,cortex-a55-pmu";
 		interrupt-parent = <&gic>;
@@ -785,8 +791,280 @@
 
 		audsys: syscon@10890000 {
 			compatible = "mediatek,mt8195-audsys", "syscon";
-			reg = <0 0x10890000 0 0x1000>;
+			reg = <0 0x10890000 0 0x10000>;
 			#clock-cells = <1>;
+
+			afe: mt8195-afe-pcm {
+				compatible = "mediatek,mt8195-audio";
+				topckgen = <&topckgen>;
+				power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
+				interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&clk26m>,
+					 <&apmixedsys CLK_APMIXED_APLL1>,
+					 <&apmixedsys CLK_APMIXED_APLL2>,
+					 <&apmixedsys CLK_APMIXED_APLL3>,
+					 <&apmixedsys CLK_APMIXED_APLL4>,
+					 <&apmixedsys CLK_APMIXED_APLL5>,
+					 <&apmixedsys CLK_APMIXED_HDMIRX_APLL>,
+					 <&topckgen CLK_TOP_APLL1>,
+					 <&topckgen CLK_TOP_APLL1_D4>,
+					 <&topckgen CLK_TOP_APLL2>,
+					 <&topckgen CLK_TOP_APLL2_D4>,
+					 <&topckgen CLK_TOP_APLL3>,
+					 <&topckgen CLK_TOP_APLL3_D4>,
+					 <&topckgen CLK_TOP_APLL4>,
+					 <&topckgen CLK_TOP_APLL4_D4>,
+					 <&topckgen CLK_TOP_APLL5>,
+					 <&topckgen CLK_TOP_APLL5_D4>,
+					 <&topckgen CLK_TOP_APLL12_DIV0>,
+					 <&topckgen CLK_TOP_APLL12_DIV1>,
+					 <&topckgen CLK_TOP_APLL12_DIV2>,
+					 <&topckgen CLK_TOP_APLL12_DIV3>,
+					 <&topckgen CLK_TOP_APLL12_DIV4>,
+					 <&topckgen CLK_TOP_APLL12_DIV9>,
+					 <&topckgen CLK_TOP_HDMIRX_APLL>,
+					 <&topckgen CLK_TOP_MAINPLL_D4_D4>,
+					 <&topckgen CLK_TOP_MAINPLL_D5_D2>,
+					 <&topckgen CLK_TOP_MAINPLL_D7_D2>,
+					 <&topckgen CLK_TOP_UNIVPLL_D4>,
+					 <&topckgen CLK_TOP_APLL1_SEL>,
+					 <&topckgen CLK_TOP_APLL2_SEL>,
+					 <&topckgen CLK_TOP_APLL3_SEL>,
+					 <&topckgen CLK_TOP_APLL4_SEL>,
+					 <&topckgen CLK_TOP_APLL5_SEL>,
+					 <&topckgen CLK_TOP_A1SYS_HP_SEL>,
+					 <&topckgen CLK_TOP_A2SYS_SEL>,
+					 <&topckgen CLK_TOP_A3SYS_SEL>,
+					 <&topckgen CLK_TOP_A4SYS_SEL>,
+					 <&topckgen CLK_TOP_ASM_H_SEL>,
+					 <&topckgen CLK_TOP_ASM_M_SEL>,
+					 <&topckgen CLK_TOP_ASM_L_SEL>,
+					 <&topckgen CLK_TOP_AUD_IEC_SEL>,
+					 <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
+					 <&topckgen CLK_TOP_AUDIO_H_SEL>,
+					 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS_SEL>,
+					 <&topckgen CLK_TOP_DPTX_M_SEL>,
+					 <&topckgen CLK_TOP_INTDIR_SEL>,
+					 <&topckgen CLK_TOP_I2SO1_M_SEL>,
+					 <&topckgen CLK_TOP_I2SO2_M_SEL>,
+					 <&topckgen CLK_TOP_I2SI1_M_SEL>,
+					 <&topckgen CLK_TOP_I2SI2_M_SEL>,
+					 <&topckgen CLK_TOP_MPHONE_SLAVE_B>,
+					 <&topckgen CLK_TOP_CFG_26M_AUD>,
+					 <&infracfg_ao CLK_INFRA_AO_AUDIO>,
+					 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
+					 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
+					 <&audsys CLK_AUD_AFE>,
+					 <&audsys CLK_AUD_LRCK_CNT>,
+					 <&audsys CLK_AUD_SPDIFIN_TUNER_APLL>,
+					 <&audsys CLK_AUD_SPDIFIN_TUNER_DBG>,
+					 <&audsys CLK_AUD_UL_TML>,
+					 <&audsys CLK_AUD_APLL1_TUNER>,
+					 <&audsys CLK_AUD_APLL2_TUNER>,
+					 <&audsys CLK_AUD_TOP0_SPDF>,
+					 <&audsys CLK_AUD_APLL>,
+					 <&audsys CLK_AUD_APLL2>,
+					 <&audsys CLK_AUD_DAC>,
+					 <&audsys CLK_AUD_DAC_PREDIS>,
+					 <&audsys CLK_AUD_TML>,
+					 <&audsys CLK_AUD_ADC>,
+					 <&audsys CLK_AUD_DAC_HIRES>,
+					 <&audsys CLK_AUD_A1SYS_HP>,
+					 <&audsys CLK_AUD_AFE_DMIC1>,
+					 <&audsys CLK_AUD_AFE_DMIC2>,
+					 <&audsys CLK_AUD_AFE_DMIC3>,
+					 <&audsys CLK_AUD_AFE_DMIC4>,
+					 <&audsys CLK_AUD_AFE_26M_DMIC_TM>,
+					 <&audsys CLK_AUD_UL_TML_HIRES>,
+					 <&audsys CLK_AUD_ADC_HIRES>,
+					 <&audsys CLK_AUD_ADDA6_ADC>,
+					 <&audsys CLK_AUD_ADDA6_ADC_HIRES>,
+					 <&audsys CLK_AUD_LINEIN_TUNER>,
+					 <&audsys CLK_AUD_EARC_TUNER>,
+					 <&audsys CLK_AUD_I2SIN>,
+					 <&audsys CLK_AUD_TDM_IN>,
+					 <&audsys CLK_AUD_I2S_OUT>,
+					 <&audsys CLK_AUD_TDM_OUT>,
+					 <&audsys CLK_AUD_HDMI_OUT>,
+					 <&audsys CLK_AUD_ASRC11>,
+					 <&audsys CLK_AUD_ASRC12>,
+					 <&audsys CLK_AUD_MULTI_IN>,
+					 <&audsys CLK_AUD_INTDIR>,
+					 <&audsys CLK_AUD_A1SYS>,
+					 <&audsys CLK_AUD_A2SYS>,
+					 <&audsys CLK_AUD_PCMIF>,
+					 <&audsys CLK_AUD_A3SYS>,
+					 <&audsys CLK_AUD_A4SYS>,
+					 <&audsys CLK_AUD_MEMIF_UL1>,
+					 <&audsys CLK_AUD_MEMIF_UL2>,
+					 <&audsys CLK_AUD_MEMIF_UL3>,
+					 <&audsys CLK_AUD_MEMIF_UL4>,
+					 <&audsys CLK_AUD_MEMIF_UL5>,
+					 <&audsys CLK_AUD_MEMIF_UL6>,
+					 <&audsys CLK_AUD_MEMIF_UL8>,
+					 <&audsys CLK_AUD_MEMIF_UL9>,
+					 <&audsys CLK_AUD_MEMIF_UL10>,
+					 <&audsys CLK_AUD_MEMIF_DL2>,
+					 <&audsys CLK_AUD_MEMIF_DL3>,
+					 <&audsys CLK_AUD_MEMIF_DL6>,
+					 <&audsys CLK_AUD_MEMIF_DL7>,
+					 <&audsys CLK_AUD_MEMIF_DL8>,
+					 <&audsys CLK_AUD_MEMIF_DL10>,
+					 <&audsys CLK_AUD_MEMIF_DL11>,
+					 <&audsys CLK_AUD_GASRC0>,
+					 <&audsys CLK_AUD_GASRC1>,
+					 <&audsys CLK_AUD_GASRC2>,
+					 <&audsys CLK_AUD_GASRC3>,
+					 <&audsys CLK_AUD_GASRC4>,
+					 <&audsys CLK_AUD_GASRC5>,
+					 <&audsys CLK_AUD_GASRC6>,
+					 <&audsys CLK_AUD_GASRC7>,
+					 <&audsys CLK_AUD_GASRC8>,
+					 <&audsys CLK_AUD_GASRC9>,
+					 <&audsys CLK_AUD_GASRC10>,
+					 <&audsys CLK_AUD_GASRC11>,
+					 <&audsys CLK_AUD_GASRC12>,
+					 <&audsys CLK_AUD_GASRC13>,
+					 <&audsys CLK_AUD_GASRC14>,
+					 <&audsys CLK_AUD_GASRC15>,
+					 <&audsys CLK_AUD_GASRC16>,
+					 <&audsys CLK_AUD_GASRC17>,
+					 <&audsys CLK_AUD_GASRC18>,
+					 <&audsys CLK_AUD_GASRC19>;
+				clock-names = "clk26m",
+					"apll1",
+					"apll2",
+					"apll3",
+					"apll4",
+					"apll5",
+					"hdmirx_apll",
+					"apll1_ck",
+					"apll1_d4",
+					"apll2_ck",
+					"apll2_d4",
+					"apll3_ck",
+					"apll3_d4",
+					"apll4_ck",
+					"apll4_d4",
+					"apll5_ck",
+					"apll5_d4",
+					"apll12_div0",
+					"apll12_div1",
+					"apll12_div2",
+					"apll12_div3",
+					"apll12_div4",
+					"apll12_div9",
+					"hdmirx_apll_ck",
+					"mainpll_d4_d4",
+					"mainpll_d5_d2",
+					"mainpll_d7_d2",
+					"univpll_d4",
+					"apll1_sel",
+					"apll2_sel",
+					"apll3_sel",
+					"apll4_sel",
+					"apll5_sel",
+					"a1sys_hp_sel",
+					"a2sys_sel",
+					"a3sys_sel",
+					"a4sys_sel",
+					"asm_h_sel",
+					"asm_m_sel",
+					"asm_l_sel",
+					"aud_iec_sel",
+					"aud_intbus_sel",
+					"audio_h_sel",
+					"audio_local_bus_sel",
+					"dptx_m_sel",
+					"intdir_sel",
+					"i2so1_m_sel",
+					"i2so2_m_sel",
+					"i2si1_m_sel",
+					"i2si2_m_sel",
+					"mphone_slave_b",
+					"cfg_26m_aud",
+					"infra_ao_audio",
+					"infra_ao_audio_26m_b",
+					"scp_adsp_audiodsp",
+					"aud_afe",
+					"aud_lrck_cnt",
+					"aud_spdifin_tuner_apll",
+					"aud_spdifin_tuner_dbg",
+					"aud_ul_tml",
+					"aud_apll1_tuner",
+					"aud_apll2_tuner",
+					"aud_top0_spdf",
+					"aud_apll",
+					"aud_apll2",
+					"aud_dac",
+					"aud_dac_predis",
+					"aud_tml",
+					"aud_adc",
+					"aud_dac_hires",
+					"aud_a1sys_hp",
+					"aud_afe_dmic1",
+					"aud_afe_dmic2",
+					"aud_afe_dmic3",
+					"aud_afe_dmic4",
+					"aud_afe_26m_dmic_tm",
+					"aud_ul_tml_hires",
+					"aud_adc_hires",
+					"aud_adda6_adc",
+					"aud_adda6_adc_hires",
+					"aud_linein_tuner",
+					"aud_earc_tuner",
+					"aud_i2sin",
+					"aud_tdm_in",
+					"aud_i2s_out",
+					"aud_tdm_out",
+					"aud_hdmi_out",
+					"aud_asrc11",
+					"aud_asrc12",
+					"aud_multi_in",
+					"aud_intdir",
+					"aud_a1sys",
+					"aud_a2sys",
+					"aud_pcmif",
+					"aud_a3sys",
+					"aud_a4sys",
+					"aud_memif_ul1",
+					"aud_memif_ul2",
+					"aud_memif_ul3",
+					"aud_memif_ul4",
+					"aud_memif_ul5",
+					"aud_memif_ul6",
+					"aud_memif_ul8",
+					"aud_memif_ul9",
+					"aud_memif_ul10",
+					"aud_memif_dl2",
+					"aud_memif_dl3",
+					"aud_memif_dl6",
+					"aud_memif_dl7",
+					"aud_memif_dl8",
+					"aud_memif_dl10",
+					"aud_memif_dl11",
+					"aud_gasrc0",
+					"aud_gasrc1",
+					"aud_gasrc2",
+					"aud_gasrc3",
+					"aud_gasrc4",
+					"aud_gasrc5",
+					"aud_gasrc6",
+					"aud_gasrc7",
+					"aud_gasrc8",
+					"aud_gasrc9",
+					"aud_gasrc10",
+					"aud_gasrc11",
+					"aud_gasrc12",
+					"aud_gasrc13",
+					"aud_gasrc14",
+					"aud_gasrc15",
+					"aud_gasrc16",
+					"aud_gasrc17",
+					"aud_gasrc18",
+					"aud_gasrc19";
+				status = "disabled";
+			};
 		};
 
 		audsys_src: syscon@108a0000 {
@@ -2155,4 +2433,10 @@
 		clocks = <&clk26m>;
 		clock-names = "ddc-i2c";
 	};
+
+	sound: mt8195-sound {
+		compatible = "mediatek,mt8195_mt6359_rt1019_rt5682";
+		mediatek,platform = <&afe>;
+		status = "disabled";
+	};
 };
-- 
2.18.0

[PATCH 22/27] arm64: dts: mt8195: add edp nodes

[Tinghan Shen]

From: Jitao Shi <jitao.shi@mediatek.com>

add edp nodes for mt8195

Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 256818c4c0bf..d7d2c2a8f461 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -23,6 +23,8 @@
 
 	aliases {
 		dpi1 = &disp_dpi1;
+		dp-intf0 = &dp_intf0;
+		dp-intf1 = &dp_intf1;
 	};
 
 	clocks {
@@ -1155,6 +1157,29 @@
 			status = "disabled";
 		};
 
+		disp_pwm0: disp_pwm0@1100e000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100e000 0 0x1000>;
+			interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>,
+					<&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
+		disp_pwm1: disp_pwm1@1100f000 {
+			compatible = "mediatek,mt8183-disp-pwm";
+			reg = <0 0x1100f000 0 0x1000>;
+			interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
+			#pwm-cells = <2>;
+			clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>,
+				<&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
+			clock-names = "main", "mm";
+			status = "disabled";
+		};
+
 		spi1: spi@11010000 {
 			compatible = "mediatek,mt8195-spi",
 				     "mediatek,mt6765-spi";
@@ -2397,6 +2422,30 @@
 			status = "disabled";
 		};
 
+		dp_intf1: dp_intf1@1c113000 {
+			compatible = "mediatek,mt8195-dp-intf";
+			reg = <0 0x1c113000 0 0x1000>;
+			interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+			clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
+				 <&vdosys1 CLK_VDO1_DPINTF>,
+				 <&topckgen CLK_TOP_DP_SEL>,
+				 <&topckgen CLK_TOP_TVDPLL2_D2>,
+				 <&topckgen CLK_TOP_TVDPLL2_D4>,
+				 <&topckgen CLK_TOP_TVDPLL2_D8>,
+				 <&topckgen CLK_TOP_TVDPLL2_D16>,
+				 <&topckgen CLK_TOP_TVDPLL2>;
+			clock-names = "hf_fmm_ck",
+				      "hf_fdp_ck",
+				      "MUX_DP",
+				      "TVDPLL_D2",
+				      "TVDPLL_D4",
+				      "TVDPLL_D8",
+				      "TVDPLL_D16",
+				      "DPI_CK";
+			status = "disabled";
+		};
+
 		hdmi0: hdmi@1c300000 {
 			compatible = "mediatek,mt8195-hdmi";
 			reg = <0 0x1c300000 0 0x1000>;
@@ -2421,11 +2470,19 @@
 
 		edp_tx: edp_tx@1c500000 {
 			status = "disabled";
-			compatible = "mediatek,mt8195-dp_tx";
+			compatible = "mediatek,mt8195-edp_tx";
 			reg = <0 0x1c500000 0 0x8000>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
 			interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
 		};
+
+		dp_tx: dp_tx@1c600000 {
+			compatible = "mediatek,mt8195-dp_tx";
+			reg = <0 0x1c600000 0 0x8000>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
+			interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
+			status = "disabled";
+		};
 	};
 
 	hdmiddc0: ddc_i2c {
-- 
2.18.0

Re: [PATCH 22/27] arm64: dts: mt8195: add edp nodes

[Chun-Kuang Hu]

Hi, Tinghan:

Tinghan Shen <tinghan.shen@mediatek.com> 於 2021年6月16日 週三 上午5:35寫道：
>
> From: Jitao Shi <jitao.shi@mediatek.com>
>
> add edp nodes for mt8195
>
> Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 59 +++++++++++++++++++++++-
>  1 file changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index 256818c4c0bf..d7d2c2a8f461 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -23,6 +23,8 @@
>
>         aliases {
>                 dpi1 = &disp_dpi1;
> +               dp-intf0 = &dp_intf0;
> +               dp-intf1 = &dp_intf1;
>         };
>
>         clocks {
> @@ -1155,6 +1157,29 @@
>                         status = "disabled";
>                 };
>
> +               disp_pwm0: disp_pwm0@1100e000 {
> +                       compatible = "mediatek,mt8183-disp-pwm";

You should use

compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";

and add definition of "mediatek,mt8195-disp-pwm" in binding document.

> +                       reg = <0 0x1100e000 0 0x1000>;
> +                       interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> +                       #pwm-cells = <2>;
> +                       clocks = <&topckgen CLK_TOP_DISP_PWM0_SEL>,
> +                                       <&infracfg_ao CLK_INFRA_AO_DISP_PWM>;
> +                       clock-names = "main", "mm";
> +                       status = "disabled";
> +               };
> +
> +               disp_pwm1: disp_pwm1@1100f000 {
> +                       compatible = "mediatek,mt8183-disp-pwm";

Ditto.

> +                       reg = <0 0x1100f000 0 0x1000>;
> +                       interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       #pwm-cells = <2>;
> +                       clocks = <&topckgen CLK_TOP_DISP_PWM1_SEL>,
> +                               <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>;
> +                       clock-names = "main", "mm";
> +                       status = "disabled";
> +               };
> +
>                 spi1: spi@11010000 {
>                         compatible = "mediatek,mt8195-spi",
>                                      "mediatek,mt6765-spi";
> @@ -2397,6 +2422,30 @@
>                         status = "disabled";
>                 };
>
> +               dp_intf1: dp_intf1@1c113000 {
> +                       compatible = "mediatek,mt8195-dp-intf";

Where is the definition of this compatible?

> +                       reg = <0 0x1c113000 0 0x1000>;
> +                       interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +                       clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>,
> +                                <&vdosys1 CLK_VDO1_DPINTF>,
> +                                <&topckgen CLK_TOP_DP_SEL>,
> +                                <&topckgen CLK_TOP_TVDPLL2_D2>,
> +                                <&topckgen CLK_TOP_TVDPLL2_D4>,
> +                                <&topckgen CLK_TOP_TVDPLL2_D8>,
> +                                <&topckgen CLK_TOP_TVDPLL2_D16>,
> +                                <&topckgen CLK_TOP_TVDPLL2>;
> +                       clock-names = "hf_fmm_ck",
> +                                     "hf_fdp_ck",
> +                                     "MUX_DP",
> +                                     "TVDPLL_D2",
> +                                     "TVDPLL_D4",
> +                                     "TVDPLL_D8",
> +                                     "TVDPLL_D16",
> +                                     "DPI_CK";
> +                       status = "disabled";
> +               };
> +
>                 hdmi0: hdmi@1c300000 {
>                         compatible = "mediatek,mt8195-hdmi";
>                         reg = <0 0x1c300000 0 0x1000>;
> @@ -2421,11 +2470,19 @@
>
>                 edp_tx: edp_tx@1c500000 {
>                         status = "disabled";
> -                       compatible = "mediatek,mt8195-dp_tx";
> +                       compatible = "mediatek,mt8195-edp_tx";
>                         reg = <0 0x1c500000 0 0x8000>;
>                         power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
>                         interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>;
>                 };
> +
> +               dp_tx: dp_tx@1c600000 {
> +                       compatible = "mediatek,mt8195-dp_tx";

Ditto.

Regards,
Chun-Kuang.

> +                       reg = <0 0x1c600000 0 0x8000>;
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
> +                       interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       status = "disabled";
> +               };
>         };
>
>         hdmiddc0: ddc_i2c {
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 23/27] arm64: dts: mt8195: add gce node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add gce node on dts file.

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d7d2c2a8f461..51edb8ee35a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -7,6 +7,7 @@
 /dts-v1/;
 
 #include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/memory/mt8195-memory-port.h>
@@ -1075,6 +1076,26 @@
 			#clock-cells = <1>;
 		};
 
+		gce0: mdp_mailbox@10320000 {
+			compatible = "mediatek,mt8195-gce";
+			reg = <0 0x10320000 0 0x4000>;
+			interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+				 <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce0", "gce1";
+		};
+
+		gce1: disp_mailbox@10330000 {
+			compatible = "mediatek,mt8195-gce";
+			reg = <0 0x10330000 0 0x4000>;
+			interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+			#mbox-cells = <3>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+				 <&infracfg_ao CLK_INFRA_AO_GCE2>;
+			clock-names = "gce0", "gce1";
+		};
+
 		uart0: serial@11001100 {
 			compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
 			reg = <0 0x11001100 0 0x100>;
-- 
2.18.0

Re: [PATCH 23/27] arm64: dts: mt8195: add gce node

[Chun-Kuang Hu]

Hi, Tinghan:

Tinghan Shen <tinghan.shen@mediatek.com> 於 2021年6月16日 週三 上午5:35寫道：
>
> From: Jason-JH Lin <jason-jh.lin@mediatek.com>
>
> add gce node on dts file.
>
> Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index d7d2c2a8f461..51edb8ee35a8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -7,6 +7,7 @@
>  /dts-v1/;
>
>  #include <dt-bindings/clock/mt8195-clk.h>
> +#include <dt-bindings/gce/mt8195-gce.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/memory/mt8195-memory-port.h>
> @@ -1075,6 +1076,26 @@
>                         #clock-cells = <1>;
>                 };
>
> +               gce0: mdp_mailbox@10320000 {
> +                       compatible = "mediatek,mt8195-gce";

Where is the definition of this compatible?

> +                       reg = <0 0x10320000 0 0x4000>;
> +                       interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       #mbox-cells = <3>;
> +                       clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> +                                <&infracfg_ao CLK_INFRA_AO_GCE2>;
> +                       clock-names = "gce0", "gce1";

According to the binding document [1], clock-names should be "gce".

[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/mailbox/mtk-gce.txt

Regards,
Chun-Kuang.

> +               };
> +
> +               gce1: disp_mailbox@10330000 {
> +                       compatible = "mediatek,mt8195-gce";
> +                       reg = <0 0x10330000 0 0x4000>;
> +                       interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       #mbox-cells = <3>;
> +                       clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> +                                <&infracfg_ao CLK_INFRA_AO_GCE2>;
> +                       clock-names = "gce0", "gce1";
> +               };
> +
>                 uart0: serial@11001100 {
>                         compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
>                         reg = <0 0x11001100 0 0x100>;
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node

[Tinghan Shen]

From: Jason-JH Lin <jason-jh.lin@mediatek.com>

add gce setting for disply node

Signed-off-by: Jason-JH Lin <jason-jh.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 51edb8ee35a8..e273833a49f8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2245,6 +2245,7 @@
 			reg-names = "vdosys0_config";
 			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
 		};
 
 		mutex: disp_mutex0@1c016000 {
@@ -2255,6 +2256,7 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 			clock-names = "vdo0_mutex";
 			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
 		};
 
 		ovl0: disp_ovl@1c000000 {
@@ -2264,6 +2266,7 @@
 			clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 			iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
 		};
 
 		rdma0: disp_rdma@1c002000 {
@@ -2273,6 +2276,7 @@
 			clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
 			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
 		};
 
 		color0: disp_color@1c003000 {
@@ -2281,6 +2285,7 @@
 			interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
 		};
 
 		ccorr0: disp_ccorr@1c004000 {
@@ -2289,6 +2294,7 @@
 			interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
 		};
 
 		aal0: disp_aal@1c005000 {
@@ -2297,6 +2303,7 @@
 			interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
 		};
 
 		gamma0: disp_gamma@1c006000 {
@@ -2305,6 +2312,7 @@
 			interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
 		};
 
 		dither0: disp_dither@1c007000 {
@@ -2313,6 +2321,7 @@
 			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
 		};
 
 		merge0: disp_vpp_merge0@1c014000 {
@@ -2321,6 +2330,7 @@
 			interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
 		};
 
 		dsc0: disp_dsc_wrap@1c009000 {
@@ -2329,6 +2339,7 @@
 			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
 			clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
 		};
 
 		dp_intf0: dp_intf0@1c015000 {
-- 
2.18.0

[PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195

[Tinghan Shen]

From: Nancy Lin <nancy.lin@mediatek.com>

add vdosys1 support for MT8195

Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 178 +++++++++++++++++++++--
 1 file changed, 169 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e273833a49f8..a98609989905 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
 		dpi1 = &disp_dpi1;
 		dp-intf0 = &dp_intf0;
 		dp-intf1 = &dp_intf1;
+		merge5 = &merge5;
 	};
 
 	clocks {
@@ -2241,22 +2242,27 @@
 
 		vdosys_config@1c01a000 {
 			compatible = "mediatek,mt8195-vdosys";
-			reg = <0 0x1c01a000 0 0x1000>;
-			reg-names = "vdosys0_config";
+			reg = <0 0x1c01a000 0 0x1000>,<0 0x1c100000 0 0x1000>;
+			reg-names = "vdosys0_config","vdosys1_config";
 			iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
-			mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
+			mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>,
+				 <&gce1 1 0 CMDQ_THR_PRIO_4>;
 		};
 
 		mutex: disp_mutex0@1c016000 {
 			compatible = "mediatek,mt8195-disp-mutex";
-			reg = <0 0x1c016000 0 0x1000>;
-			reg-names = "vdo0_mutex";
-			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+			reg = <0 0x1c016000 0 0x1000>,
+			      <0 0x1c101000 0 0x1000>;
+			reg-names = "vdo0_mutex","vdo1_mutex";
+			clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>,
+				 <&vdosys1 CLK_VDO1_DISP_MUTEX>;
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
-			clock-names = "vdo0_mutex";
-			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
-			mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+			clock-names = "vdo0_mutex","sub_mutex";
+			interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
+				     <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+			mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>,
+					       <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
 		};
 
 		ovl0: disp_ovl@1c000000 {
@@ -2446,6 +2452,92 @@
 			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
 		};
 
+		disp_pseudo_ovl0@1c104000 {
+			compatible = "mediatek,mt8195-disp-pseudo-ovl";
+			reg = <0 0x1c104000 0 0x1000>,
+			      <0 0x1c105000 0 0x1000>,
+			      <0 0x1c106000 0 0x1000>,
+			      <0 0x1c107000 0 0x1000>,
+			      <0 0x1c108000 0 0x1000>,
+			      <0 0x1c109000 0 0x1000>,
+			      <0 0x1c10A000 0 0x1000>,
+			      <0 0x1c10B000 0 0x1000>,
+			      <0 0x1c10C000 0 0x1000>,
+			      <0 0x1c10D000 0 0x1000>,
+			      <0 0x1c10E000 0 0x1000>,
+			      <0 0x1c10F000 0 0x1000>,
+			      <0 0x1c100000 0 0x1000>;
+			reg-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1","vdo1_mdp_rdma2",
+				    "vdo1_mdp_rdma3","vdo1_mdp_rdma4",
+				    "vdo1_mdp_rdma5","vdo1_mdp_rdma6",
+				    "vdo1_mdp_rdma7","vdo1_merge0",
+				    "vdo1_merge1","vdo1_merge2","vdo1_merge3","top";
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xA000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xB000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xC000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xD000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xE000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0xF000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
+			clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA1>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA2>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA3>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA4>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA5>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA6>,
+				 <&vdosys1 CLK_VDO1_MDP_RDMA7>,
+				 <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+				 <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+				 <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+				 <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+				 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+			clock-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1",
+				      "vdo1_mdp_rdma2","vdo1_mdp_rdma3",
+				      "vdo1_mdp_rdma4","vdo1_mdp_rdma5",
+				      "vdo1_mdp_rdma6","vdo1_mdp_rdma7",
+				      "vdo1_merge0","vdo1_merge1",
+				      "vdo1_merge2","vdo1_merge3",
+				      "vdo1_merge0_async","vdo1_merge1_async",
+				      "vdo1_merge2_async","vdo1_merge3_async";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+			mediatek,larb = <&larb2>;
+			mediatek,smi-id = <0>;
+			iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+			interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma0*/
+				     <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma1*/
+				     <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma2*/
+				     <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma3*/
+				     <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma4*/
+				     <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma5*/
+				     <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma6*/
+				     <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma7*/
+				     <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>, /*merge0*/
+				     <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>, /*merge1*/
+				     <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>, /*merge2*/
+				     <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; /*merge3*/
+		};
+
+		merge5: disp_vpp_merge5@1c110000 {
+			compatible = "mediatek,mt8195-disp-merge";
+			reg = <0 0x1c110000 0 0x1000>;
+			interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+			clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+				 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+			clock-names = "merge5","merge5_async";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+		};
+
 		disp_dpi1: disp_dpi1@1c112000 {
 			compatible = "mediatek,mt8195-dpi";
 			reg = <0 0x1c112000 0 0x1000>;
@@ -2478,6 +2570,54 @@
 			status = "disabled";
 		};
 
+		disp_ethdr@1c114000 {
+			compatible = "mediatek,mt8195-disp-ethdr";
+			reg = <0 0x1c114000 0 0x1000>,
+			      <0 0x1c115000 0 0x1000>,
+			      <0 0x1c117000 0 0x1000>,
+			      <0 0x1c119000 0 0x1000>,
+			      <0 0x1c11A000 0 0x1000>,
+			      <0 0x1c11B000 0 0x1000>,
+			      <0 0x1c11C000 0 0x1000>,
+			      <0 0x1c100000 0 0x1000>;
+			reg-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
+				    "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
+				    "hdr_adl_ds","top";
+			mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+						  <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>,
+						  <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
+			clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+				 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+				 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+				 <&vdosys1 CLK_VDO1_26M_SLOW>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+				 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+				 <&topckgen CLK_TOP_ETHDR_SEL>;
+			clock-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
+				      "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
+				      "hdr_adl_ds","hdr_vdo_fe0_async",
+				      "hdr_vdo_fe1_async","hdr_gfx_fe0_async",
+				      "hdr_gfx_fe1_async","hdr_vdo_be_async",
+				      "ethdr_top";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+			mediatek,larb = <&larb3>;
+			mediatek,smi-id = <1>;
+			iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+				 <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+			interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*disp mixer*/
+		};
+
 		hdmi0: hdmi@1c300000 {
 			compatible = "mediatek,mt8195-hdmi";
 			reg = <0 0x1c300000 0 0x1000>;
@@ -2517,6 +2657,26 @@
 		};
 	};
 
+	disp_pseudo_ovl_l2 {
+		compatible = "mediatek,mt8195-pseudo-ovl-larb";
+		mediatek,larb-id = <2>;
+		power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+		iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>,
+			 <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>,
+			 <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>,
+			 <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+	};
+
+	disp_pseudo_ovl_l3 {
+		compatible = "mediatek,mt8195-pseudo-ovl-larb";
+		mediatek,larb-id = <3>;
+		power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+		iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>,
+			 <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>,
+			 <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>,
+			 <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+	};
+
 	hdmiddc0: ddc_i2c {
 		compatible = "mediatek,mt8195-hdmi-ddc";
 		clocks = <&clk26m>;
-- 
2.18.0

Re: [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195

[Chun-Kuang Hu]

Hi, Tinghan:

Tinghan Shen <tinghan.shen@mediatek.com> 於 2021年6月16日 週三 上午5:39寫道：
>
> From: Nancy Lin <nancy.lin@mediatek.com>
>
> add vdosys1 support for MT8195
>
> Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 178 +++++++++++++++++++++--
>  1 file changed, 169 insertions(+), 9 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index e273833a49f8..a98609989905 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -26,6 +26,7 @@
>                 dpi1 = &disp_dpi1;
>                 dp-intf0 = &dp_intf0;
>                 dp-intf1 = &dp_intf1;
> +               merge5 = &merge5;
>         };
>
>         clocks {
> @@ -2241,22 +2242,27 @@
>
>                 vdosys_config@1c01a000 {
>                         compatible = "mediatek,mt8195-vdosys";
> -                       reg = <0 0x1c01a000 0 0x1000>;
> -                       reg-names = "vdosys0_config";
> +                       reg = <0 0x1c01a000 0 0x1000>,<0 0x1c100000 0 0x1000>;
> +                       reg-names = "vdosys0_config","vdosys1_config";
>                         iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
>                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> -                       mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
> +                       mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>,
> +                                <&gce1 1 0 CMDQ_THR_PRIO_4>;
>                 };
>
>                 mutex: disp_mutex0@1c016000 {
>                         compatible = "mediatek,mt8195-disp-mutex";
> -                       reg = <0 0x1c016000 0 0x1000>;
> -                       reg-names = "vdo0_mutex";
> -                       clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
> +                       reg = <0 0x1c016000 0 0x1000>,
> +                             <0 0x1c101000 0 0x1000>;
> +                       reg-names = "vdo0_mutex","vdo1_mutex";
> +                       clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>,
> +                                <&vdosys1 CLK_VDO1_DISP_MUTEX>;
>                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
> -                       clock-names = "vdo0_mutex";
> -                       interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
> -                       mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
> +                       clock-names = "vdo0_mutex","sub_mutex";
> +                       interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
> +                                    <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>,
> +                                              <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
>                 };
>
>                 ovl0: disp_ovl@1c000000 {
> @@ -2446,6 +2452,92 @@
>                         power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
>                 };
>
> +               disp_pseudo_ovl0@1c104000 {
> +                       compatible = "mediatek,mt8195-disp-pseudo-ovl";

Where is the definition of this compatible?

> +                       reg = <0 0x1c104000 0 0x1000>,
> +                             <0 0x1c105000 0 0x1000>,
> +                             <0 0x1c106000 0 0x1000>,
> +                             <0 0x1c107000 0 0x1000>,
> +                             <0 0x1c108000 0 0x1000>,
> +                             <0 0x1c109000 0 0x1000>,
> +                             <0 0x1c10A000 0 0x1000>,
> +                             <0 0x1c10B000 0 0x1000>,
> +                             <0 0x1c10C000 0 0x1000>,
> +                             <0 0x1c10D000 0 0x1000>,
> +                             <0 0x1c10E000 0 0x1000>,
> +                             <0 0x1c10F000 0 0x1000>,
> +                             <0 0x1c100000 0 0x1000>;
> +                       reg-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1","vdo1_mdp_rdma2",
> +                                   "vdo1_mdp_rdma3","vdo1_mdp_rdma4",
> +                                   "vdo1_mdp_rdma5","vdo1_mdp_rdma6",
> +                                   "vdo1_mdp_rdma7","vdo1_merge0",
> +                                   "vdo1_merge1","vdo1_merge2","vdo1_merge3","top";
> +                       mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xA000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xB000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xC000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xD000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xE000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0xF000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
> +                       clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA1>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA2>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA3>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA4>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA5>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA6>,
> +                                <&vdosys1 CLK_VDO1_MDP_RDMA7>,
> +                                <&vdosys1 CLK_VDO1_VPP_MERGE0>,
> +                                <&vdosys1 CLK_VDO1_VPP_MERGE1>,
> +                                <&vdosys1 CLK_VDO1_VPP_MERGE2>,
> +                                <&vdosys1 CLK_VDO1_VPP_MERGE3>,
> +                                <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
> +                       clock-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1",
> +                                     "vdo1_mdp_rdma2","vdo1_mdp_rdma3",
> +                                     "vdo1_mdp_rdma4","vdo1_mdp_rdma5",
> +                                     "vdo1_mdp_rdma6","vdo1_mdp_rdma7",
> +                                     "vdo1_merge0","vdo1_merge1",
> +                                     "vdo1_merge2","vdo1_merge3",
> +                                     "vdo1_merge0_async","vdo1_merge1_async",
> +                                     "vdo1_merge2_async","vdo1_merge3_async";
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +                       mediatek,larb = <&larb2>;
> +                       mediatek,smi-id = <0>;
> +                       iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
> +                       interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma0*/
> +                                    <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma1*/
> +                                    <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma2*/
> +                                    <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma3*/
> +                                    <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma4*/
> +                                    <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma5*/
> +                                    <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma6*/
> +                                    <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma7*/
> +                                    <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>, /*merge0*/
> +                                    <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>, /*merge1*/
> +                                    <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>, /*merge2*/
> +                                    <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; /*merge3*/
> +               };
> +
> +               merge5: disp_vpp_merge5@1c110000 {
> +                       compatible = "mediatek,mt8195-disp-merge";

Ditto.

> +                       reg = <0 0x1c110000 0 0x1000>;
> +                       interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
> +                       clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
> +                                <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
> +                       clock-names = "merge5","merge5_async";
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +                       mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
> +               };
> +
>                 disp_dpi1: disp_dpi1@1c112000 {
>                         compatible = "mediatek,mt8195-dpi";
>                         reg = <0 0x1c112000 0 0x1000>;
> @@ -2478,6 +2570,54 @@
>                         status = "disabled";
>                 };
>
> +               disp_ethdr@1c114000 {
> +                       compatible = "mediatek,mt8195-disp-ethdr";

Ditto.

> +                       reg = <0 0x1c114000 0 0x1000>,
> +                             <0 0x1c115000 0 0x1000>,
> +                             <0 0x1c117000 0 0x1000>,
> +                             <0 0x1c119000 0 0x1000>,
> +                             <0 0x1c11A000 0 0x1000>,
> +                             <0 0x1c11B000 0 0x1000>,
> +                             <0 0x1c11C000 0 0x1000>,
> +                             <0 0x1c100000 0 0x1000>;
> +                       reg-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
> +                                   "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
> +                                   "hdr_adl_ds","top";
> +                       mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>,
> +                                                 <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
> +                       clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
> +                                <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
> +                                <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
> +                                <&vdosys1 CLK_VDO1_26M_SLOW>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
> +                                <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
> +                                <&topckgen CLK_TOP_ETHDR_SEL>;
> +                       clock-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
> +                                     "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
> +                                     "hdr_adl_ds","hdr_vdo_fe0_async",
> +                                     "hdr_vdo_fe1_async","hdr_gfx_fe0_async",
> +                                     "hdr_gfx_fe1_async","hdr_vdo_be_async",
> +                                     "ethdr_top";
> +                       power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +                       mediatek,larb = <&larb3>;
> +                       mediatek,smi-id = <1>;
> +                       iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
> +                                <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
> +                       interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*disp mixer*/
> +               };
> +
>                 hdmi0: hdmi@1c300000 {
>                         compatible = "mediatek,mt8195-hdmi";
>                         reg = <0 0x1c300000 0 0x1000>;
> @@ -2517,6 +2657,26 @@
>                 };
>         };
>
> +       disp_pseudo_ovl_l2 {
> +               compatible = "mediatek,mt8195-pseudo-ovl-larb";

Ditto.

> +               mediatek,larb-id = <2>;
> +               power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +               iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>,
> +                        <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>,
> +                        <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>,
> +                        <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
> +       };
> +
> +       disp_pseudo_ovl_l3 {
> +               compatible = "mediatek,mt8195-pseudo-ovl-larb";

Ditto.

Regards,
Chun-Kuang.

> +               mediatek,larb-id = <3>;
> +               power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
> +               iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>,
> +                        <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>,
> +                        <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>,
> +                        <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
> +       };
> +
>         hdmiddc0: ddc_i2c {
>                 compatible = "mediatek,mt8195-hdmi-ddc";
>                 clocks = <&clk26m>;
> --
> 2.18.0
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

[PATCH 26/27] arm64: dts: mt8195: add scp device node

[Tinghan Shen]

add scp node for mt8195

Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a98609989905..25a6ee7c6659 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -787,6 +787,16 @@
 			status = "disabled";
 		};
 
+		scp: scp@10500000 {
+			compatible = "mediatek,mt8195-scp";
+			reg = <0 0x10500000 0 0x100000>,
+			      <0 0x10700000 0 0x8000>,
+			      <0 0x10720000 0 0xe0000>;
+			reg-names = "sram", "l1tcm", "cfg";
+			interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+			status = "okay";
+		};
+
 		scp_adsp: syscon@10720000 {
 			compatible = "mediatek,mt8195-scp_adsp", "syscon";
 			reg = <0 0x10720000 0 0x1000>;
-- 
2.18.0

[PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes

[Tinghan Shen]

From: YT Lee <yt.lee@mediatek.corp-partner.google.com>

this 8195 cpufreq device nodes is based on below dt-bindings document
https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-3-git-send-email-hector.yuan@mediatek.com/

and it also rely on below patches to work
[1]https://patchwork.kernel.org/project/linux-mediatek/patch/1615549235-27700-2-git-send-email-hector.yuan@mediatek.com/
[2]https://patchwork.kernel.org/project/linux-pm/patch/20201105125001.32473-1-lukasz.luba@arm.com/
[3]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-3-lukasz.luba@arm.com/
[4]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-4-lukasz.luba@arm.com/
[5]https://patchwork.kernel.org/project/linux-pm/patch/20201103090600.29053-5-lukasz.luba@arm.com/

Signed-off-by: YT Lee <yt.lee@mediatek.corp-partner.google.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 25a6ee7c6659..e5ebf8d663df 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -54,6 +54,7 @@
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x000>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -66,6 +67,7 @@
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x100>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -78,6 +80,7 @@
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x200>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -90,6 +93,7 @@
 			compatible = "arm,cortex-a55", "arm,armv8";
 			reg = <0x300>;
 			enable-method = "psci";
+			performance-domains = <&performance 0>;
 			clock-frequency = <1701000000>;
 			capacity-dmips-mhz = <578>;
 			cpu-idle-states = <&cpuoff_l &clusteroff_l>;
@@ -102,6 +106,7 @@
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x400>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -114,6 +119,7 @@
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x500>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -126,6 +132,7 @@
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x600>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -138,6 +145,7 @@
 			compatible = "arm,cortex-a78", "arm,armv8";
 			reg = <0x700>;
 			enable-method = "psci";
+			performance-domains = <&performance 1>;
 			clock-frequency = <2171000000>;
 			capacity-dmips-mhz = <1024>;
 			cpu-idle-states = <&cpuoff_b &clusteroff_b>;
@@ -257,6 +265,12 @@
 		method = "smc";
 	};
 
+	performance: performance-controller@11bc10 {
+		compatible = "mediatek,cpufreq-hw";
+		reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+		#performance-domain-cells = <1>;
+	};
+
 	timer: timer {
 		compatible = "arm,armv8-timer";
 		interrupt-parent = <&gic>;
-- 
2.18.0

Re: arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes

[Matthias Brugger]

Hi Tnghan,

It looks like as if you send a whole bunch of device tree files which don't have
any binding description yet.

Can you please filter and only send these patches that actually have a binding
entry? That would make my life much easier.

Apart from that it would be good if you could ask internally to get some advice
how to improve Signed-off-by tags (I spotted at least one patch where yours was
missing) or how to improve commit messages.

Thanks!
Matthias

On 15/06/2021 19:32, Tinghan Shen wrote:
> This series is a collection of device nodes for Mediatek SoC MT8195 and
> depends on patches[1][2][3].
> 
> The dependency list is not complete.
> some dependencies are still under working.
> 
> [1] arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
>     https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
> 
> [2] dt-bindings: power: Add MT8195 power domains
>     https://patchwork.kernel.org/project/linux-mediatek/patch/20210610023614.5375-3-chun-jie.chen@mediatek.com/
> 
> [3] dt-bindings: pinctrl: mt8195: add pinctrl file and binding document
>     https://patchwork.kernel.org/project/linux-mediatek/patch/20210413055702.27535-2-zhiyong.tao@mediatek.com/
> 
>