From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
Tomasz Figa <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<chao.hao@mediatek.com>
Subject: [PATCH 17/24] iommu/mediatek: Just move code position in hw_init
Date: Wed, 30 Jun 2021 10:34:57 +0800 [thread overview]
Message-ID: <20210630023504.18177-18-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210630023504.18177-1-yong.wu@mediatek.com>
No functional change too. mt8195 IOMMU support bank functions.
some global control etting is in bank0. and the other banks have its
bank independent setting. this patch only moves the control settings
and the independent registers together.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 48 +++++++++++++++++++--------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 1072a10e36ce..5237c837128e 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -743,30 +743,6 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(regval, data->base + REG_MMU_CTRL_REG);
- regval = F_L2_MULIT_HIT_EN |
- F_TABLE_WALK_FAULT_INT_EN |
- F_PREETCH_FIFO_OVERFLOW_INT_EN |
- F_MISS_FIFO_OVERFLOW_INT_EN |
- F_PREFETCH_FIFO_ERR_INT_EN |
- F_MISS_FIFO_ERR_INT_EN;
- writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
-
- regval = F_INT_TRANSLATION_FAULT |
- F_INT_MAIN_MULTI_HIT_FAULT |
- F_INT_INVALID_PA_FAULT |
- F_INT_ENTRY_REPLACEMENT_FAULT |
- F_INT_TLB_MISS_FAULT |
- F_INT_MISS_TRANSACTION_FIFO_FAULT |
- F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
- writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
-
- if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
- regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
- else
- regval = lower_32_bits(data->protect_base) |
- upper_32_bits(data->protect_base);
- writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
-
if (data->enable_4GB &&
MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_VLD_PA_RNG)) {
/*
@@ -800,6 +776,30 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
}
writel_relaxed(regval, data->base + REG_MMU_MISC_CTRL);
+ regval = F_L2_MULIT_HIT_EN |
+ F_TABLE_WALK_FAULT_INT_EN |
+ F_PREETCH_FIFO_OVERFLOW_INT_EN |
+ F_MISS_FIFO_OVERFLOW_INT_EN |
+ F_PREFETCH_FIFO_ERR_INT_EN |
+ F_MISS_FIFO_ERR_INT_EN;
+ writel_relaxed(regval, data->base + REG_MMU_INT_CONTROL0);
+
+ regval = F_INT_TRANSLATION_FAULT |
+ F_INT_MAIN_MULTI_HIT_FAULT |
+ F_INT_INVALID_PA_FAULT |
+ F_INT_ENTRY_REPLACEMENT_FAULT |
+ F_INT_TLB_MISS_FAULT |
+ F_INT_MISS_TRANSACTION_FIFO_FAULT |
+ F_INT_PRETETCH_TRANSATION_FIFO_FAULT;
+ writel_relaxed(regval, data->base + REG_MMU_INT_MAIN_CONTROL);
+
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_LEGACY_IVRP_PADDR))
+ regval = (data->protect_base >> 1) | (data->enable_4GB << 31);
+ else
+ regval = lower_32_bits(data->protect_base) |
+ upper_32_bits(data->protect_base);
+ writel_relaxed(regval, data->base + REG_MMU_IVRP_PADDR);
+
if (devm_request_irq(data->dev, data->irq, mtk_iommu_isr, 0,
dev_name(data->dev), (void *)data)) {
writel_relaxed(0, data->base + REG_MMU_PT_BASE_ADDR);
--
2.18.0
next prev parent reply other threads:[~2021-06-30 2:37 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-30 2:34 [PATCH 00/24] MT8195 IOMMU SUPPORT Yong Wu
2021-06-30 2:34 ` [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-06-30 6:26 ` Krzysztof Kozlowski
2021-06-30 7:30 ` Yong Wu
2021-07-14 21:11 ` Rob Herring
2021-06-30 2:34 ` [PATCH 02/24] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2021-06-30 6:27 ` Krzysztof Kozlowski
2021-07-14 21:14 ` Rob Herring
2021-06-30 2:34 ` [PATCH 03/24] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-06-30 2:34 ` [PATCH 04/24] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2021-06-30 2:34 ` [PATCH 05/24] iommu/mediatek: Add 12G~16G support for mult domain Yong Wu
2021-06-30 2:34 ` [PATCH 06/24] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-06-30 2:34 ` [PATCH 07/24] iommu/mediatek: Add flag NON_STD_AXI Yong Wu
2021-06-30 2:34 ` [PATCH 08/24] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-06-30 2:34 ` [PATCH 09/24] iommu/mediatek: Always pm_runtime_get while tlb flush Yong Wu
2021-06-30 2:34 ` [PATCH 10/24] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-06-30 2:34 ` [PATCH 11/24] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-06-30 2:34 ` [PATCH 12/24] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-06-30 2:34 ` [PATCH 13/24] iommu/mediatek: Add infra iommu support Yong Wu
2021-06-30 2:34 ` [PATCH 14/24] iommu/mediatek: Add PCIe support Yong Wu
2021-06-30 2:34 ` [PATCH 15/24] iommu/mediatek: Add mt8195 support Yong Wu
2021-06-30 2:34 ` [PATCH 16/24] iommu/mediatek: Only adjust code about register base Yong Wu
2021-06-30 2:34 ` Yong Wu [this message]
2021-06-30 2:34 ` [PATCH 18/24] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-06-30 2:34 ` [PATCH 19/24] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-06-30 2:35 ` [PATCH 20/24] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-06-30 2:35 ` [PATCH 21/24] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-06-30 2:35 ` [PATCH 22/24] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-06-30 2:35 ` [PATCH 23/24] iommu/mediatek: Add multi bank support Yong Wu
2021-06-30 2:35 ` [PATCH 24/24] iommu/mediatek: mt8195: Enable multi-bank for infra iommu Yong Wu
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