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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
	<chao.hao@mediatek.com>
Subject: [PATCH 02/24] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU
Date: Wed, 30 Jun 2021 10:34:42 +0800	[thread overview]
Message-ID: <20210630023504.18177-3-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210630023504.18177-1-yong.wu@mediatek.com>

In mt8195, we have a new IOMMU that is for INFRA IOMMU. its masters
mainly are PCIe and USB. Different with MM IOMMU, all these masters
connect with IOMMU directly, there is no mediatek,larbs property for
infra IOMMU.

Another thing is about PCIe ports. currently the function
"of_iommu_configure_dev_id" only support the id number is 1, But our
PCIe have two ports, one is for reading and the other is for writing.
see more about the PCIe patch in this patchset. Thus, I only list
the reading id here and add the other id in our driver.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 .../bindings/iommu/mediatek,iommu.yaml         | 14 +++++++++++++-
 .../dt-bindings/memory/mt8195-memory-port.h    | 18 ++++++++++++++++++
 include/dt-bindings/memory/mtk-memory-port.h   |  2 ++
 3 files changed, 33 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index 9b04630158c8..6f3ff631c06b 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -79,6 +79,7 @@ properties:
           - mediatek,mt8192-m4u  # generation two
           - mediatek,mt8195-iommu-vdo        # generation two
           - mediatek,mt8195-iommu-vpp        # generation two
+          - mediatek,mt8195-iommu-infra      # generation two
 
       - description: mt7623 generation one
         items:
@@ -129,7 +130,6 @@ required:
   - compatible
   - reg
   - interrupts
-  - mediatek,larbs
   - '#iommu-cells'
 
 allOf:
@@ -161,6 +161,18 @@ allOf:
       required:
         - power-domains
 
+  - if:
+      not:
+        properties:
+          compatible:
+            items:
+              enum:
+                - mediatek,mt8195-iommu-infra
+
+    then:
+      required:
+        - mediatek,larbs
+
 additionalProperties: false
 
 examples:
diff --git a/include/dt-bindings/memory/mt8195-memory-port.h b/include/dt-bindings/memory/mt8195-memory-port.h
index 783bcae8cdea..67afad848725 100644
--- a/include/dt-bindings/memory/mt8195-memory-port.h
+++ b/include/dt-bindings/memory/mt8195-memory-port.h
@@ -387,4 +387,22 @@
 #define M4U_PORT_L28_CAM_DRZS4NO_R1		MTK_M4U_ID(28, 5)
 #define M4U_PORT_L28_CAM_TNCSO_R1		MTK_M4U_ID(28, 6)
 
+/* infra iommu ports */
+/* PCIe1: read: BIT16; write BIT17. */
+#define M4U_PORT_INFRA_PCIE1			MTK_IFAIOMMU_PERI_ID(16)
+/* PCIe0: read: BIT18; write BIT19. */
+#define M4U_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
+#define M4U_PORT_INFRA_SSUSB_P3_R		MTK_IFAIOMMU_PERI_ID(20)
+#define M4U_PORT_INFRA_SSUSB_P3_W		MTK_IFAIOMMU_PERI_ID(21)
+#define M4U_PORT_INFRA_SSUSB_P2_R		MTK_IFAIOMMU_PERI_ID(22)
+#define M4U_PORT_INFRA_SSUSB_P2_W		MTK_IFAIOMMU_PERI_ID(23)
+#define M4U_PORT_INFRA_SSUSB_P1_1_R		MTK_IFAIOMMU_PERI_ID(24)
+#define M4U_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)
+#define M4U_PORT_INFRA_SSUSB_P1_0_R		MTK_IFAIOMMU_PERI_ID(26)
+#define M4U_PORT_INFRA_SSUSB_P1_0_W		MTK_IFAIOMMU_PERI_ID(27)
+#define M4U_PORT_INFRA_SSUSB2_R			MTK_IFAIOMMU_PERI_ID(28)
+#define M4U_PORT_INFRA_SSUSB2_W			MTK_IFAIOMMU_PERI_ID(29)
+#define M4U_PORT_INFRA_SSUSB_R			MTK_IFAIOMMU_PERI_ID(30)
+#define M4U_PORT_INFRA_SSUSB_W			MTK_IFAIOMMU_PERI_ID(31)
+
 #endif
diff --git a/include/dt-bindings/memory/mtk-memory-port.h b/include/dt-bindings/memory/mtk-memory-port.h
index 7d64103209af..2f68a0511a25 100644
--- a/include/dt-bindings/memory/mtk-memory-port.h
+++ b/include/dt-bindings/memory/mtk-memory-port.h
@@ -12,4 +12,6 @@
 #define MTK_M4U_TO_LARB(id)		(((id) >> 5) & 0x1f)
 #define MTK_M4U_TO_PORT(id)		((id) & 0x1f)
 
+#define MTK_IFAIOMMU_PERI_ID(port)	MTK_M4U_ID(0, port)
+
 #endif
-- 
2.18.0


  parent reply	other threads:[~2021-06-30  2:35 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-30  2:34 [PATCH 00/24] MT8195 IOMMU SUPPORT Yong Wu
2021-06-30  2:34 ` [PATCH 01/24] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-06-30  6:26   ` Krzysztof Kozlowski
2021-06-30  7:30     ` Yong Wu
2021-07-14 21:11   ` Rob Herring
2021-06-30  2:34 ` Yong Wu [this message]
2021-06-30  6:27   ` [PATCH 02/24] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Krzysztof Kozlowski
2021-07-14 21:14   ` Rob Herring
2021-06-30  2:34 ` [PATCH 03/24] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-06-30  2:34 ` [PATCH 04/24] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2021-06-30  2:34 ` [PATCH 05/24] iommu/mediatek: Add 12G~16G support for mult domain Yong Wu
2021-06-30  2:34 ` [PATCH 06/24] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-06-30  2:34 ` [PATCH 07/24] iommu/mediatek: Add flag NON_STD_AXI Yong Wu
2021-06-30  2:34 ` [PATCH 08/24] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-06-30  2:34 ` [PATCH 09/24] iommu/mediatek: Always pm_runtime_get while tlb flush Yong Wu
2021-06-30  2:34 ` [PATCH 10/24] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-06-30  2:34 ` [PATCH 11/24] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-06-30  2:34 ` [PATCH 12/24] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-06-30  2:34 ` [PATCH 13/24] iommu/mediatek: Add infra iommu support Yong Wu
2021-06-30  2:34 ` [PATCH 14/24] iommu/mediatek: Add PCIe support Yong Wu
2021-06-30  2:34 ` [PATCH 15/24] iommu/mediatek: Add mt8195 support Yong Wu
2021-06-30  2:34 ` [PATCH 16/24] iommu/mediatek: Only adjust code about register base Yong Wu
2021-06-30  2:34 ` [PATCH 17/24] iommu/mediatek: Just move code position in hw_init Yong Wu
2021-06-30  2:34 ` [PATCH 18/24] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-06-30  2:34 ` [PATCH 19/24] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-06-30  2:35 ` [PATCH 20/24] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-06-30  2:35 ` [PATCH 21/24] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-06-30  2:35 ` [PATCH 22/24] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-06-30  2:35 ` [PATCH 23/24] iommu/mediatek: Add multi bank support Yong Wu
2021-06-30  2:35 ` [PATCH 24/24] iommu/mediatek: mt8195: Enable multi-bank for infra iommu Yong Wu

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