* [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-24 16:46 ` Rob Herring
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
` (15 subsequent siblings)
16 siblings, 1 reply; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Rob Herring, Mark Brown,
Srinivas Kandagatla, Jonathan Cameron, Guenter Roeck, Vinod Koul,
Hector Martin, Sudeep Holla, Lorenzo Pieralisi, devicetree,
linux-kernel
Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350).
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 9a2432a88074..897eec887e5a 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -171,6 +171,7 @@ properties:
- qcom,kryo385
- qcom,kryo468
- qcom,kryo485
+ - qcom,kryo560
- qcom,kryo685
- qcom,scorpion
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
2021-08-20 20:49 ` [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-21 14:55 ` Konrad Dybcio
2021-09-14 16:08 ` Bjorn Andersson
2021-08-20 20:49 ` [PATCH 03/17] arm64: dts: qcom: sm6350: Add LLCC node Konrad Dybcio
` (14 subsequent siblings)
16 siblings, 2 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck,
linux-arm-msm, devicetree, linux-kernel
Add a base DT for SM6350 SoC
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 486 +++++++++++++++++++++++++++
1 file changed, 486 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm6350.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
new file mode 100644
index 000000000000..0526bc141a6d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -0,0 +1,486 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/soc/qcom,rpmh-rsc.h>
+
+/ {
+ interrupt-parent = <&intc>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks {
+ xo_board: xo-board {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <38400000>;
+ clock-output-names = "xo_board";
+ };
+
+ sleep_clk: sleep-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_0>;
+ #cooling-cells = <2>;
+ L2_0: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ L3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+ };
+
+ CPU1: cpu@100 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_100>;
+ #cooling-cells = <2>;
+ L2_100: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU2: cpu@200 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x200>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_200>;
+ #cooling-cells = <2>;
+ L2_200: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU3: cpu@300 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x300>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_300>;
+ #cooling-cells = <2>;
+ L2_300: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU4: cpu@400 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_400>;
+ #cooling-cells = <2>;
+ L2_400: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU5: cpu@500 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1024>;
+ dynamic-power-coefficient = <100>;
+ next-level-cache = <&L2_500>;
+ #cooling-cells = <2>;
+ L2_500: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+
+ };
+
+ CPU6: cpu@600 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ next-level-cache = <&L2_600>;
+ #cooling-cells = <2>;
+ L2_600: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ CPU7: cpu@700 {
+ device_type = "cpu";
+ compatible = "qcom,kryo560";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ capacity-dmips-mhz = <1894>;
+ dynamic-power-coefficient = <703>;
+ next-level-cache = <&L2_700>;
+ #cooling-cells = <2>;
+ L2_700: l2-cache {
+ compatible = "cache";
+ next-level-cache = <&L3_0>;
+ };
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&CPU0>;
+ };
+
+ core1 {
+ cpu = <&CPU1>;
+ };
+
+ core2 {
+ cpu = <&CPU2>;
+ };
+
+ core3 {
+ cpu = <&CPU3>;
+ };
+
+ core4 {
+ cpu = <&CPU4>;
+ };
+
+ core5 {
+ cpu = <&CPU5>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&CPU6>;
+ };
+
+ core1 {
+ cpu = <&CPU7>;
+ };
+ };
+ };
+ };
+
+ firmware {
+ scm: scm {
+ compatible = "qcom,scm-sm6350", "qcom,scm";
+ #reset-cells = <1>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the size */
+ reg = <0x0 0x80000000 0x0 0x0>;
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ reserved_memory: reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ hyp_mem: memory@80000000 {
+ reg = <0 0x80000000 0 0x600000>;
+ no-map;
+ };
+
+ xbl_aop_mem: memory@80700000 {
+ reg = <0 0x80700000 0 0x160000>;
+ no-map;
+ };
+
+ cmd_db: memory@80860000 {
+ compatible = "qcom,cmd-db";
+ reg = <0 0x80860000 0 0x20000>;
+ no-map;
+ };
+
+ sec_apps_mem: memory@808ff000 {
+ reg = <0 0x808ff000 0 0x1000>;
+ no-map;
+ };
+
+ smem_mem: memory@80900000 {
+ reg = <0 0x80900000 0 0x200000>;
+ no-map;
+ };
+
+ cdsp_sec_mem: memory@80b00000 {
+ reg = <0 0x80b00000 0 0x1e00000>;
+ no-map;
+ };
+
+ pil_camera_mem: memory@86000000 {
+ reg = <0 0x86000000 0 0x500000>;
+ no-map;
+ };
+
+ pil_npu_mem: memory@86500000 {
+ reg = <0 0x86500000 0 0x500000>;
+ no-map;
+ };
+
+ pil_video_mem: memory@86a00000 {
+ reg = <0 0x86a00000 0 0x500000>;
+ no-map;
+ };
+
+ pil_cdsp_mem: memory@86f00000 {
+ reg = <0 0x86f00000 0 0x1e00000>;
+ no-map;
+ };
+
+ pil_adsp_mem: memory@88d00000 {
+ reg = <0 0x88d00000 0 0x2800000>;
+ no-map;
+ };
+
+ wlan_fw_mem: memory@8b500000 {
+ reg = <0 0x8b500000 0 0x200000>;
+ no-map;
+ };
+
+ pil_ipa_fw_mem: memory@8b700000 {
+ reg = <0 0x8b700000 0 0x10000>;
+ no-map;
+ };
+
+ pil_ipa_gsi_mem: memory@8b710000 {
+ reg = <0 0x8b710000 0 0x5400>;
+ no-map;
+ };
+
+ pil_gpu_mem: memory@8b715400 {
+ reg = <0 0x8b715400 0 0x2000>;
+ no-map;
+ };
+
+ pil_modem_mem: memory@8b800000 {
+ reg = <0 0x8b800000 0 0xf800000>;
+ no-map;
+ };
+
+ cont_splash_memory: memory@a0000000 {
+ reg = <0 0xa0000000 0 0x2300000>;
+ no-map;
+ };
+
+ dfps_data_memory: memory@a2300000 {
+ reg = <0 0xa2300000 0 0x100000>;
+ no-map;
+ };
+
+ removed_region: memory@c0000000 {
+ reg = <0 0xc0000000 0 0x3900000>;
+ no-map;
+ };
+
+ debug_region: memory@ffb00000 {
+ reg = <0 0xffb00000 0 0xc0000>;
+ no-map;
+ };
+
+ last_log_region: memory@ffbc0000 {
+ reg = <0 0xffbc0000 0 0x40000>;
+ no-map;
+ };
+
+ ramoops: ramoops@ffc00000 {
+ compatible = "removed-dma-pool", "ramoops";
+ reg = <0 0xffc00000 0 0x00100000>;
+ record-size = <0x1000>;
+ console-size = <0x40000>;
+ ftrace-size = <0x0>;
+ msg-size = <0x20000 0x20000>;
+ cc-size = <0x0>;
+ no-map;
+ };
+
+ cmdline_region: memory@ffd00000 {
+ reg = <0 0xffd00000 0 0x1000>;
+ no-map;
+ };
+ };
+
+ smem {
+ compatible = "qcom,smem";
+ memory-region = <&smem_mem>;
+ hwlocks = <&tcsr_mutex 3>;
+ };
+
+ soc: soc@0 {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0 0x10 0>;
+ dma-ranges = <0 0 0 0 0x10 0>;
+ compatible = "simple-bus";
+
+ ipcc: mailbox@408000 {
+ compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #mbox-cells = <2>;
+ };
+
+ tcsr_mutex: hwlock@1f40000 {
+ compatible = "qcom,tcsr-mutex";
+ reg = <0x0 0x01f40000 0x0 0x40000>;
+ #hwlock-cells = <1>;
+ };
+
+ pdc: interrupt-controller@b220000 {
+ compatible = "qcom,sm6350-pdc", "qcom,pdc";
+ reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
+ qcom,pdc-ranges = <0 480 94>, <94 609 31>,
+ <125 63 1>, <126 655 12>, <138 139 15>;
+ #interrupt-cells = <2>;
+ interrupt-parent = <&intc>;
+ interrupt-controller;
+ };
+
+ intc: interrupt-controller@17a00000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */
+ <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */
+ interrupts = <GIC_PPI 8 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ watchdog@17c10000 {
+ compatible = "qcom,apss-wdt-sm6350", "qcom,kpss-wdt";
+ reg = <0 0x17c10000 0 0x1000>;
+ clocks = <&sleep_clk>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer@17c20000 {
+ compatible = "arm,armv7-timer-mem";
+ reg = <0x0 0x17c20000 0x0 0x1000>;
+ clock-frequency = <19200000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ frame@17c21000 {
+ frame-number = <0>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c21000 0x0 0x1000>,
+ <0x0 0x17c22000 0x0 0x1000>;
+ };
+
+ frame@17c23000 {
+ frame-number = <1>;
+ interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c23000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c25000 {
+ frame-number = <2>;
+ interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c25000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c27000 {
+ frame-number = <3>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c27000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c29000 {
+ frame-number = <4>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c29000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2b000 {
+ frame-number = <5>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c2b000 0x0 0x1000>;
+ status = "disabled";
+ };
+
+ frame@17c2d000 {
+ frame-number = <6>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x0 0x17c2d000 0x0 0x1000>;
+ status = "disabled";
+ };
+ };
+
+ apps_rsc: rsc@18200000 {
+ compatible = "qcom,rpmh-rsc";
+ label = "apps_rsc";
+ reg = <0x0 0x18200000 0x0 0x10000>,
+ <0x0 0x18210000 0x0 0x10000>,
+ <0x0 0x18220000 0x0 0x10000>;
+ reg-names = "drv-0", "drv-1", "drv-2";
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,tcs-offset = <0xd00>;
+ qcom,drv-id = <2>;
+ qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
+ <WAKE_TCS 3>, <CONTROL_TCS 1>;
+ };
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ clock-frequency = <19200000>;
+ interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 03/17] arm64: dts: qcom: sm6350: Add LLCC node
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
2021-08-20 20:49 ` [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs Konrad Dybcio
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 04/17] arm64: dts: qcom: sm6350: Add RPMHCC node Konrad Dybcio
` (13 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add a node for LLCC with SM6350-specific compatible.
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 0526bc141a6d..6cfc2201d975 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -373,6 +373,12 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ system-cache-controller@9200000 {
+ compatible = "qcom,sm6350-llcc";
+ reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
+ reg-names = "llcc_base", "llcc_broadcast_base";
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 04/17] arm64: dts: qcom: sm6350: Add RPMHCC node
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (2 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 03/17] arm64: dts: qcom: sm6350: Add LLCC node Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 05/17] arm64: dts: qcom: sm6350: Add GCC node Konrad Dybcio
` (12 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add RPMHCC node to allow for referencing RPMH-controlled clocks in other
nodes.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 6cfc2201d975..596d3a64917c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -478,6 +478,13 @@ apps_rsc: rsc@18200000 {
qcom,drv-id = <2>;
qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 3>,
<WAKE_TCS 3>, <CONTROL_TCS 1>;
+
+ rpmhcc: clock-controller {
+ compatible = "qcom,sm6350-rpmh-clk";
+ #clock-cells = <1>;
+ clock-names = "xo";
+ clocks = <&xo_board>;
+ };
};
};
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 05/17] arm64: dts: qcom: sm6350: Add GCC node
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (3 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 04/17] arm64: dts: qcom: sm6350: Add RPMHCC node Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 06/17] arm64: dts: qcom: sm6350: Add TLMM block node Konrad Dybcio
` (11 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add and configure GCC node to allow for referencing GCC-controlled clocks
in other nodes.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 596d3a64917c..83c46f237f28 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -3,6 +3,8 @@
* Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
*/
+#include <dt-bindings/clock/qcom,gcc-sm6350.h>
+#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -358,6 +360,20 @@ soc: soc@0 {
dma-ranges = <0 0 0 0 0x10 0>;
compatible = "simple-bus";
+ gcc: clock-controller@100000 {
+ compatible = "qcom,gcc-sm6350";
+ reg = <0 0x00100000 0 0x1f0000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ clock-names = "bi_tcxo",
+ "bi_tcxo_ao",
+ "sleep_clk";
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ };
+
ipcc: mailbox@408000 {
compatible = "qcom,sm6350-ipcc", "qcom,ipcc";
reg = <0 0x00408000 0 0x1000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 06/17] arm64: dts: qcom: sm6350: Add TLMM block node
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (4 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 05/17] arm64: dts: qcom: sm6350: Add GCC node Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 07/17] arm64: dts: qcom: sm6350: Add USB1 nodes Konrad Dybcio
` (10 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add TLMM pinctrl node to enable referencing the SoC pins in other nodes.
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 83c46f237f28..889dd07d3371 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -405,6 +405,25 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tlmm: pinctrl@f100000 {
+ compatible = "qcom,sm6350-tlmm";
+ reg = <0 0x0f100000 0 0x300000>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ gpio-ranges = <&tlmm 0 0 156>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 07/17] arm64: dts: qcom: sm6350: Add USB1 nodes
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (5 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 06/17] arm64: dts: qcom: sm6350: Add TLMM block node Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support Konrad Dybcio
` (9 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add nodes required for USB1 to function. SM6350 (thankfully) resuses SDM845 and
SC7180 IP, so no additional code porting is required.
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 101 +++++++++++++++++++++++++++
1 file changed, 101 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 889dd07d3371..e70b1f09a488 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -389,12 +389,113 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ usb_1_hsphy: phy@88e3000 {
+ compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
+ reg = <0 0x088e3000 0 0x400>;
+ status = "disabled";
+ #phy-cells = <0>;
+
+ clocks = <&xo_board>, <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "cfg_ahb", "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+ };
+
+ usb_1_qmpphy: phy@88e9000 {
+ compatible = "qcom,sc7180-qmp-usb3-dp-phy";
+ reg = <0 0x088e9000 0 0x200>,
+ <0 0x088e8000 0 0x40>,
+ <0 0x088ea000 0 0x200>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_QLINK_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&xo_board>;
+ clock-names = "aux", "ref", "com_aux", "cfg_ahb";
+
+ resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ usb_1_ssphy: usb3-phy@88e9200 {
+ reg = <0 0x088e9200 0 0x200>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x400>,
+ <0 0x088e9600 0 0x200>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+
+ dp_phy: dp-phy@88ea200 {
+ reg = <0 0x088ea200 0 0x200>,
+ <0 0x088ea400 0 0x200>,
+ <0 0x088eac00 0 0x400>,
+ <0 0x088ea600 0 0x200>,
+ <0 0x088ea800 0 0x200>,
+ <0 0x088eaa00 0 0x100>;
+ #phy-cells = <0>;
+ #clock-cells = <1>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
+
system-cache-controller@9200000 {
compatible = "qcom,sm6350-llcc";
reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
reg-names = "llcc_base", "llcc_broadcast_base";
};
+ usb_1: usb@a6f8800 {
+ compatible = "qcom,sm6350-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+ status = "disabled";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+ clock-names = "cfg_noc", "core", "iface", "mock_utmi",
+ "sleep";
+
+ interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 14 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hs_phy_irq", "dp_hs_phy_irq",
+ "dm_hs_phy_irq", "ss_phy_irq";
+
+ power-domains = <&gcc USB30_PRIM_GDSC>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ usb_1_dwc3: dwc3@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,has-lpm-erratum;
+ snps,hird-threshold = /bits/ 8 <0x10>;
+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,sm6350-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x17c000f0 0 0x64>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (6 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 07/17] arm64: dts: qcom: sm6350: Add USB1 nodes Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 09/17] arm64: dts: qcom: sm6350: Add TSENS nodes Konrad Dybcio
` (8 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add cpufreq-hw node and assign qcom,freq-domain properties to CPUs to enable
CPU clock scaling.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index e70b1f09a488..f7965d5fb341 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -41,6 +41,7 @@ CPU0: cpu@0 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -59,6 +60,7 @@ CPU1: cpu@100 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -74,6 +76,7 @@ CPU2: cpu@200 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -89,6 +92,7 @@ CPU3: cpu@300 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -104,6 +108,7 @@ CPU4: cpu@400 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -119,6 +124,7 @@ CPU5: cpu@500 {
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -135,6 +141,7 @@ CPU6: cpu@600 {
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -150,6 +157,7 @@ CPU7: cpu@700 {
capacity-dmips-mhz = <1894>;
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
@@ -622,6 +630,16 @@ rpmhcc: clock-controller {
clocks = <&xo_board>;
};
};
+
+ cpufreq_hw: cpufreq@18323000 {
+ compatible = "qcom,cpufreq-hw";
+ reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ };
};
timer {
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 09/17] arm64: dts: qcom: sm6350: Add TSENS nodes
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (7 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 10/17] arm64: dts: qcom: sm6350: Add AOSS_QMP Konrad Dybcio
` (7 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add nodes required for TSENS block using the common qcom,tsens-v2 binding.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index f7965d5fb341..097fb74eebea 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -514,6 +514,28 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ tsens0: thermal-sensor@c263000 {
+ compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c263000 0 0x1ff>, /* TM */
+ <0 0x0c222000 0 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 28 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
+ tsens1: thermal-sensor@c265000 {
+ compatible = "qcom,sm6350-tsens", "qcom,tsens-v2";
+ reg = <0 0x0c265000 0 0x1ff>, /* TM */
+ <0 0x0c223000 0 0x8>; /* SROT */
+ #qcom,sensors = <16>;
+ interrupts = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 29 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "uplow", "critical";
+ #thermal-sensor-cells = <1>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 10/17] arm64: dts: qcom: sm6350: Add AOSS_QMP
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (8 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 09/17] arm64: dts: qcom: sm6350: Add TSENS nodes Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 11/17] arm64: dts: qcom: sm6350: Add SPMI bus Konrad Dybcio
` (6 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add a node for AOSS_QMP in preparation for remote processor enablement.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 097fb74eebea..96767c4b1879 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -536,6 +536,17 @@ tsens1: thermal-sensor@c265000 {
#thermal-sensor-cells = <1>;
};
+ aoss_qmp: power-controller@c300000 {
+ compatible = "qcom,sm6350-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x1000>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ #power-domain-cells = <1>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 11/17] arm64: dts: qcom: sm6350: Add SPMI bus
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (9 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 10/17] arm64: dts: qcom: sm6350: Add AOSS_QMP Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 12/17] arm64: dts: qcom: sm6350: Add PRNG node Konrad Dybcio
` (5 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add a node for SPMI to allow for communication with on-board PMICs.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 96767c4b1879..6ee535f9e203 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -547,6 +547,24 @@ aoss_qmp: power-controller@c300000 {
#power-domain-cells = <1>;
};
+ spmi_bus: spmi@c440000 {
+ compatible = "qcom,spmi-pmic-arb";
+ reg = <0 0xc440000 0 0x1100>,
+ <0 0xc600000 0 0x2000000>,
+ <0 0xe600000 0 0x100000>,
+ <0 0xe700000 0 0xa0000>,
+ <0 0xc40a000 0 0x26000>;
+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
+ interrupt-names = "periph_irq";
+ interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,ee = <0>;
+ qcom,channel = <0>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ interrupt-controller;
+ #interrupt-cells = <4>;
+ };
+
tlmm: pinctrl@f100000 {
compatible = "qcom,sm6350-tlmm";
reg = <0 0x0f100000 0 0x300000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 12/17] arm64: dts: qcom: sm6350: Add PRNG node
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (10 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 11/17] arm64: dts: qcom: sm6350: Add SPMI bus Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 13/17] arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Konrad Dybcio
` (4 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add a node for the PRNG to enable hw-accelerated pseudo-random number
generation.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 6ee535f9e203..4aed8a50ebe0 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -391,6 +391,13 @@ ipcc: mailbox@408000 {
#mbox-cells = <2>;
};
+ rng: rng@793000 {
+ compatible = "qcom,prng-ee";
+ reg = <0 0x00793000 0 0x1000>;
+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
+ clock-names = "core";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 13/17] arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (11 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 12/17] arm64: dts: qcom: sm6350: Add PRNG node Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 14/17] arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes Konrad Dybcio
` (3 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add RPMHPD node, its OPP table and BCM voter to prepare for performance level
voting.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 ++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 4aed8a50ebe0..9ca14fa8324a 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -687,6 +687,60 @@ rpmhcc: clock-controller {
clock-names = "xo";
clocks = <&xo_board>;
};
+
+ rpmhpd: power-controller {
+ compatible = "qcom,sm6350-rpmhpd";
+ #power-domain-cells = <1>;
+ operating-points-v2 = <&rpmhpd_opp_table>;
+
+ rpmhpd_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ rpmhpd_opp_ret: opp1 {
+ opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+ };
+
+ rpmhpd_opp_min_svs: opp2 {
+ opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+ };
+
+ rpmhpd_opp_low_svs: opp3 {
+ opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+ };
+
+ rpmhpd_opp_svs: opp4 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+ };
+
+ rpmhpd_opp_svs_l1: opp5 {
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ };
+
+ rpmhpd_opp_nom: opp6 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+ };
+
+ rpmhpd_opp_nom_l1: opp7 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+ };
+
+ rpmhpd_opp_nom_l2: opp8 {
+ opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+ };
+
+ rpmhpd_opp_turbo: opp9 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+ };
+
+ rpmhpd_opp_turbo_l1: opp10 {
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ };
+ };
+ };
+
+ apps_bcm_voter: bcm_voter {
+ compatible = "qcom,bcm-voter";
+ };
};
cpufreq_hw: cpufreq@18323000 {
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 14/17] arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (12 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 13/17] arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 15/17] arm64: dts: qcom: sm6350: Add apps_smmu Konrad Dybcio
` (2 subsequent siblings)
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add SDHCI1/2 nodes for eMMC and uSD card respectively.
Do note that most SM6350 devices seem to come with UFS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 81 ++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 9ca14fa8324a..df99d6207f1c 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
/ {
@@ -398,12 +399,92 @@ rng: rng@793000 {
clock-names = "core";
};
+ sdhc_1: sdhci@7c4000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x007c4000 0 0x1000>,
+ <0 0x007c5000 0 0x1000>,
+ <0 0x007c8000 0 0x8000>;
+ reg-names = "hc", "cqhci", "ice";
+
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC1_AHB_CLK>,
+ <&gcc GCC_SDCC1_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x000f642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&sdhc1_opp_table>;
+ bus-width = <8>;
+ non-removable;
+ supports-cqe;
+
+ status = "disabled";
+
+ sdhc1_opp_table: sdhc1-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_min_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+ };
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0x0 0x01f40000 0x0 0x40000>;
#hwlock-cells = <1>;
};
+ sdhc_2: sdhci@8804000 {
+ compatible = "qcom,sm6350-sdhci", "qcom,sdhci-msm-v5";
+ reg = <0 0x08804000 0 0x1000>;
+
+ interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hc_irq", "pwr_irq";
+
+ clocks = <&gcc GCC_SDCC2_AHB_CLK>,
+ <&gcc GCC_SDCC2_APPS_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "core", "xo";
+ qcom,dll-config = <0x0007642c>;
+ qcom,ddr-config = <0x80040868>;
+ power-domains = <&rpmhpd SM6350_CX>;
+ operating-points-v2 = <&sdhc2_opp_table>;
+ bus-width = <4>;
+
+ status = "disabled";
+
+ sdhc2_opp_table: sdhc2-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-202000000 {
+ opp-hz = /bits/ 64 <202000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
usb_1_hsphy: phy@88e3000 {
compatible = "qcom,sm6350-qusb2-phy", "qcom,qusb2-v2-phy";
reg = <0 0x088e3000 0 0x400>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 15/17] arm64: dts: qcom: sm6350: Add apps_smmu
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (13 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 14/17] arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 16/17] arm64: dts: qcom: sm6350: Add iommus property to USB1 Konrad Dybcio
2021-08-20 20:49 ` [PATCH 17/17] arm64: dts: qcom: Add device tree for Sony Xperia 10 III Konrad Dybcio
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add a node for the APPS SMMU to allow for managing memory access to peripherals
such as the USB controller.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 88 ++++++++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index df99d6207f1c..a81e875af503 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -672,6 +672,94 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 156>;
};
+ apps_smmu: iommu@15000000 {
+ compatible = "qcom,sm6350-smmu-500", "arm,mmu-500";
+ reg = <0 0x15000000 0 0x100000>;
+ #iommu-cells = <2>;
+ #global-interrupts = <1>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 16/17] arm64: dts: qcom: sm6350: Add iommus property to USB1
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (14 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 15/17] arm64: dts: qcom: sm6350: Add apps_smmu Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
2021-08-20 20:49 ` [PATCH 17/17] arm64: dts: qcom: Add device tree for Sony Xperia 10 III Konrad Dybcio
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
This is required for us to be able to access the associated registers, which
are (on at least some devices) gated by default.
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index a81e875af503..8bf9175dd09a 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -583,6 +583,7 @@ usb_1_dwc3: dwc3@a600000 {
compatible = "snps,dwc3";
reg = <0 0x0a600000 0 0xcd00>;
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x540 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
snps,has-lpm-erratum;
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 17/17] arm64: dts: qcom: Add device tree for Sony Xperia 10 III
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
` (15 preceding siblings ...)
2021-08-20 20:49 ` [PATCH 16/17] arm64: dts: qcom: sm6350: Add iommus property to USB1 Konrad Dybcio
@ 2021-08-20 20:49 ` Konrad Dybcio
16 siblings, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-20 20:49 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Konrad Dybcio, Andy Gross, Bjorn Andersson,
Rob Herring, linux-arm-msm, devicetree, linux-kernel
Add initial SM6350 SoC and Sony Xperia 10 III (PDX213, Lena platform) device
trees. There is no sign of another Lena devices on the horizon, so a common
DTSI is not created for now. 10 III features a Full HD OLED display and 5G
support, among other nice things like USB3.
The bootloader is VERY unpleasant, to get a bootable setup you have to run:
mkbootimg --kernel arch/arm64/boot/Image.gz --ramdisk [some initrd] \
--dtb arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dtb \
--cmdline "[some cmdline]" --base 0 --kernel_offset 0x8000 \
--ramdisk_offset 0x1000000 --dtb_offset 0x1f00000 --os_version 11 \
--os_patch_level "2021-08" --tags_offset 0x100 --pagesize 4096 \
--header_version 2 -o mainline.img
adb reboot bootloader
// You have to either pull vbmeta{"","_system"} from
// /dev/block/bootdevice/by-name/ or build one as a part of AOSP build process
fastboot --disable-verity --disable-verification flash vbmeta vbmeta.img
fastboot --disable-verity --disable-verification flash vbmeta_system \
vbmeta_system.img
fastboot flash boot mainline.img
fastboot erase dtbo // This will take approx 70s...
fastboot reboot
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
---
arch/arm64/boot/dts/qcom/Makefile | 1 +
.../qcom/sm6350-sony-xperia-lena-pdx213.dts | 57 +++++++++++++++++++
2 files changed, 58 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
index 5bbeb058e1f2..d1ace2541ce1 100644
--- a/arch/arm64/boot/dts/qcom/Makefile
+++ b/arch/arm64/boot/dts/qcom/Makefile
@@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-akatsuki.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-sony-xperia-tama-apollo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-xiaomi-beryllium.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm850-lenovo-yoga-c630.dtb
+dtb-$(CONFIG_ARCH_QCOM) += sm6350-sony-xperia-lena-pdx213.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-hdk.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-microsoft-surface-duo.dtb
dtb-$(CONFIG_ARCH_QCOM) += sm8150-mtp.dtb
diff --git a/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
new file mode 100644
index 000000000000..a26c23754f5d
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm6350-sony-xperia-lena-pdx213.dts
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
+ */
+/dts-v1/;
+
+#include "sm6350.dtsi"
+
+/ {
+ model = "Sony Xperia 10 III";
+ compatible = "sony,pdx213", "qcom,sm6350";
+ qcom,msm-id = <434 0x10000>, <459 0x10000>;
+ qcom,board-id = <0x1000B 0>;
+
+ chosen {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ framebuffer: framebuffer@a0000000 {
+ compatible = "simple-framebuffer";
+ reg = <0 0xa0000000 0 0x2300000>;
+ width = <1080>;
+ height = <2520>;
+ stride = <(1080 * 4)>;
+ format = "a8r8g8b8";
+ clocks = <&gcc GCC_DISP_AXI_CLK>;
+ };
+ };
+};
+
+&sdhc_2 {
+ status = "okay";
+
+ cd-gpios = <&tlmm 94 GPIO_ACTIVE_HIGH>;
+};
+
+&tlmm {
+ gpio-reserved-ranges = <13 4>, <45 2>, <56 2>;
+};
+
+&usb_1 {
+ status = "okay";
+};
+
+&usb_1_dwc3 {
+ maximum-speed = "super-speed";
+ dr_mode = "peripheral";
+};
+
+&usb_1_hsphy {
+ status = "okay";
+};
+
+&usb_1_qmpphy {
+ status = "okay";
+};
--
2.33.0
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
@ 2021-08-21 14:55 ` Konrad Dybcio
2021-09-14 16:08 ` Bjorn Andersson
1 sibling, 0 replies; 20+ messages in thread
From: Konrad Dybcio @ 2021-08-21 14:55 UTC (permalink / raw)
To: ~postmarketos/upstreaming
Cc: martin.botka, angelogioacchino.delregno, marijn.suijten,
jamipkettunen, Andy Gross, Bjorn Andersson, Rob Herring,
Kees Cook, Anton Vorontsov, Colin Cross, Tony Luck,
linux-arm-msm, devicetree, linux-kernel
On 20.08.2021 22:49, Konrad Dybcio wrote:
> Add a base DT for SM6350 SoC
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 486 +++++++++++++++++++++++++++
> 1 file changed, 486 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm6350.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> new file mode 100644
> index 000000000000..0526bc141a6d
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -0,0 +1,486 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org>
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
Small mistake, `#include <dt-bindings/gpio/gpio.h>` got sucked up into the rebase void..
Konrad
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs
2021-08-20 20:49 ` [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs Konrad Dybcio
@ 2021-08-24 16:46 ` Rob Herring
0 siblings, 0 replies; 20+ messages in thread
From: Rob Herring @ 2021-08-24 16:46 UTC (permalink / raw)
To: Konrad Dybcio
Cc: martin.botka, Mark Brown, jamipkettunen, Jonathan Cameron,
~postmarketos/upstreaming, Lorenzo Pieralisi, devicetree,
marijn.suijten, Sudeep Holla, Hector Martin,
angelogioacchino.delregno, Rob Herring, Vinod Koul,
Guenter Roeck, linux-kernel, Srinivas Kandagatla
On Fri, 20 Aug 2021 22:49:10 +0200, Konrad Dybcio wrote:
> Document Kryo 560 CPUs found in Qualcomm Snapdragon 690 (SM6350).
>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> Documentation/devicetree/bindings/arm/cpus.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
2021-08-21 14:55 ` Konrad Dybcio
@ 2021-09-14 16:08 ` Bjorn Andersson
1 sibling, 0 replies; 20+ messages in thread
From: Bjorn Andersson @ 2021-09-14 16:08 UTC (permalink / raw)
To: Konrad Dybcio
Cc: ~postmarketos/upstreaming, martin.botka,
angelogioacchino.delregno, marijn.suijten, jamipkettunen,
Andy Gross, Rob Herring, Kees Cook, Anton Vorontsov, Colin Cross,
Tony Luck, linux-arm-msm, devicetree, linux-kernel
On Fri 20 Aug 15:49 CDT 2021, Konrad Dybcio wrote:
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
[..]
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> +
> + core2 {
> + cpu = <&CPU2>;
> + };
> +
> + core3 {
> + cpu = <&CPU3>;
> + };
> +
> + core4 {
> + cpu = <&CPU4>;
> + };
> +
> + core5 {
> + cpu = <&CPU5>;
> + };
> + };
> +
> + cluster1 {
Shouldn't this be represented as a single "cluster", like other DynamIQ
devices?
> + core0 {
> + cpu = <&CPU6>;
> + };
> +
> + core1 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> + };
Regards,
Bjorn
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2021-09-14 16:08 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20210820204926.235192-1-konrad.dybcio@somainline.org>
2021-08-20 20:49 ` [PATCH 01/17] dt-bindings: arm: cpus: Add Kryo 560 CPUs Konrad Dybcio
2021-08-24 16:46 ` Rob Herring
2021-08-20 20:49 ` [PATCH 02/17] arm64: dts: qcom: Add SM6350 device tree Konrad Dybcio
2021-08-21 14:55 ` Konrad Dybcio
2021-09-14 16:08 ` Bjorn Andersson
2021-08-20 20:49 ` [PATCH 03/17] arm64: dts: qcom: sm6350: Add LLCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 04/17] arm64: dts: qcom: sm6350: Add RPMHCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 05/17] arm64: dts: qcom: sm6350: Add GCC node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 06/17] arm64: dts: qcom: sm6350: Add TLMM block node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 07/17] arm64: dts: qcom: sm6350: Add USB1 nodes Konrad Dybcio
2021-08-20 20:49 ` [PATCH 08/17] arm64: dts: qcom: sm6350: Add cpufreq-hw support Konrad Dybcio
2021-08-20 20:49 ` [PATCH 09/17] arm64: dts: qcom: sm6350: Add TSENS nodes Konrad Dybcio
2021-08-20 20:49 ` [PATCH 10/17] arm64: dts: qcom: sm6350: Add AOSS_QMP Konrad Dybcio
2021-08-20 20:49 ` [PATCH 11/17] arm64: dts: qcom: sm6350: Add SPMI bus Konrad Dybcio
2021-08-20 20:49 ` [PATCH 12/17] arm64: dts: qcom: sm6350: Add PRNG node Konrad Dybcio
2021-08-20 20:49 ` [PATCH 13/17] arm64: dts: qcom: sm6350: Add RPMHPD and BCM voter Konrad Dybcio
2021-08-20 20:49 ` [PATCH 14/17] arm64: dts: qcom: sm6350: Add SDHCI1/2 nodes Konrad Dybcio
2021-08-20 20:49 ` [PATCH 15/17] arm64: dts: qcom: sm6350: Add apps_smmu Konrad Dybcio
2021-08-20 20:49 ` [PATCH 16/17] arm64: dts: qcom: sm6350: Add iommus property to USB1 Konrad Dybcio
2021-08-20 20:49 ` [PATCH 17/17] arm64: dts: qcom: Add device tree for Sony Xperia 10 III Konrad Dybcio
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).