* [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
@ 2021-08-25 1:11 ` Chun-Jie Chen
2021-12-06 16:41 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 2/5] arm64: dts: mediatek: Correct UART " Chun-Jie Chen
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-25 1:11 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
update systimer clock to the real one.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index c7c7d4e017ae..2b63d2ea6cb6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -312,7 +312,7 @@
"mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x1000>;
interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>;
+ clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
clock-names = "clk13m";
};
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192
2021-08-25 1:11 ` [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192 Chun-Jie Chen
@ 2021-12-06 16:41 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2021-12-06 16:41 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi Chun-Jie,
thanks for the patch! However, can you please improve the commit message? Here's
a possible suggestion:
When the initial devicetree for mt8192 was added in 48489980e27e ("arm64:
dts: Add Mediatek SoC MT8192 and evaluation board dts and Makefile"), the
clock driver for mt8192 was not yet upstream, so the clock property nodes
were set to the clk26m clock as a placeholder.
Given that the clock driver has since been added through 710573dee31b ("clk:
mediatek: Add MT8192 basic clocks support"), as well as its dt-bindings
through f35f1a23e0e1 ("clk: mediatek: Add dt-bindings of MT8192 clocks") and
devicetree nodes through 5d2b897bc6f5 ("arm64: dts: mediatek: Add mt8192
clock controllers"), fix the systimer clock property to point to the actual
clock.
Then you could use the same message for the other commits, just updating which
clock is being fixed in the last sentence there. With that improved commit
message:
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index c7c7d4e017ae..2b63d2ea6cb6 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -312,7 +312,7 @@
> "mediatek,mt6765-timer";
> reg = <0 0x10017000 0 0x1000>;
> interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>;
> + clocks = <&topckgen CLK_TOP_CSW_F26M_D2>;
> clock-names = "clk13m";
> };
>
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [v1 2/5] arm64: dts: mediatek: Correct UART clock of MT8192
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
2021-08-25 1:11 ` [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192 Chun-Jie Chen
@ 2021-08-25 1:11 ` Chun-Jie Chen
2021-12-06 16:44 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 3/5] arm64: dts: mediatek: Correct SPI " Chun-Jie Chen
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-25 1:11 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
update uart0 and uart1 bus clock to the real one.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 2b63d2ea6cb6..31d135e18784 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -327,7 +327,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
clock-names = "baud", "bus";
status = "disabled";
};
@@ -337,7 +337,7 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
clock-names = "baud", "bus";
status = "disabled";
};
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [v1 2/5] arm64: dts: mediatek: Correct UART clock of MT8192
2021-08-25 1:11 ` [v1 2/5] arm64: dts: mediatek: Correct UART " Chun-Jie Chen
@ 2021-12-06 16:44 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2021-12-06 16:44 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi,
On Wed, Aug 25, 2021 at 09:11:17AM +0800, Chun-Jie Chen wrote:
> update uart0 and uart1 bus clock to the real one.
With the same commit message improvement from patch 1:
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 2b63d2ea6cb6..31d135e18784 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -327,7 +327,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11002000 0 0x1000>;
> interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> @@ -337,7 +337,7 @@
> "mediatek,mt6577-uart";
> reg = <0 0x11003000 0 0x1000>;
> interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>;
> clock-names = "baud", "bus";
> status = "disabled";
> };
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [v1 3/5] arm64: dts: mediatek: Correct SPI clock of MT8192
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
2021-08-25 1:11 ` [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192 Chun-Jie Chen
2021-08-25 1:11 ` [v1 2/5] arm64: dts: mediatek: Correct UART " Chun-Jie Chen
@ 2021-08-25 1:11 ` Chun-Jie Chen
2021-12-06 16:47 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 4/5] arm64: dts: mediatek: Correct Nor Flash " Chun-Jie Chen
2021-08-25 1:11 ` [v1 5/5] arm64: dts: mediatek: Correct I2C " Chun-Jie Chen
4 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-25 1:11 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
update uart0 ~ 7 clocks to the real ones.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 31d135e18784..d1c85d3e152b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -355,9 +355,9 @@
#size-cells = <0>;
reg = <0 0x1100a000 0 0x1000>;
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -369,9 +369,9 @@
#size-cells = <0>;
reg = <0 0x11010000 0 0x1000>;
interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI1>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -383,9 +383,9 @@
#size-cells = <0>;
reg = <0 0x11012000 0 0x1000>;
interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI2>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -397,9 +397,9 @@
#size-cells = <0>;
reg = <0 0x11013000 0 0x1000>;
interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI3>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -411,9 +411,9 @@
#size-cells = <0>;
reg = <0 0x11018000 0 0x1000>;
interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI4>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -425,9 +425,9 @@
#size-cells = <0>;
reg = <0 0x11019000 0 0x1000>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI5>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -439,9 +439,9 @@
#size-cells = <0>;
reg = <0 0x1101d000 0 0x1000>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI6>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
@@ -453,9 +453,9 @@
#size-cells = <0>;
reg = <0 0x1101e000 0 0x1000>;
interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
+ <&topckgen CLK_TOP_SPI_SEL>,
+ <&infracfg CLK_INFRA_SPI7>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [v1 3/5] arm64: dts: mediatek: Correct SPI clock of MT8192
2021-08-25 1:11 ` [v1 3/5] arm64: dts: mediatek: Correct SPI " Chun-Jie Chen
@ 2021-12-06 16:47 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2021-12-06 16:47 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi,
On Wed, Aug 25, 2021 at 09:11:18AM +0800, Chun-Jie Chen wrote:
> update uart0 ~ 7 clocks to the real ones.
Same comment from patch 1. But also here you had a typo: should be spi instead
of uart.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 48 ++++++++++++------------
> 1 file changed, 24 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 31d135e18784..d1c85d3e152b 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -355,9 +355,9 @@
> #size-cells = <0>;
> reg = <0 0x1100a000 0 0x1000>;
> interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI0>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -369,9 +369,9 @@
> #size-cells = <0>;
> reg = <0 0x11010000 0 0x1000>;
> interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI1>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -383,9 +383,9 @@
> #size-cells = <0>;
> reg = <0 0x11012000 0 0x1000>;
> interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI2>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -397,9 +397,9 @@
> #size-cells = <0>;
> reg = <0 0x11013000 0 0x1000>;
> interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI3>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -411,9 +411,9 @@
> #size-cells = <0>;
> reg = <0 0x11018000 0 0x1000>;
> interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI4>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -425,9 +425,9 @@
> #size-cells = <0>;
> reg = <0 0x11019000 0 0x1000>;
> interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI5>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -439,9 +439,9 @@
> #size-cells = <0>;
> reg = <0 0x1101d000 0 0x1000>;
> interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI6>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> @@ -453,9 +453,9 @@
> #size-cells = <0>;
> reg = <0 0x1101e000 0 0x1000>;
> interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_MAINPLL_D5_D4>,
> + <&topckgen CLK_TOP_SPI_SEL>,
> + <&infracfg CLK_INFRA_SPI7>;
> clock-names = "parent-clk", "sel-clk", "spi-clk";
> status = "disabled";
> };
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [v1 4/5] arm64: dts: mediatek: Correct Nor Flash clock of MT8192
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
` (2 preceding siblings ...)
2021-08-25 1:11 ` [v1 3/5] arm64: dts: mediatek: Correct SPI " Chun-Jie Chen
@ 2021-08-25 1:11 ` Chun-Jie Chen
2021-12-06 16:48 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 5/5] arm64: dts: mediatek: Correct I2C " Chun-Jie Chen
4 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-25 1:11 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
update nor flash clock to the real one.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index d1c85d3e152b..db6f4c6dc404 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -464,9 +464,9 @@
compatible = "mediatek,mt8192-nor";
reg = <0 0x11234000 0 0xe0>;
interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>,
- <&clk26m>,
- <&clk26m>;
+ clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
+ <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
+ <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
clock-names = "spi", "sf", "axi";
#address-cells = <1>;
#size-cells = <0>;
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [v1 4/5] arm64: dts: mediatek: Correct Nor Flash clock of MT8192
2021-08-25 1:11 ` [v1 4/5] arm64: dts: mediatek: Correct Nor Flash " Chun-Jie Chen
@ 2021-12-06 16:48 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2021-12-06 16:48 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi,
On Wed, Aug 25, 2021 at 09:11:19AM +0800, Chun-Jie Chen wrote:
> update nor flash clock to the real one.
Same comment from patch 1.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index d1c85d3e152b..db6f4c6dc404 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -464,9 +464,9 @@
> compatible = "mediatek,mt8192-nor";
> reg = <0 0x11234000 0 0xe0>;
> interrupts = <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>,
> - <&clk26m>,
> - <&clk26m>;
> + clocks = <&topckgen CLK_TOP_SFLASH_SEL>,
> + <&infracfg CLK_INFRA_FLASHIF_SFLASH>,
> + <&infracfg CLK_INFRA_FLASHIF_TOP_H_133M>;
> clock-names = "spi", "sf", "axi";
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [v1 5/5] arm64: dts: mediatek: Correct I2C clock of MT8192
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
` (3 preceding siblings ...)
2021-08-25 1:11 ` [v1 4/5] arm64: dts: mediatek: Correct Nor Flash " Chun-Jie Chen
@ 2021-08-25 1:11 ` Chun-Jie Chen
2021-12-06 16:49 ` Nícolas F. R. A. Prado
4 siblings, 1 reply; 10+ messages in thread
From: Chun-Jie Chen @ 2021-08-25 1:11 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Nicolas Boichat
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group,
Chun-Jie Chen
update i2c 0 ~ 9 clocks to the real ones.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 30 ++++++++++++++++--------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index db6f4c6dc404..866b04e78690 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -484,7 +484,8 @@
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -503,7 +504,8 @@
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -516,7 +518,8 @@
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -529,7 +532,8 @@
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -548,7 +552,8 @@
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -561,7 +566,8 @@
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -574,7 +580,8 @@
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -593,7 +600,8 @@
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +620,8 @@
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +634,8 @@
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
--
2.18.0
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [v1 5/5] arm64: dts: mediatek: Correct I2C clock of MT8192
2021-08-25 1:11 ` [v1 5/5] arm64: dts: mediatek: Correct I2C " Chun-Jie Chen
@ 2021-12-06 16:49 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 10+ messages in thread
From: Nícolas F. R. A. Prado @ 2021-12-06 16:49 UTC (permalink / raw)
To: Chun-Jie Chen
Cc: Matthias Brugger, Rob Herring, Nicolas Boichat, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, srv_heupstream,
Project_Global_Chrome_Upstream_Group
Hi,
On Wed, Aug 25, 2021 at 09:11:20AM +0800, Chun-Jie Chen wrote:
> update i2c 0 ~ 9 clocks to the real ones.
Same comment from patch 1.
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
>
> Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 30 ++++++++++++++++--------
> 1 file changed, 20 insertions(+), 10 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index db6f4c6dc404..866b04e78690 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -484,7 +484,8 @@
> reg = <0 0x11cb0000 0 0x1000>,
> <0 0x10217300 0 0x80>;
> interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -503,7 +504,8 @@
> reg = <0 0x11d00000 0 0x1000>,
> <0 0x10217600 0 0x180>;
> interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -516,7 +518,8 @@
> reg = <0 0x11d01000 0 0x1000>,
> <0 0x10217780 0 0x180>;
> interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -529,7 +532,8 @@
> reg = <0 0x11d02000 0 0x1000>,
> <0 0x10217900 0 0x180>;
> interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -548,7 +552,8 @@
> reg = <0 0x11d20000 0 0x1000>,
> <0 0x10217100 0 0x80>;
> interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -561,7 +566,8 @@
> reg = <0 0x11d21000 0 0x1000>,
> <0 0x10217180 0 0x180>;
> interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -574,7 +580,8 @@
> reg = <0 0x11d22000 0 0x1000>,
> <0 0x10217380 0 0x180>;
> interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -593,7 +600,8 @@
> reg = <0 0x11e00000 0 0x1000>,
> <0 0x10217500 0 0x80>;
> interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -612,7 +620,8 @@
> reg = <0 0x11f00000 0 0x1000>,
> <0 0x10217080 0 0x80>;
> interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> @@ -625,7 +634,8 @@
> reg = <0 0x11f01000 0 0x1000>,
> <0 0x10217580 0 0x80>;
> interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
> - clocks = <&clk26m>, <&clk26m>;
> + clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
> + <&infracfg CLK_INFRA_AP_DMA>;
> clock-names = "main", "dma";
> clock-div = <1>;
> #address-cells = <1>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread