* [PATCH v2 1/8] dt-bindings: arm: fsl: add NXP S32G2 boards
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-08 6:45 ` [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format Chester Lin
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, Shawn Guo, Li Yang, Andreas Färber,
Krzysztof Kozlowski
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, catalin-dan.udma, bogdan.hamciuc,
bogdan.folea, ciprianmarian.costea, Radu Nicolae Pirea,
ghennadi.procopciuc, Matthias Brugger, Ivan T . Ivanov, Lee,
Chun-Yi, Chester Lin, Rob Herring
Add bindings for S32G2's evaluation board (S32G-VNP-EVB) and reference
design board 2 ( S32G-VNP-RDB2).
Signed-off-by: Chester Lin <clin@suse.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v2:
- Rename the vendor string to "nxp,".
Documentation/devicetree/bindings/arm/fsl.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 60f4862ba15e..12ab7ac565fb 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -990,6 +990,13 @@ properties:
- const: solidrun,lx2160a-cex7
- const: fsl,lx2160a
+ - description: S32G2 based Boards
+ items:
+ - enum:
+ - nxp,s32g274a-evb
+ - nxp,s32g274a-rdb2
+ - const: nxp,s32g2
+
- description: S32V234 based Boards
items:
- enum:
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
2021-09-08 6:45 ` [PATCH v2 1/8] dt-bindings: arm: fsl: add NXP S32G2 boards Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-20 22:32 ` Rob Herring
2021-09-08 6:45 ` [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2 Chester Lin
` (6 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Andreas Färber,
Krzysztof Kozlowski, Stoica Cosmin-Stefan, Larisa Grigore
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Shawn Guo, Li Yang, catalin-dan.udma, bogdan.hamciuc,
bogdan.folea, ciprianmarian.costea, Radu Nicolae Pirea,
ghennadi.procopciuc, Matthias Brugger, Ivan T . Ivanov, Lee,
Chun-Yi, Chester Lin
Convert the FSL LINFlexD UART binding to json-schema.
Signed-off-by: Chester Lin <clin@suse.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
---
Changes in v2:
- Drop the specific description "S32V234 SoC".
- Fill my name in the maintainer field. I tried to contact the authors
of fsl,s32-linflexuart.txt but got no response.
.../bindings/serial/fsl,s32-linflexuart.txt | 22 ---------
.../bindings/serial/fsl,s32-linflexuart.yaml | 46 +++++++++++++++++++
2 files changed, 46 insertions(+), 22 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
deleted file mode 100644
index f1bbe0826be5..000000000000
--- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
+++ /dev/null
@@ -1,22 +0,0 @@
-* Freescale LINFlexD UART
-
-The LINFlexD controller implements several LIN protocol versions, as well as
-support for full-duplex UART communication through 8-bit and 9-bit frames.
-
-See chapter 47 ("LINFlexD") in the reference manual[1].
-
-Required properties:
-- compatible :
- - "fsl,s32v234-linflexuart" for LINFlexD configured in UART mode, which
- is compatible with the one integrated on S32V234 SoC
-- reg : Address and length of the register set for the device
-- interrupts : Should contain uart interrupt
-
-Example:
-uart0: serial@40053000 {
- compatible = "fsl,s32v234-linflexuart";
- reg = <0x0 0x40053000 0x0 0x1000>;
- interrupts = <0 59 4>;
-};
-
-[1] https://www.nxp.com/webapp/Download?colCode=S32V234RM
diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
new file mode 100644
index 000000000000..b6fc123e8375
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/fsl,s32-linflexuart.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale LINFlexD UART
+
+description: |
+ The LINFlexD controller implements several LIN protocol versions, as well
+ as support for full-duplex UART communication through 8-bit and 9-bit
+ frames. See chapter 47 ("LINFlexD") in the reference manual
+ https://www.nxp.com/webapp/Download?colCode=S32V234RM.
+
+maintainers:
+ - Chester Lin <clin@suse.com>
+
+allOf:
+ - $ref: "serial.yaml"
+
+properties:
+ compatible:
+ description: The LINFlexD controller in UART mode.
+ items:
+ - const: fsl,s32v234-linflexuart
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ serial@40053000 {
+ compatible = "fsl,s32v234-linflexuart";
+ reg = <0x40053000 0x1000>;
+ interrupts = <0 59 4>;
+ };
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format
2021-09-08 6:45 ` [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format Chester Lin
@ 2021-09-20 22:32 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-09-20 22:32 UTC (permalink / raw)
To: Chester Lin
Cc: devicetree, Radu Nicolae Pirea, Lee, Chun-Yi,
Andreas Färber, ciprianmarian.costea, Ivan T . Ivanov,
Rob Herring, catalin-dan.udma, bogdan.folea, linux-arm-kernel,
ghennadi.procopciuc, linux-kernel, Larisa Grigore,
Stoica Cosmin-Stefan, Greg Kroah-Hartman, Krzysztof Kozlowski,
Li Yang, Matthias Brugger, s32, Shawn Guo, linux-serial,
bogdan.hamciuc
On Wed, 08 Sep 2021 14:45:22 +0800, Chester Lin wrote:
> Convert the FSL LINFlexD UART binding to json-schema.
>
> Signed-off-by: Chester Lin <clin@suse.com>
> Reviewed-by: Andreas Färber <afaerber@suse.de>
> ---
> Changes in v2:
> - Drop the specific description "S32V234 SoC".
> - Fill my name in the maintainer field. I tried to contact the authors
> of fsl,s32-linflexuart.txt but got no response.
>
> .../bindings/serial/fsl,s32-linflexuart.txt | 22 ---------
> .../bindings/serial/fsl,s32-linflexuart.yaml | 46 +++++++++++++++++++
> 2 files changed, 46 insertions(+), 22 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.txt
> create mode 100644 Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
2021-09-08 6:45 ` [PATCH v2 1/8] dt-bindings: arm: fsl: add NXP S32G2 boards Chester Lin
2021-09-08 6:45 ` [PATCH v2 2/8] dt-bindings: serial: fsl-linflexuart: convert to json-schema format Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-20 22:32 ` Rob Herring
2021-09-08 6:45 ` [PATCH v2 4/8] arm64: dts: add NXP S32G2 support Chester Lin
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Greg Kroah-Hartman, Rob Herring, Radu Nicolae Pirea, Andreas Färber
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Shawn Guo, Li Yang, Krzysztof Kozlowski, catalin-dan.udma,
bogdan.hamciuc, bogdan.folea, ciprianmarian.costea,
ghennadi.procopciuc, Matthias Brugger, Ivan T . Ivanov, Lee,
Chun-Yi, Chester Lin
Add a compatible string for the uart binding of NXP S32G2 platforms. Here
we use "s32v234-linflexuart" as fallback since the current linflexuart
driver can still work on S32G2.
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Remove redundant minItems/maxItems from compatible properties.
- Remove the redundant example.
- Rename the vendor string to "nxp," for s32g2.
.../devicetree/bindings/serial/fsl,s32-linflexuart.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
index b6fc123e8375..8b643bae3c7b 100644
--- a/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
+++ b/Documentation/devicetree/bindings/serial/fsl,s32-linflexuart.yaml
@@ -20,9 +20,11 @@ allOf:
properties:
compatible:
- description: The LINFlexD controller in UART mode.
- items:
+ oneOf:
- const: fsl,s32v234-linflexuart
+ - items:
+ - const: nxp,s32g2-linflexuart
+ - const: fsl,s32v234-linflexuart
reg:
maxItems: 1
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2
2021-09-08 6:45 ` [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2 Chester Lin
@ 2021-09-20 22:32 ` Rob Herring
0 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2021-09-20 22:32 UTC (permalink / raw)
To: Chester Lin
Cc: catalin-dan.udma, Shawn Guo, Andreas Färber,
ghennadi.procopciuc, Li Yang, Rob Herring, ciprianmarian.costea,
devicetree, linux-kernel, bogdan.hamciuc, Ivan T . Ivanov,
Radu Nicolae Pirea, Greg Kroah-Hartman, Krzysztof Kozlowski, s32,
Matthias Brugger, Lee, Chun-Yi, bogdan.folea, linux-arm-kernel,
linux-serial
On Wed, 08 Sep 2021 14:45:23 +0800, Chester Lin wrote:
> Add a compatible string for the uart binding of NXP S32G2 platforms. Here
> we use "s32v234-linflexuart" as fallback since the current linflexuart
> driver can still work on S32G2.
>
> Signed-off-by: Chester Lin <clin@suse.com>
> ---
> Changes in v2:
> - Remove redundant minItems/maxItems from compatible properties.
> - Remove the redundant example.
> - Rename the vendor string to "nxp," for s32g2.
>
> .../devicetree/bindings/serial/fsl,s32-linflexuart.yaml | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/8] arm64: dts: add NXP S32G2 support
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (2 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 3/8] dt-bindings: serial: fsl-linflexuart: add compatible for S32G2 Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-08 6:45 ` [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support Chester Lin
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Marc Zyngier, Matthias Brugger
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, Shawn Guo, Li Yang, Krzysztof Kozlowski,
catalin-dan.udma, bogdan.hamciuc, bogdan.folea,
ciprianmarian.costea, Radu Nicolae Pirea, ghennadi.procopciuc,
Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin
Add an initial dtsi file for generic SoC features of NXP S32G2.
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add a SoC description.
- Add an interrupt-affinity to the pmu node.
- Move the psci node into the "/firmware" node.
- Remove the redundant properties and white lines.
- Remove the wrong interrupt specifier from the gic node.
- Specify the range and cell-size of /soc [0 - 4 GiB].
- Correct the reserved size of GICR to 512KiB [0x80000].
arch/arm64/boot/dts/freescale/s32g2.dtsi | 99 ++++++++++++++++++++++++
1 file changed, 99 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32g2.dtsi
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
new file mode 100644
index 000000000000..53b18671deec
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * NXP S32G2 SoC family
+ *
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ compatible = "nxp,s32g2";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ enable-method = "psci";
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ enable-method = "psci";
+ next-level-cache = <&cluster0_l2>;
+ };
+
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x100>;
+ enable-method = "psci";
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cpu3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x101>;
+ enable-method = "psci";
+ next-level-cache = <&cluster1_l2>;
+ };
+
+ cluster0_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ cluster1_l2: l2-cache1 {
+ compatible = "cache";
+ };
+ };
+
+ pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
+ };
+
+ firmware {
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0 0x80000000>;
+
+ gic: interrupt-controller@50800000 {
+ compatible = "arm,gic-v3";
+ reg = <0x50800000 0x10000>,
+ <0x50880000 0x80000>,
+ <0x50400000 0x2000>,
+ <0x50410000 0x2000>,
+ <0x50420000 0x2000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ };
+ };
+};
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (3 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 4/8] arm64: dts: add NXP S32G2 support Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-08 6:45 ` [PATCH v2 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support Chester Lin
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, Larisa Grigore, Radu Nicolae Pirea,
Andreas Färber, Matthias Brugger
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, Shawn Guo, Li Yang, Krzysztof Kozlowski,
catalin-dan.udma, bogdan.hamciuc, bogdan.folea,
ciprianmarian.costea, ghennadi.procopciuc, Ivan T . Ivanov, Lee,
Chun-Yi, Chester Lin
Add serial/uart support for NXP S32G2 based on the information provided by
NXP's CodeAurora BSP.
Signed-off-by: Larisa Grigore <larisa.grigore@nxp.com>
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add new Signed-off-by.
- Fix the copyright string.
- Remove aliases.
- Revise reg properties based on new cell size.
arch/arm64/boot/dts/freescale/s32g2.dtsi | 25 ++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 53b18671deec..59ea8a25aa4c 100644
--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi
@@ -3,6 +3,7 @@
* NXP S32G2 SoC family
*
* Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2017-2021 NXP
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -84,6 +85,30 @@ soc {
#size-cells = <1>;
ranges = <0 0 0 0x80000000>;
+ uart0: serial@401c8000 {
+ compatible = "nxp,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x401c8000 0x3000>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart1: serial@401cc000 {
+ compatible = "nxp,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x401cc000 0x3000>;
+ interrupts = <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ uart2: serial@402bc000 {
+ compatible = "nxp,s32g2-linflexuart",
+ "fsl,s32v234-linflexuart";
+ reg = <0x402bc000 0x3000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@50800000 {
compatible = "arm,gic-v3";
reg = <0x50800000 0x10000>,
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (4 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 5/8] arm64: dts: s32g2: add serial/uart support Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-08 6:45 ` [PATCH v2 7/8] arm64: dts: s32g2: add memory nodes for evb and rdb2 Chester Lin
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Matthias Brugger
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, Shawn Guo, Li Yang, Krzysztof Kozlowski,
catalin-dan.udma, bogdan.hamciuc, bogdan.folea,
ciprianmarian.costea, Radu Nicolae Pirea, ghennadi.procopciuc,
Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin
Add initial device-trees of NXP S32G2's Evaluation Board (S32G-VNP-EVB)
and Reference Design 2 Board (S32G-VNP-RDB2).
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Correct the model string.
- Rename the compatible vendor string to "nxp,".
- Move the serial/uart aliases from the SoC .dtsi to board .dts files.
- Add comments for the uart markings on PCB.
arch/arm64/boot/dts/freescale/Makefile | 2 ++
.../arm64/boot/dts/freescale/s32g274a-evb.dts | 26 +++++++++++++++
.../boot/dts/freescale/s32g274a-rdb2.dts | 32 +++++++++++++++++++
3 files changed, 60 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-evb.dts
create mode 100644 arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index db9e36ebe932..0d4a18bd83e6 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -70,4 +70,6 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb
+dtb-$(CONFIG_ARCH_S32) += s32g274a-rdb2.dtb
dtb-$(CONFIG_ARCH_S32) += s32v234-evb.dtb
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
new file mode 100644
index 000000000000..3aec05de0842
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+/dts-v1/;
+
+#include "s32g2.dtsi"
+
+/ {
+ model = "NXP S32G2 Evaluation Board (S32G-VNP-EVB)";
+ compatible = "nxp,s32g274a-evb", "nxp,s32g2";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* UART (J58) to Micro USB port */
+&uart0 {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
new file mode 100644
index 000000000000..ed3f23babdca
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright (c) 2021 SUSE LLC
+ */
+
+/dts-v1/;
+
+#include "s32g2.dtsi"
+
+/ {
+ model = "NXP S32G2 Reference Design Board 2 (S32G-VNP-RDB2)";
+ compatible = "nxp,s32g274a-rdb2", "nxp,s32g2";
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+/* UART (J2) to Micro USB port */
+&uart0 {
+ status = "okay";
+};
+
+/* UART (J1) to Micro USB port */
+&uart1 {
+ status = "okay";
+};
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 7/8] arm64: dts: s32g2: add memory nodes for evb and rdb2
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (5 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 6/8] arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-09-08 6:45 ` [PATCH v2 8/8] MAINTAINERS: add an entry for NXP S32G boards Chester Lin
2021-10-04 8:11 ` [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Shawn Guo
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Matthias Brugger
Cc: s32, devicetree, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, Shawn Guo, Li Yang, Krzysztof Kozlowski,
catalin-dan.udma, bogdan.hamciuc, bogdan.folea,
ciprianmarian.costea, Radu Nicolae Pirea, ghennadi.procopciuc,
Ivan T . Ivanov, Lee, Chun-Yi, Chester Lin
Add memory nodes for S32G-VNP-EVB and S32G-VNP-RDB2.
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Modify the patch description.
- Fix the copyright string.
- Adjust RAM size comments.
- Convert reg addresses of memory nodes into hex format.
arch/arm64/boot/dts/freescale/s32g274a-evb.dts | 8 ++++++++
arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts | 8 ++++++++
2 files changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
index 3aec05de0842..9118d8d2ee01 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-evb.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2019-2021 NXP
*/
/dts-v1/;
@@ -18,6 +19,13 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ /* 4GiB RAM */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>,
+ <0x8 0x80000000 0 0x80000000>;
+ };
};
/* UART (J58) to Micro USB port */
diff --git a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
index ed3f23babdca..e05ee854cdf5 100644
--- a/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
+++ b/arch/arm64/boot/dts/freescale/s32g274a-rdb2.dts
@@ -1,6 +1,7 @@
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright (c) 2021 SUSE LLC
+ * Copyright (c) 2019-2021 NXP
*/
/dts-v1/;
@@ -19,6 +20,13 @@ aliases {
chosen {
stdout-path = "serial0:115200n8";
};
+
+ /* 4GiB RAM */
+ memory@80000000 {
+ device_type = "memory";
+ reg = <0x0 0x80000000 0 0x80000000>,
+ <0x8 0x80000000 0 0x80000000>;
+ };
};
/* UART (J2) to Micro USB port */
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [PATCH v2 8/8] MAINTAINERS: add an entry for NXP S32G boards
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (6 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 7/8] arm64: dts: s32g2: add memory nodes for evb and rdb2 Chester Lin
@ 2021-09-08 6:45 ` Chester Lin
2021-10-04 8:11 ` [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Shawn Guo
8 siblings, 0 replies; 12+ messages in thread
From: Chester Lin @ 2021-09-08 6:45 UTC (permalink / raw)
To: Rob Herring, devicetree, Andreas Färber, Matthias Brugger,
Krzysztof Kozlowski
Cc: s32, linux-kernel, linux-arm-kernel, linux-serial,
Greg Kroah-Hartman, Shawn Guo, Li Yang, catalin-dan.udma,
bogdan.hamciuc, bogdan.folea, ciprianmarian.costea,
Radu Nicolae Pirea, ghennadi.procopciuc, Ivan T . Ivanov, Lee,
Chun-Yi, Chester Lin
Add a new entry for the maintenance of NXP S32G DT files.
Signed-off-by: Chester Lin <clin@suse.com>
---
Changes in v2:
- Add information of reviewers.
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5a61cb2d0cd4..6f2a3f8ae88e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2308,6 +2308,14 @@ F: arch/arm/boot/dts/nuvoton-wpcm450*
F: arch/arm/mach-npcm/wpcm450.c
F: drivers/*/*wpcm*
+ARM/NXP S32G ARCHITECTURE
+M: Chester Lin <clin@suse.com>
+R: Andreas Färber <afaerber@suse.de>
+R: Matthias Brugger <mbrugger@suse.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S: Maintained
+F: arch/arm64/boot/dts/freescale/s32g*.dts*
+
ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT
L: openmoko-kernel@lists.openmoko.org (subscribers-only)
S: Orphan
--
2.30.0
^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support
2021-09-08 6:45 [PATCH v2 0/8] arm64: dts: initial NXP S32G2 support Chester Lin
` (7 preceding siblings ...)
2021-09-08 6:45 ` [PATCH v2 8/8] MAINTAINERS: add an entry for NXP S32G boards Chester Lin
@ 2021-10-04 8:11 ` Shawn Guo
8 siblings, 0 replies; 12+ messages in thread
From: Shawn Guo @ 2021-10-04 8:11 UTC (permalink / raw)
To: Chester Lin
Cc: Rob Herring, Greg Kroah-Hartman, devicetree, linux-arm-kernel,
s32, Li Yang, Andreas Färber, Matthias Brugger,
Radu Nicolae Pirea, linux-kernel, linux-serial,
Krzysztof Kozlowski, catalin-dan.udma, bogdan.hamciuc,
bogdan.folea, ciprianmarian.costea, ghennadi.procopciuc,
Ivan T . Ivanov, Lee, Chun-Yi
On Wed, Sep 08, 2021 at 02:45:20PM +0800, Chester Lin wrote:
> Hello,
>
> Here I'd like to propose a patchset, which is initial upstream support for NXP
> S32G2. S32G is a processor family developed by NXP for automotive solutions,
> such as vehicle networking and automotive high-performance processing. This
> series focuses on S32G2, which is the latest generation we can find at the
> moment. As the first round to support S32G2, this patchset only enables basic
> components and interfaces the SoC must have while kernel booting, which aims
> to have minimum hardware enablement for these two boards, S32G-VNP-EVB and
> S32G-VNP-RDB2. The concepts of how these boards work are originated from the
> downstream kernel tree[1] developed by NXP, which provides lots of details
> about the SoC S32G274A and its integrated boards. This series has been
> verified with downstream ATF[2] & U-Boot[3] based on the ATF boot flow.
>
> Thanks,
> Chester
>
> [1] https://source.codeaurora.org/external/autobsps32/linux/
> [2] https://source.codeaurora.org/external/autobsps32/arm-trusted-firmware/
> [3] https://source.codeaurora.org/external/autobsps32/u-boot/
>
> Changes in v2:
> - dt-bindings:
> - Rename the compatible vendor string to "nxp," for s32g2.
> - Drop the specific description "S32V234 SoC".
> - Fill my name in the maintainer field. I tried to contact the authors
> of fsl,s32-linflexuart.txt but got no response.
> - Remove redundant minItems/maxItems from compatible properties.
> - Remove the redundant example from fsl,s32-linflexuart.yaml.
> - dtsi/dts:
> - Add a SoC description in s32g2.dtsi.
> - Add an interrupt-affinity to the pmu node.
> - Move the psci node into the "/firmware" node.
> - Remove the redundant properties and white lines in DT.
> - Remove the wrong interrupt specifier from the gic node.
> - Specify the range and cell-size of /soc [0 - 4 GiB].
> - Correct the reserved size of GICR to 512Kbytes [0x80000].
> - Add new Signed-off-by to the DT uart patch.
> - Fix copyright strings.
> - Revise reg properties based on new cell-size.
> - Move the serial/uart aliases from the SoC .dtsi to board .dts files.
> - Correct the model string of RDB2.
> - Add comments for the uart markings on PCB.
> - Adjust RAM size comments of memory nodes.
> - Convert reg addresses of memory nodes into hex format.
> - MAINTAINERS
> - Add information of reviewers.
>
> Chester Lin (8):
> dt-bindings: arm: fsl: add NXP S32G2 boards
> dt-bindings: serial: fsl-linflexuart: convert to json-schema format
> dt-bindings: serial: fsl-linflexuart: add compatible for S32G2
> arm64: dts: add NXP S32G2 support
> arm64: dts: s32g2: add serial/uart support
> arm64: dts: s32g2: add VNP-EVB and VNP-RDB2 support
> arm64: dts: s32g2: add memory nodes for evb and rdb2
> MAINTAINERS: add an entry for NXP S32G boards
Applied all, thanks!
^ permalink raw reply [flat|nested] 12+ messages in thread