From: Hector Martin <marcan@marcan.st>
To: linux-arm-kernel@lists.infradead.org
Cc: Hector Martin <marcan@marcan.st>,
Alyssa Rosenzweig <alyssa@rosenzweig.io>,
Sven Peter <sven@svenpeter.dev>, Marc Zyngier <maz@kernel.org>,
Mark Kettenis <mark.kettenis@xs4all.nl>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Viresh Kumar <vireshk@kernel.org>, Nishanth Menon <nm@ti.com>,
Catalin Marinas <catalin.marinas@arm.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Kevin Hilman <khilman@kernel.org>,
Ulf Hansson <ulf.hansson@linaro.org>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [RFC PATCH 2/9] dt-bindings: memory-controller: Add apple,mcc binding
Date: Tue, 12 Oct 2021 01:57:00 +0900 [thread overview]
Message-ID: <20211011165707.138157-3-marcan@marcan.st> (raw)
In-Reply-To: <20211011165707.138157-1-marcan@marcan.st>
This device represents the memory controller in Apple SoCs, and is
chiefly in charge of adjusting performance characteristics according to
system demand.
Signed-off-by: Hector Martin <marcan@marcan.st>
---
.../memory-controllers/apple,mcc.yaml | 80 +++++++++++++++++++
.../opp/apple,mcc-operating-points.yaml | 62 ++++++++++++++
2 files changed, 142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml
create mode 100644 Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml
diff --git a/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml b/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml
new file mode 100644
index 000000000000..0774f10e65ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/memory-controllers/apple,mcc.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/memory-controllers/apple,mcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple SoC MCC memory controller performance controls
+
+maintainers:
+ - Hector Martin <marcan@marcan.st>
+
+description: |
+ Apple SoCs contain a multichannel memory controller that can have its
+ configuration changed to adjust to changing performance requirements from
+ the rest of the SoC. This node represents the controller and provides a
+ power domain provider that downstream devices can use to adjust the memory
+ controller performance level.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - apple,t8103-mcc
+ - const: apple,mcc
+
+ reg:
+ maxItems: 1
+
+ "#power-domain-cells":
+ const: 0
+
+ operating-points-v2:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description:
+ A reference to the OPP table describing the memory controller performance
+ levels. Each OPP node should contain an `apple,memory-perf-config`
+ property that contains the configuration values for that performance
+ level.
+
+ apple,num-channels:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The number of memory channels in use.
+
+required:
+ - compatible
+ - reg
+ - "#power-domain-cells"
+ - operating-points-v2
+ - apple,num-channels
+
+additionalProperties: false
+
+examples:
+ # See clock/apple,cluster-clock.yaml for an example of downstream usage.
+ - |
+ mcc_opp: opp-table-2 {
+ compatible = "operating-points-v2";
+
+ mcc_lowperf: opp0 {
+ opp-level = <0>;
+ apple,memory-perf-config = <0x813057f 0x1800180>;
+ };
+ mcc_highperf: opp1 {
+ opp-level = <1>;
+ apple,memory-perf-config = <0x133 0x55555340>;
+ };
+ };
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mcc: memory-controller@200200000 {
+ compatible = "apple,t8103-mcc", "apple,mcc";
+ #power-domain-cells = <0>;
+ reg = <0x2 0x200000 0x0 0x200000>;
+ operating-points-v2 = <&mcc_opp>;
+ apple,num-channels = <8>;
+ };
+ };
diff --git a/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml b/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml
new file mode 100644
index 000000000000..babf27841bb7
--- /dev/null
+++ b/Documentation/devicetree/bindings/opp/apple,mcc-operating-points.yaml
@@ -0,0 +1,62 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/opp/apple,mcc-operating-points.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Apple SoC memory controller OPP bindings
+
+maintainers:
+ - Hector Martin <marcan@marcan.st>
+
+description: |
+ Apple SoCs can have their memory controller performance adjusted depending on
+ system requirements. These performance states are represented by specific
+ memory controller register values. The apple-mcc driver uses these values
+ to change the MCC performance.
+
+allOf:
+ - $ref: opp-v2-base.yaml#
+
+properties:
+ compatible:
+ const: apple,mcc-operating-points
+
+required:
+ - compatible
+
+patternProperties:
+ "opp[0-9]+":
+ type: object
+
+ properties:
+ opp-level: true
+ apple,memory-perf-config:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ A pair of register values used to configure this performance state.
+ minItems: 2
+ maxItems: 2
+
+ required:
+ - opp-level
+ - apple,memory-perf-config
+
+ unevaluatedProperties: false
+
+additionalProperties: false
+
+examples:
+ - |
+ mcc_opp: opp-table-2 {
+ compatible = "operating-points-v2";
+
+ mcc_lowperf: opp0 {
+ opp-level = <0>;
+ apple,memory-perf-config = <0x813057f 0x1800180>;
+ };
+ mcc_highperf: opp1 {
+ opp-level = <1>;
+ apple,memory-perf-config = <0x133 0x55555340>;
+ };
+ };
--
2.33.0
next prev parent reply other threads:[~2021-10-11 16:57 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-11 16:56 [RFC PATCH 0/9] Apple SoC CPU P-state switching Hector Martin
2021-10-11 16:56 ` [RFC PATCH 1/9] MAINTAINERS: apple: Add apple-mcc and clk-apple-cluster paths Hector Martin
2021-10-11 16:57 ` Hector Martin [this message]
2021-10-12 8:48 ` [RFC PATCH 2/9] dt-bindings: memory-controller: Add apple,mcc binding Krzysztof Kozlowski
2021-10-19 22:43 ` Rob Herring
2021-10-11 16:57 ` [RFC PATCH 3/9] dt-bindings: clock: Add apple,cluster-clk binding Hector Martin
2021-10-12 8:51 ` Krzysztof Kozlowski
2021-10-12 9:35 ` Viresh Kumar
[not found] ` <D0DE08FE-562E-4A48-BCA0-9094DAFCA564@marcan.st>
[not found] ` <20211012094302.3cownyzr4phxwifs@vireshk-i7>
[not found] ` <64584F8C-D49F-41B5-9658-CF8A25186E67@marcan.st>
[not found] ` <20211012095735.mhh2lzu52ohtotl6@vireshk-i7>
2021-10-12 13:48 ` Hector Martin
2021-10-11 16:57 ` [RFC PATCH 4/9] opp: core: Don't warn if required OPP device does not exist Hector Martin
2021-10-12 3:21 ` Viresh Kumar
2021-10-12 5:34 ` Hector Martin
2021-10-12 5:51 ` Viresh Kumar
2021-10-12 5:57 ` Hector Martin
2021-10-12 9:26 ` Viresh Kumar
2021-10-12 9:31 ` Hector Martin "marcan"
2021-10-12 9:32 ` Viresh Kumar
2021-10-14 6:52 ` Hector Martin
2021-10-14 6:56 ` Viresh Kumar
2021-10-14 7:03 ` Hector Martin
2021-10-14 7:22 ` Viresh Kumar
2021-10-14 7:23 ` Hector Martin
2021-10-14 11:08 ` Ulf Hansson
2021-10-14 9:55 ` Ulf Hansson
2021-10-14 11:43 ` Hector Martin
2021-10-14 12:55 ` Ulf Hansson
2021-10-14 17:02 ` Hector Martin
2021-10-15 11:26 ` Ulf Hansson
2021-10-11 16:57 ` [RFC PATCH 5/9] PM: domains: Add of_genpd_add_provider_simple_noclk() Hector Martin
2021-10-11 16:57 ` [RFC PATCH 6/9] memory: apple: Add apple-mcc driver to manage MCC perf in Apple SoCs Hector Martin
2021-10-12 9:19 ` Krzysztof Kozlowski
2021-10-14 6:59 ` Hector Martin
2021-10-14 7:36 ` Krzysztof Kozlowski
2021-10-14 7:52 ` Hector Martin
2021-10-14 8:04 ` Krzysztof Kozlowski
2021-10-14 8:31 ` Hector Martin
2021-10-11 16:57 ` [RFC PATCH 7/9] clk: apple: Add clk-apple-cluster driver to manage CPU p-states Hector Martin
[not found] ` <163424925931.1688384.9647104000291025081@swboyd.mtv.corp.google.com>
2021-10-17 9:16 ` Hector Martin
2021-10-11 16:57 ` [RFC PATCH 8/9] arm64: apple: Select MEMORY and APPLE_MCC Hector Martin
2021-10-11 16:57 ` [RFC PATCH 9/9] arm64: apple: Add CPU frequency scaling support for t8103 Hector Martin
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