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* [PATCH] clk: tegra: Use div64_ul instead of do_div
@ 2021-11-17  1:47 cgel.zte
  2021-11-18  7:41 ` [PATCH v2] " cgel.zte
  0 siblings, 1 reply; 2+ messages in thread
From: cgel.zte @ 2021-11-17  1:47 UTC (permalink / raw)
  To: pdeschrijver
  Cc: pgaikwad, mturquette, sboyd, thierry.reding, jonathanh,
	linux-clk, linux-tegra, linux-kernel, Changcheng Deng,
	Zeal Robot

From: Changcheng Deng <deng.changcheng@zte.com.cn>

do_div() does a 64-by-32 division. If the divisor is unsigned long, using
div64_ul can avoid truncation to 32-bit.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn>
---
 drivers/clk/tegra/clk-utils.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-utils.c b/drivers/clk/tegra/clk-utils.c
index 1a5daae4e501..12658add9dd7 100644
--- a/drivers/clk/tegra/clk-utils.c
+++ b/drivers/clk/tegra/clk-utils.c
@@ -26,7 +26,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
 	if (flags & TEGRA_DIVIDER_ROUND_UP)
 		divider_ux1 += rate - 1;
 
-	do_div(divider_ux1, rate);
+	div64_ul(divider_ux1, rate);
 
 	if (flags & TEGRA_DIVIDER_INT)
 		divider_ux1 *= mul;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* [PATCH v2] clk: tegra: Use div64_ul instead of do_div
  2021-11-17  1:47 [PATCH] clk: tegra: Use div64_ul instead of do_div cgel.zte
@ 2021-11-18  7:41 ` cgel.zte
  0 siblings, 0 replies; 2+ messages in thread
From: cgel.zte @ 2021-11-18  7:41 UTC (permalink / raw)
  To: pdeschrijver
  Cc: jonathanh, linux-clk, linux-kernel, linux-tegra, mturquette,
	pgaikwad, sboyd, thierry.reding, zealci, cgel.zte,
	deng.changcheng

From: Changcheng Deng <deng.changcheng@zte.com.cn>

do_div() does a 64-by-32 division. Here the divisor is an unsigned long
which on some platforms is 64 bit wide. So use div64_ul instead of do_div
to avoid a possible truncation.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Changcheng Deng <deng.changcheng@zte.com.cn>
---
 drivers/clk/tegra/clk-utils.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/tegra/clk-utils.c b/drivers/clk/tegra/clk-utils.c
index 1a5daae4e501..12658add9dd7 100644
--- a/drivers/clk/tegra/clk-utils.c
+++ b/drivers/clk/tegra/clk-utils.c
@@ -26,7 +26,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
 	if (flags & TEGRA_DIVIDER_ROUND_UP)
 		divider_ux1 += rate - 1;
 
-	do_div(divider_ux1, rate);
+	divider_ux1 = div64_ul(divider_ux1, rate);
 
 	if (flags & TEGRA_DIVIDER_INT)
 		divider_ux1 *= mul;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2021-11-18  7:41 UTC | newest]

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2021-11-17  1:47 [PATCH] clk: tegra: Use div64_ul instead of do_div cgel.zte
2021-11-18  7:41 ` [PATCH v2] " cgel.zte

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