From: "Pali Rohár" <pali@kernel.org>
To: "Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Marek Behún" <kabel@kernel.org>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PATCH 10/15] PCI: mvebu: Set PCI Bridge Class Code to PCI Bridge
Date: Thu, 25 Nov 2021 13:46:00 +0100 [thread overview]
Message-ID: <20211125124605.25915-11-pali@kernel.org> (raw)
In-Reply-To: <20211125124605.25915-1-pali@kernel.org>
The default value of Class Code of this bridge corresponds to a Memory
controller, though. This is probably relict from the past when old
Marvell/Galileo PCI-based controllers were used as standalone PCI device
for connecting SDRAM or workaround for PCs with broken BIOS. Details are
in commit 36de23a4c5f0 ("MIPS: Cobalt: Explain GT64111 early PCI fixup").
Change the Class Code to correspond to a PCI Bridge.
Add comment explaining this change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Cc: stable@vger.kernel.org
---
drivers/pci/controller/pci-mvebu.c | 28 +++++++++++++++++++++++++++-
1 file changed, 27 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/pci-mvebu.c b/drivers/pci/controller/pci-mvebu.c
index 017ae9f869ac..4edce441901c 100644
--- a/drivers/pci/controller/pci-mvebu.c
+++ b/drivers/pci/controller/pci-mvebu.c
@@ -225,7 +225,7 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
{
- u32 ctrl, cmd, mask;
+ u32 ctrl, cmd, dev_rev, mask;
/* Setup PCIe controller to Root Complex mode. */
ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
@@ -237,6 +237,32 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
mvebu_writel(port, cmd, PCIE_CMD_OFF);
+ /*
+ * Change Class Code of PCI Bridge device to PCI Bridge (0x6004)
+ * because default value is Memory controller (0x5080).
+ *
+ * Note that this mvebu PCI Bridge does not have compliant Type 1
+ * Configuration Space. Header Type is reported as Type 0 and it
+ * has format of Type 0 config space.
+ *
+ * Moreover Type 0 BAR registers (ranges 0x10 - 0x28 and 0x30 - 0x34)
+ * have the same format in Marvell's specification as in PCIe
+ * specification, but their meaning is totally different and they do
+ * different things: they are aliased into internal mvebu registers
+ * (e.g. PCIE_BAR_LO_OFF) and these should not be changed or
+ * reconfigured by pci device drivers.
+ *
+ * Therefore driver uses emulation of PCI Bridge which emulates
+ * access to configuration space via internal mvebu registers or
+ * emulated configuration buffer. Driver access these PCI Bridge
+ * directly for simplification, but these registers can be accessed
+ * also via standard mvebu way for accessing PCI config space.
+ */
+ dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
+ dev_rev &= ~0xffffff00;
+ dev_rev |= (PCI_CLASS_BRIDGE_PCI << 8) << 8;
+ mvebu_writel(port, dev_rev, PCIE_DEV_REV_OFF);
+
/* Point PCIe unit MBUS decode windows to DRAM space. */
mvebu_pcie_setup_wins(port);
--
2.20.1
next prev parent reply other threads:[~2021-11-25 12:50 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 12:45 [PATCH 00/15] pci: mvebu: Various fixes Pali Rohár
2021-11-25 12:45 ` [PATCH 01/15] PCI: mvebu: Check for valid ports Pali Rohár
2021-11-25 12:45 ` [PATCH 02/15] PCI: mvebu: Check for errors from pci_bridge_emul_init() call Pali Rohár
2021-11-25 12:45 ` [PATCH 03/15] PCI: mvebu: Check that PCI bridge specified in DT has function number zero Pali Rohár
2022-01-07 18:15 ` Bjorn Helgaas
2022-01-07 18:18 ` Pali Rohár
2022-01-07 21:09 ` Bjorn Helgaas
2022-01-07 21:58 ` Pali Rohár
2021-11-25 12:45 ` [PATCH 04/15] PCI: mvebu: Handle invalid size of read config request Pali Rohár
2022-01-07 18:45 ` Bjorn Helgaas
2022-01-07 19:15 ` Russell King (Oracle)
2021-11-25 12:45 ` [PATCH 05/15] PCI: mvebu: Disallow mapping interrupts on emulated bridges Pali Rohár
2022-01-07 21:32 ` Bjorn Helgaas
2022-01-07 22:13 ` Pali Rohár
2022-01-07 23:01 ` Bjorn Helgaas
2022-01-07 23:11 ` Pali Rohár
2021-11-25 12:45 ` [PATCH 06/15] PCI: mvebu: Fix support for bus mastering and PCI_COMMAND on emulated bridge Pali Rohár
2021-11-25 12:45 ` [PATCH 07/15] PCI: mvebu: Do not modify PCI IO type bits in conf_write Pali Rohár
2021-11-25 12:45 ` [PATCH 08/15] PCI: mvebu: Propagate errors when updating PCI_IO_BASE and PCI_MEM_BASE registers Pali Rohár
2022-01-07 21:55 ` Bjorn Helgaas
2022-01-07 22:28 ` Pali Rohár
2022-01-07 23:16 ` Bjorn Helgaas
2022-01-07 23:46 ` Pali Rohár
2022-01-13 0:19 ` Bjorn Helgaas
2022-01-13 10:35 ` Pali Rohár
2022-01-20 17:50 ` Bjorn Helgaas
2022-01-20 19:08 ` Pali Rohár
2022-01-20 19:37 ` Bjorn Helgaas
2021-11-25 12:45 ` [PATCH 09/15] PCI: mvebu: Setup PCIe controller to Root Complex mode Pali Rohár
2021-11-25 12:46 ` Pali Rohár [this message]
2021-11-25 12:46 ` [PATCH 11/15] PCI: mvebu: Fix configuring secondary bus of PCIe Root Port via emulated bridge Pali Rohár
2021-11-25 12:46 ` [PATCH 12/15] PCI: mvebu: Fix support for PCI_BRIDGE_CTL_BUS_RESET on " Pali Rohár
2021-11-25 12:46 ` [PATCH 13/15] PCI: mvebu: Fix support for PCI_EXP_DEVCTL " Pali Rohár
2021-11-25 12:46 ` [PATCH 14/15] PCI: mvebu: Fix support for PCI_EXP_RTSTA " Pali Rohár
2021-11-25 12:46 ` [PATCH 15/15] PCI: mvebu: Fix support for DEVCAP2, DEVCTL2 and LNKCTL2 registers " Pali Rohár
2022-01-04 15:04 ` [PATCH 00/15] pci: mvebu: Various fixes Lorenzo Pieralisi
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