From: Tianfei zhang <tianfei.zhang@intel.com>
To: hao.wu@intel.com, trix@redhat.com, mdf@kernel.org,
yilun.xu@intel.com, linux-fpga@vger.kernel.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: corbet@lwn.net, Matthew Gerlach <matthew.gerlach@linux.intel.com>,
Tianfei Zhang <tianfei.zhang@intel.com>
Subject: [PATCH v1 6/7] fpga: dfl: Handle dfl's starting with AFU
Date: Mon, 14 Feb 2022 06:26:18 -0500 [thread overview]
Message-ID: <20220214112619.219761-7-tianfei.zhang@intel.com> (raw)
In-Reply-To: <20220214112619.219761-1-tianfei.zhang@intel.com>
From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Allow for a Device Feature List (DFL) to start with
a Device Feature Header (DFH) of type Accelerator Function Unit (AFU)
by doing nothing. This allows for PCIe VFs to be created.
Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
drivers/fpga/dfl-pci.c | 7 ++++++-
drivers/fpga/dfl.c | 23 ++++++++++++++---------
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c
index 8abd9b408403..83b604d6dbe6 100644
--- a/drivers/fpga/dfl-pci.c
+++ b/drivers/fpga/dfl-pci.c
@@ -277,7 +277,12 @@ static int find_dfls_by_default(struct pci_dev *pcidev,
dfl_fpga_enum_info_add_dfl(info, start, len);
} else {
- ret = -ENODEV;
+ v = readq(base + DFH);
+ if (FIELD_GET(DFH_TYPE, v) != DFH_TYPE_AFU) {
+ dev_info(&pcidev->dev, "Unknown feature type 0x%llx id 0x%llx\n",
+ FIELD_GET(DFH_TYPE, v), FIELD_GET(DFH_ID, v));
+ ret = -ENODEV;
+ }
}
/* release I/O mappings for next step enumeration */
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index a5263ac258c5..25bd24a4cca0 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -900,9 +900,11 @@ static void build_info_free(struct build_feature_devs_info *binfo)
dfl_id_free(feature_dev_id_type(binfo->feature_dev),
binfo->feature_dev->id);
- list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
- list_del(&finfo->node);
- kfree(finfo);
+ if (!list_empty(&binfo->sub_features)) {
+ list_for_each_entry_safe(finfo, p, &binfo->sub_features, node) {
+ list_del(&finfo->node);
+ kfree(finfo);
+ }
}
}
@@ -1437,6 +1439,7 @@ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
binfo->dev = info->dev;
binfo->cdev = cdev;
+ INIT_LIST_HEAD(&binfo->sub_features);
binfo->nr_irqs = info->nr_irqs;
if (info->nr_irqs)
@@ -1446,12 +1449,14 @@ dfl_fpga_feature_devs_enumerate(struct dfl_fpga_enum_info *info)
* start enumeration for all feature devices based on Device Feature
* Lists.
*/
- list_for_each_entry(dfl, &info->dfls, node) {
- ret = parse_feature_list(binfo, dfl->start, dfl->len);
- if (ret) {
- remove_feature_devs(cdev);
- build_info_free(binfo);
- goto unregister_region_exit;
+ if (!list_empty(&info->dfls)) {
+ list_for_each_entry(dfl, &info->dfls, node) {
+ ret = parse_feature_list(binfo, dfl->start, dfl->len);
+ if (ret) {
+ remove_feature_devs(cdev);
+ build_info_free(binfo);
+ goto unregister_region_exit;
+ }
}
}
--
2.17.1
next prev parent reply other threads:[~2022-02-14 11:39 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 11:26 [PATCH v1 0/7] Add Intel OFS support for DFL driver Tianfei zhang
2022-02-14 11:26 ` [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS Tianfei zhang
2022-02-14 12:18 ` Akira Yokosawa
2022-02-14 17:56 ` Randy Dunlap
2022-02-14 23:27 ` Zhang, Tianfei
2022-02-15 14:32 ` Tom Rix
2022-02-16 3:34 ` Wu, Hao
2022-02-21 7:39 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 2/7] fpga: dfl: check feature type before parse irq info Tianfei zhang
2022-02-15 14:49 ` Tom Rix
2022-02-17 2:38 ` Xu Yilun
2022-02-21 7:54 ` Zhang, Tianfei
2022-02-18 6:53 ` Zhang, Tianfei
2022-02-18 14:29 ` Tom Rix
2022-02-21 12:05 ` Zhang, Tianfei
2022-02-16 3:35 ` Wu, Hao
2022-02-21 7:41 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space Tianfei zhang
2022-02-15 15:05 ` Tom Rix
2022-02-18 7:31 ` Zhang, Tianfei
2022-02-18 14:49 ` Tom Rix
2022-02-21 17:22 ` matthew.gerlach
2022-02-21 17:51 ` Tom Rix
2022-02-22 9:07 ` Zhang, Tianfei
2022-02-16 3:38 ` Wu, Hao
2022-02-21 7:48 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 4/7] fpga: dfl: fix VF creation when ports have no local BAR space Tianfei zhang
2022-02-15 15:50 ` Tom Rix
2022-02-18 8:14 ` Zhang, Tianfei
2022-02-18 14:55 ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list Tianfei zhang
2022-02-15 15:55 ` Tom Rix
2022-02-18 8:24 ` Zhang, Tianfei
2022-02-14 11:26 ` Tianfei zhang [this message]
2022-02-15 16:09 ` [PATCH v1 6/7] fpga: dfl: Handle dfl's starting with AFU Tom Rix
2022-02-14 11:26 ` [PATCH v1 7/7] fpga: dfl: pci: Add generic OFS PCI PID Tianfei zhang
2022-02-15 16:16 ` Tom Rix
2022-02-18 9:03 ` Zhang, Tianfei
2022-02-18 15:27 ` Tom Rix
2022-02-21 17:50 ` matthew.gerlach
2022-02-21 18:09 ` Tom Rix
2022-02-22 3:11 ` Zhang, Tianfei
2022-02-22 16:11 ` Tom Rix
2022-02-23 1:48 ` Zhang, Tianfei
2022-02-24 17:54 ` matthew.gerlach
2022-02-28 10:57 ` Wu, Hao
2022-03-01 0:25 ` matthew.gerlach
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