From: "Zhang, Tianfei" <tianfei.zhang@intel.com>
To: Tom Rix <trix@redhat.com>, "Wu, Hao" <hao.wu@intel.com>,
"mdf@kernel.org" <mdf@kernel.org>,
"Xu, Yilun" <yilun.xu@intel.com>,
"linux-fpga@vger.kernel.org" <linux-fpga@vger.kernel.org>,
"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Cc: "corbet@lwn.net" <corbet@lwn.net>,
Matthew Gerlach <matthew.gerlach@linux.intel.com>
Subject: RE: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
Date: Fri, 18 Feb 2022 08:24:50 +0000 [thread overview]
Message-ID: <BN9PR11MB5483DE5B3268E74B0C439CD8E3379@BN9PR11MB5483.namprd11.prod.outlook.com> (raw)
In-Reply-To: <6fae1b06-f275-fc11-8a3f-92fd7c666396@redhat.com>
> -----Original Message-----
> From: Tom Rix <trix@redhat.com>
> Sent: Tuesday, February 15, 2022 11:56 PM
> To: Zhang, Tianfei <tianfei.zhang@intel.com>; Wu, Hao <hao.wu@intel.com>;
> mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org;
> linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org
> Cc: corbet@lwn.net; Matthew Gerlach <matthew.gerlach@linux.intel.com>
> Subject: Re: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
>
>
> On 2/14/22 3:26 AM, Tianfei zhang wrote:
> > From: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> >
> > Not all FPGA designs managed by the DFL driver have a port.
> > In these cases, don't write the Port Access Control register when
> > enabling SRIOV.
>
> Drop the 'drivers:' in the subject line.
Yes, I agree.
>
> This patch likely needs to moved to 4/7 since the last patch also iterated over
> the list.
Yes, I agree, I will move it on next version patch.
>
> Tom
>
> >
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
> > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
> > ---
> > drivers/fpga/dfl.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index
> > cfc539a656f0..a5263ac258c5 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct
> dfl_fpga_cdev *cdev, int num_vfs)
> > int ret = 0, port_count = 0;
> >
> > mutex_lock(&cdev->lock);
> > + if (list_empty(&cdev->port_dev_list))
> > + goto done;
> >
> > list_for_each_entry(pdata, &cdev->port_dev_list, node) {
> > if (pdata->dev)
next prev parent reply other threads:[~2022-02-18 8:25 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 11:26 [PATCH v1 0/7] Add Intel OFS support for DFL driver Tianfei zhang
2022-02-14 11:26 ` [PATCH v1 1/7] Documentation: fpga: dfl: add description of IOFS Tianfei zhang
2022-02-14 12:18 ` Akira Yokosawa
2022-02-14 17:56 ` Randy Dunlap
2022-02-14 23:27 ` Zhang, Tianfei
2022-02-15 14:32 ` Tom Rix
2022-02-16 3:34 ` Wu, Hao
2022-02-21 7:39 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 2/7] fpga: dfl: check feature type before parse irq info Tianfei zhang
2022-02-15 14:49 ` Tom Rix
2022-02-17 2:38 ` Xu Yilun
2022-02-21 7:54 ` Zhang, Tianfei
2022-02-18 6:53 ` Zhang, Tianfei
2022-02-18 14:29 ` Tom Rix
2022-02-21 12:05 ` Zhang, Tianfei
2022-02-16 3:35 ` Wu, Hao
2022-02-21 7:41 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space Tianfei zhang
2022-02-15 15:05 ` Tom Rix
2022-02-18 7:31 ` Zhang, Tianfei
2022-02-18 14:49 ` Tom Rix
2022-02-21 17:22 ` matthew.gerlach
2022-02-21 17:51 ` Tom Rix
2022-02-22 9:07 ` Zhang, Tianfei
2022-02-16 3:38 ` Wu, Hao
2022-02-21 7:48 ` Zhang, Tianfei
2022-02-14 11:26 ` [PATCH v1 4/7] fpga: dfl: fix VF creation when ports have no local BAR space Tianfei zhang
2022-02-15 15:50 ` Tom Rix
2022-02-18 8:14 ` Zhang, Tianfei
2022-02-18 14:55 ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list Tianfei zhang
2022-02-15 15:55 ` Tom Rix
2022-02-18 8:24 ` Zhang, Tianfei [this message]
2022-02-14 11:26 ` [PATCH v1 6/7] fpga: dfl: Handle dfl's starting with AFU Tianfei zhang
2022-02-15 16:09 ` Tom Rix
2022-02-14 11:26 ` [PATCH v1 7/7] fpga: dfl: pci: Add generic OFS PCI PID Tianfei zhang
2022-02-15 16:16 ` Tom Rix
2022-02-18 9:03 ` Zhang, Tianfei
2022-02-18 15:27 ` Tom Rix
2022-02-21 17:50 ` matthew.gerlach
2022-02-21 18:09 ` Tom Rix
2022-02-22 3:11 ` Zhang, Tianfei
2022-02-22 16:11 ` Tom Rix
2022-02-23 1:48 ` Zhang, Tianfei
2022-02-24 17:54 ` matthew.gerlach
2022-02-28 10:57 ` Wu, Hao
2022-03-01 0:25 ` matthew.gerlach
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