[PATCH v4 0/3] x86/mce: Support extended MCA_ADDR address on SMCA systems

[PATCH v4 0/3] x86/mce: Support extended MCA_ADDR address on SMCA systems

[Smita Koralahalli]

This series of patches adds support for extended physical address on newer
AMD processors such as AMD 'Milan'.

The first patch provides a fix to avoid unnecessary padding in mce_bank
struct.

The second patch defines a separate helper function to extract
MCA_ADDR[ErrorAddr].

Finally, the last patch adds support for extended ErrorAddr bits in
MCA_ADDR.

Link:
https://lkml.kernel.org/r/20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com

Smita Koralahalli (3):
  x86/mce: Avoid unnecessary padding in struct mce_bank
  x86/mce: Define function to extract ErrorAddr from MCA_ADDR
  x86/mce: Add support for Extended Physical Address MCA changes

 arch/x86/include/asm/mce.h         |  4 ++++
 arch/x86/kernel/cpu/mce/amd.c      | 35 ++++++++++++++++++++++--------
 arch/x86/kernel/cpu/mce/core.c     | 20 +++++------------
 arch/x86/kernel/cpu/mce/internal.h | 16 ++++++++++++++
 4 files changed, 52 insertions(+), 23 deletions(-)

-- 
2.17.1

[PATCH v4 1/3] x86/mce: Avoid unnecessary padding in struct mce_bank

[Smita Koralahalli]

Convert struct mce_bank member "init" from bool to a bitfield to get rid
of unnecessary padding.

Outputs collected before and after the change.

$ pahole -C mce_bank arch/x86/kernel/cpu/mce/core.o

before:

	/* size: 16, cachelines: 1, members: 2 */
	/* padding: 7 */
	/* last cacheline: 16 bytes */

after:

	/* size: 16, cachelines: 1, members: 3 */
	/* last cacheline: 16 bytes */

No functional changes.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
---
Link:
https://lkml.kernel.org/r/20220211223442.254489-5-Smita.KoralahalliChannabasappa@amd.com

v4:
	Moved this patch to the first in the series.
---
 arch/x86/kernel/cpu/mce/core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 728f3b36ce2d..c0e9aa9c8749 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -69,7 +69,9 @@ DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
 
 struct mce_bank {
 	u64			ctl;			/* subevents to enable */
-	bool			init;			/* initialise bank? */
+
+	__u64 init			: 1,		/* initialise bank? */
+	      __reserved_1		: 63;
 };
 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
 
-- 
2.17.1

[tip: ras/core] x86/mce: Avoid unnecessary padding in struct mce_bank

[tip-bot2 for Smita Koralahalli]

The following commit has been merged into the ras/core branch of tip:

Commit-ID:     9f1b19b977ee3cbd3fe9135ff63dbf221eac1d6a
Gitweb:        https://git.kernel.org/tip/9f1b19b977ee3cbd3fe9135ff63dbf221eac1d6a
Author:        Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
AuthorDate:    Fri, 25 Feb 2022 13:33:40 -06:00
Committer:     Borislav Petkov <bp@suse.de>
CommitterDate: Tue, 05 Apr 2022 21:23:34 +02:00

x86/mce: Avoid unnecessary padding in struct mce_bank

Convert struct mce_bank member "init" from bool to a bitfield to get rid
of unnecessary padding.

$ pahole -C mce_bank arch/x86/kernel/cpu/mce/core.o

before:

  /* size: 16, cachelines: 1, members: 2 */
  /* padding: 7 */
  /* last cacheline: 16 bytes */

after:

  /* size: 16, cachelines: 1, members: 3 */
  /* last cacheline: 16 bytes */

No functional changes.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Link: https://lore.kernel.org/r/20220225193342.215780-2-Smita.KoralahalliChannabasappa@amd.com
---
 arch/x86/kernel/cpu/mce/core.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 981496e..d775fcd 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -69,7 +69,9 @@ DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
 
 struct mce_bank {
 	u64			ctl;			/* subevents to enable */
-	bool			init;			/* initialise bank? */
+
+	__u64 init			: 1,		/* initialise bank? */
+	      __reserved_1		: 63;
 };
 static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
 

[PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Smita Koralahalli]

Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This
will be further refactored to support extended ErrorAddr bits in MCA_ADDR
in newer AMD processors such as AMD 'Milan'.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20220211223442.254489-2-Smita.KoralahalliChannabasappa@amd.com

v2:
	No change.
v3:
	Rebased on the latest tip tree. No functional changes.
v4:
	Commit description change to be void of the patch linearity.
---
 arch/x86/include/asm/mce.h     |  2 ++
 arch/x86/kernel/cpu/mce/amd.c  | 14 +++++++++-----
 arch/x86/kernel/cpu/mce/core.c |  7 ++-----
 3 files changed, 13 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index cc73061e7255..99a4c32cbdfa 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -337,12 +337,14 @@ extern int mce_threshold_remove_device(unsigned int cpu);
 
 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
+void smca_extract_err_addr(struct mce *m);
 #else
 
 static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
 static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
 static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
+static inline void smca_extract_err_addr(struct mce *m) { }
 #endif
 
 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 1940d305db1c..981d718851a2 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -722,6 +722,13 @@ bool amd_mce_is_memory_error(struct mce *m)
 	return m->bank == 4 && xec == 0x8;
 }
 
+void smca_extract_err_addr(struct mce *m)
+{
+	u8 lsb = (m->addr >> 56) & 0x3f;
+
+	m->addr &= GENMASK_ULL(55, lsb);
+}
+
 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 {
 	struct mce m;
@@ -740,11 +747,8 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 		 * Extract [55:<lsb>] where lsb is the least significant
 		 * *valid* bit of the address bits.
 		 */
-		if (mce_flags.smca) {
-			u8 lsb = (m.addr >> 56) & 0x3f;
-
-			m.addr &= GENMASK_ULL(55, lsb);
-		}
+		if (mce_flags.smca)
+			smca_extract_err_addr(&m);
 	}
 
 	if (mce_flags.smca) {
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index c0e9aa9c8749..313058dc129f 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -645,11 +645,8 @@ static noinstr void mce_read_aux(struct mce *m, int i)
 		 * Extract [55:<lsb>] where lsb is the least significant
 		 * *valid* bit of the address bits.
 		 */
-		if (mce_flags.smca) {
-			u8 lsb = (m->addr >> 56) & 0x3f;
-
-			m->addr &= GENMASK_ULL(55, lsb);
-		}
+		if (mce_flags.smca)
+			smca_extract_err_addr(m);
 	}
 
 	if (mce_flags.smca) {
-- 
2.17.1

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Borislav Petkov]

On Fri, Feb 25, 2022 at 01:33:41PM -0600, Smita Koralahalli wrote:
> Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This
> will be further refactored to support extended ErrorAddr bits in MCA_ADDR
> in newer AMD processors such as AMD 'Milan'.
> 
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
> ---
> Link:
> https://lkml.kernel.org/r/20220211223442.254489-2-Smita.KoralahalliChannabasappa@amd.com
> 
> v2:
> 	No change.
> v3:
> 	Rebased on the latest tip tree. No functional changes.
> v4:
> 	Commit description change to be void of the patch linearity.
> ---
>  arch/x86/include/asm/mce.h     |  2 ++
>  arch/x86/kernel/cpu/mce/amd.c  | 14 +++++++++-----
>  arch/x86/kernel/cpu/mce/core.c |  7 ++-----
>  3 files changed, 13 insertions(+), 10 deletions(-)

So if you're going to extract functionality, make sure you extract it
all and keep it all encapsulated in a single function, see below.

Now take this one pls and do your patch 3 ontop by extending the comment
over smca_extract_err_addr() with the new functionality.

Thx.

---
From: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Date: Fri, 25 Feb 2022 13:33:41 -0600
Subject: [PATCH] x86/mce: Define a function to extract ErrorAddr from MCA_ADDR

Move MCA_ADDR[ErrorAddr] extraction into a separate helper function. This
will be further refactored to support extended ErrorAddr bits in MCA_ADDR
in newer AMD CPUs.

  [ bp: Massage. ]

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
Link: https://lore.kernel.org/r/20220225193342.215780-3-Smita.KoralahalliChannabasappa@amd.com
---
 arch/x86/include/asm/mce.h     |  2 ++
 arch/x86/kernel/cpu/mce/amd.c  | 23 ++++++++++++++---------
 arch/x86/kernel/cpu/mce/core.c | 11 +----------
 3 files changed, 17 insertions(+), 19 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index cc73061e7255..a1da72941f4e 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -337,12 +337,14 @@ extern int mce_threshold_remove_device(unsigned int cpu);
 
 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
+void smca_extract_err_addr(struct mce *m);
 #else
 
 static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
 static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
 static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
+static inline void smca_extract_err_addr(struct mce *m)			{ }
 #endif
 
 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 1940d305db1c..a1a4a5dc53e8 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -722,6 +722,19 @@ bool amd_mce_is_memory_error(struct mce *m)
 	return m->bank == 4 && xec == 0x8;
 }
 
+/* Extract [55:<lsb>] where lsb is the LS-*valid* bit of the address bits. */
+void smca_extract_err_addr(struct mce *m)
+{
+	u8 lsb;
+
+	if (!mce_flags.smca)
+		return;
+
+	lsb = (m->addr >> 56) & 0x3f;
+
+	m->addr &= GENMASK_ULL(55, lsb);
+}
+
 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 {
 	struct mce m;
@@ -736,15 +749,7 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 	if (m.status & MCI_STATUS_ADDRV) {
 		m.addr = addr;
 
-		/*
-		 * Extract [55:<lsb>] where lsb is the least significant
-		 * *valid* bit of the address bits.
-		 */
-		if (mce_flags.smca) {
-			u8 lsb = (m.addr >> 56) & 0x3f;
-
-			m.addr &= GENMASK_ULL(55, lsb);
-		}
+		smca_extract_err_addr(&m);
 	}
 
 	if (mce_flags.smca) {
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index d775fcd74e98..5ba2df911d19 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -632,16 +632,7 @@ static noinstr void mce_read_aux(struct mce *m, int i)
 			m->addr >>= shift;
 			m->addr <<= shift;
 		}
-
-		/*
-		 * Extract [55:<lsb>] where lsb is the least significant
-		 * *valid* bit of the address bits.
-		 */
-		if (mce_flags.smca) {
-			u8 lsb = (m->addr >> 56) & 0x3f;
-
-			m->addr &= GENMASK_ULL(55, lsb);
-		}
+		smca_extract_err_addr(m);
 	}
 
 	if (mce_flags.smca) {
-- 
2.35.1

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Borislav Petkov]

On Thu, Mar 31, 2022 at 03:24:37PM +0200, Borislav Petkov wrote:
> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
> index 1940d305db1c..a1a4a5dc53e8 100644
> --- a/arch/x86/kernel/cpu/mce/amd.c
> +++ b/arch/x86/kernel/cpu/mce/amd.c
> @@ -722,6 +722,19 @@ bool amd_mce_is_memory_error(struct mce *m)
>  	return m->bank == 4 && xec == 0x8;
>  }
>  
> +/* Extract [55:<lsb>] where lsb is the LS-*valid* bit of the address bits. */
> +void smca_extract_err_addr(struct mce *m)

In addition:

diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 9ccc2ea0ea00..4acc7959be6e 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -723,7 +723,7 @@ bool amd_mce_is_memory_error(struct mce *m)
 }
 
 /* Extract [55:<lsb>] where lsb is the LS-*valid* bit of the address bits. */
-void smca_extract_err_addr(struct mce *m)
+void __always_inline smca_extract_err_addr(struct mce *m)
 {
 	u8 lsb;
 

because some compilers cause:

vmlinux.o: warning: objtool: mce_read_aux()+0x82: call to smca_extract_err_addr() leaves .noinstr.text section

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Borislav Petkov]

On Sun, Apr 03, 2022 at 03:16:20PM +0200, Borislav Petkov wrote:
> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
> index 9ccc2ea0ea00..4acc7959be6e 100644
> --- a/arch/x86/kernel/cpu/mce/amd.c
> +++ b/arch/x86/kernel/cpu/mce/amd.c
> @@ -723,7 +723,7 @@ bool amd_mce_is_memory_error(struct mce *m)
>  }
>  
>  /* Extract [55:<lsb>] where lsb is the LS-*valid* bit of the address bits. */
> -void smca_extract_err_addr(struct mce *m)
> +void __always_inline smca_extract_err_addr(struct mce *m)

Ok, flip those - the pedantic bot is not happy:

>> arch/x86/kernel/cpu/mce/amd.c:726:1: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration]
     726 | void __always_inline smca_extract_err_addr(struct mce *m)
         | ^~~~

Needs to be

__always_inline void

whateva...

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Thomas Gleixner]

On Sun, Apr 03 2022 at 20:50, Borislav Petkov wrote:
> On Sun, Apr 03, 2022 at 03:16:20PM +0200, Borislav Petkov wrote:
>> diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
>> index 9ccc2ea0ea00..4acc7959be6e 100644
>> --- a/arch/x86/kernel/cpu/mce/amd.c
>> +++ b/arch/x86/kernel/cpu/mce/amd.c
>> @@ -723,7 +723,7 @@ bool amd_mce_is_memory_error(struct mce *m)
>>  }
>>  
>>  /* Extract [55:<lsb>] where lsb is the LS-*valid* bit of the address bits. */
>> -void smca_extract_err_addr(struct mce *m)
>> +void __always_inline smca_extract_err_addr(struct mce *m)
>
> Ok, flip those - the pedantic bot is not happy:
>
>>> arch/x86/kernel/cpu/mce/amd.c:726:1: warning: 'inline' is not at beginning of declaration [-Wold-style-declaration]
>      726 | void __always_inline smca_extract_err_addr(struct mce *m)
>          | ^~~~
>
> Needs to be
>
> __always_inline void
>
> whateva...

How is __always_inline supposed to work across compilation units w/o
LTO? The callsite is in core.c ...

Thanks,

        tglx

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Borislav Petkov]

On Sun, Apr 03, 2022 at 09:58:07PM +0200, Thomas Gleixner wrote:
> How is __always_inline supposed to work across compilation units w/o
> LTO? The callsite is in core.c ...

Hmm, right.

So even with patch 3 adding more changes to that function I think it is
still simple enough so that we can move it up into the mce/internal.h
header so that the inlining can work.

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Smita Koralahalli]

On 4/3/2022 1:44 PM, Borislav Petkov wrote:
> On Sun, Apr 03, 2022 at 09:58:07PM +0200, Thomas Gleixner wrote:
>> How is __always_inline supposed to work across compilation units w/o
>> LTO? The callsite is in core.c ...
> Hmm, right.
>
> So even with patch 3 adding more changes to that function I think it is
> still simple enough so that we can move it up into the mce/internal.h
> header so that the inlining can work.
Ok will incorporate all changes.

I didn't quite understand what needs to be moved to mce/internal.h. Was that
addressed to me?  The function call smca_extract_err_addr() is in mce/core.c
and the definition in mce.h
>
> Thx.
>

Re: [PATCH v4 2/3] x86/mce: Define function to extract ErrorAddr from MCA_ADDR

[Borislav Petkov]

On Mon, Apr 04, 2022 at 01:55:21PM -0700, Smita Koralahalli wrote:
> I didn't quite understand what needs to be moved to mce/internal.h. Was that
> addressed to me?  The function call smca_extract_err_addr() is in mce/core.c
> and the definition in mce.h

In your current v4, the function definition is in
arch/x86/kernel/cpu/mce/amd.c

However, since it needs to be inlined into both callsites because
mce_read_aux() is marked noinstr, the definition should be

static __always_inline void smca_extract_err_addr(struct mce *m)

and that definition should be in the header mce/internal.h

Thx.

-- 
Regards/Gruss,
    Boris.

https://people.kernel.org/tglx/notes-about-netiquette

[PATCH v4 3/3] x86/mce: Add support for Extended Physical Address MCA changes

[Smita Koralahalli]

Newer AMD processors such as AMD 'Milan' support more physical address
bits.

That is the MCA_ADDR registers on Scalable MCA systems contain the
ErrorAddr in bits [56:0] instead of [55:0]. Hence the existing LSB field
from bits [61:56] in MCA_ADDR must be moved around to accommodate the
larger ErrorAddr size.

MCA_CONFIG[McaLsbInStatusSupported] indicates this change. If set, the
LSB field will be found in MCA_STATUS rather than MCA_ADDR.

Each logical CPU has unique MCA bank in hardware and is not shared with
other logical CPUs. Additionally on SMCA systems, each feature bit may be
different for each bank within same logical CPU.

Check for MCA_CONFIG[McaLsbInStatusSupported] for each MCA bank and for
each CPU.

Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20220211223442.254489-3-Smita.KoralahalliChannabasappa@amd.com

v2:
	Declared lsb_in_status in existing mce_bank[] struct.
	Moved struct mce_bank[] declaration from core.c -> internal.h
v3:
	Rebased on the latest tip tree. No functional changes.
v4:
	No change.
---
 arch/x86/include/asm/mce.h         |  2 ++
 arch/x86/kernel/cpu/mce/amd.c      | 25 +++++++++++++++++++------
 arch/x86/kernel/cpu/mce/core.c     | 15 ++++-----------
 arch/x86/kernel/cpu/mce/internal.h | 16 ++++++++++++++++
 4 files changed, 41 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 99a4c32cbdfa..cc67c74e8b46 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -338,6 +338,7 @@ extern int mce_threshold_remove_device(unsigned int cpu);
 void mce_amd_feature_init(struct cpuinfo_x86 *c);
 enum smca_bank_types smca_get_bank_type(unsigned int cpu, unsigned int bank);
 void smca_extract_err_addr(struct mce *m);
+void smca_feature_init(void);
 #else
 
 static inline int mce_threshold_create_device(unsigned int cpu)		{ return 0; };
@@ -345,6 +346,7 @@ static inline int mce_threshold_remove_device(unsigned int cpu)		{ return 0; };
 static inline bool amd_mce_is_memory_error(struct mce *m)		{ return false; };
 static inline void mce_amd_feature_init(struct cpuinfo_x86 *c)		{ }
 static inline void smca_extract_err_addr(struct mce *m) { }
+static inline void smca_feature_init(void) { }
 #endif
 
 static inline void mce_hygon_feature_init(struct cpuinfo_x86 *c)	{ return mce_amd_feature_init(c); }
diff --git a/arch/x86/kernel/cpu/mce/amd.c b/arch/x86/kernel/cpu/mce/amd.c
index 981d718851a2..ed75d4bd2aff 100644
--- a/arch/x86/kernel/cpu/mce/amd.c
+++ b/arch/x86/kernel/cpu/mce/amd.c
@@ -724,9 +724,26 @@ bool amd_mce_is_memory_error(struct mce *m)
 
 void smca_extract_err_addr(struct mce *m)
 {
-	u8 lsb = (m->addr >> 56) & 0x3f;
+	if (this_cpu_ptr(mce_banks_array)[m->bank].lsb_in_status) {
+		u8 lsb = (m->status >> 24) & 0x3f;
 
-	m->addr &= GENMASK_ULL(55, lsb);
+		m->addr &= GENMASK_ULL(56, lsb);
+	} else {
+		u8 lsb = (m->addr >> 56) & 0x3f;
+
+		m->addr &= GENMASK_ULL(55, lsb);
+	}
+}
+
+void smca_feature_init(void)
+{
+	unsigned int bank;
+	u64 mca_cfg;
+
+	for (bank = 0; bank < this_cpu_read(mce_num_banks); ++bank) {
+		rdmsrl(MSR_AMD64_SMCA_MCx_CONFIG(bank), mca_cfg);
+		this_cpu_ptr(mce_banks_array)[bank].lsb_in_status = !!(mca_cfg & BIT(8));
+	}
 }
 
 static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
@@ -743,10 +760,6 @@ static void __log_error(unsigned int bank, u64 status, u64 addr, u64 misc)
 	if (m.status & MCI_STATUS_ADDRV) {
 		m.addr = addr;
 
-		/*
-		 * Extract [55:<lsb>] where lsb is the least significant
-		 * *valid* bit of the address bits.
-		 */
 		if (mce_flags.smca)
 			smca_extract_err_addr(&m);
 	}
diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 313058dc129f..5cf753493d77 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -67,13 +67,7 @@ DEFINE_PER_CPU(unsigned, mce_exception_count);
 
 DEFINE_PER_CPU_READ_MOSTLY(unsigned int, mce_num_banks);
 
-struct mce_bank {
-	u64			ctl;			/* subevents to enable */
-
-	__u64 init			: 1,		/* initialise bank? */
-	      __reserved_1		: 63;
-};
-static DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
+DEFINE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
 
 #define ATTR_LEN               16
 /* One object for each MCE bank, shared by all CPUs */
@@ -641,10 +635,6 @@ static noinstr void mce_read_aux(struct mce *m, int i)
 			m->addr <<= shift;
 		}
 
-		/*
-		 * Extract [55:<lsb>] where lsb is the least significant
-		 * *valid* bit of the address bits.
-		 */
 		if (mce_flags.smca)
 			smca_extract_err_addr(m);
 	}
@@ -1948,6 +1938,9 @@ static void __mcheck_cpu_init_early(struct cpuinfo_x86 *c)
 		mce_flags.succor	 = !!cpu_has(c, X86_FEATURE_SUCCOR);
 		mce_flags.smca		 = !!cpu_has(c, X86_FEATURE_SMCA);
 		mce_flags.amd_threshold	 = 1;
+
+		if (mce_flags.smca)
+			smca_feature_init();
 	}
 }
 
diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h
index 3efb5037c364..0b12fe528e1b 100644
--- a/arch/x86/kernel/cpu/mce/internal.h
+++ b/arch/x86/kernel/cpu/mce/internal.h
@@ -178,6 +178,22 @@ struct mce_vendor_flags {
 
 extern struct mce_vendor_flags mce_flags;
 
+struct mce_bank {
+	u64			ctl;			/* subevents to enable */
+
+	__u64 init			: 1,		/* initialise bank? */
+
+	/*
+	 * (AMD) MCA_CONFIG[McaLsbInStatusSupported]: This bit indicates
+	 * the LSB field is found in MCA_STATUS, when set.
+	 */
+	      lsb_in_status		: 1,
+
+	      __reserved_1		: 62;
+};
+
+DECLARE_PER_CPU_READ_MOSTLY(struct mce_bank[MAX_NR_BANKS], mce_banks_array);
+
 enum mca_msr {
 	MCA_CTL,
 	MCA_STATUS,
-- 
2.17.1

Re: [PATCH v4 0/3] x86/mce: Support extended MCA_ADDR address on SMCA systems

[Koralahalli Channabasappa, Smita]

Hi all,

Do you have any comments that needs to be addressed on these set of patches?

Thanks,
Smita

On 2/25/22 1:33 PM, Smita Koralahalli wrote:

> This series of patches adds support for extended physical address on newer
> AMD processors such as AMD 'Milan'.
>
> The first patch provides a fix to avoid unnecessary padding in mce_bank
> struct.
>
> The second patch defines a separate helper function to extract
> MCA_ADDR[ErrorAddr].
>
> Finally, the last patch adds support for extended ErrorAddr bits in
> MCA_ADDR.
>
> Link:
> https://lkml.kernel.org/r/20220211223442.254489-1-Smita.KoralahalliChannabasappa@amd.com
>
> Smita Koralahalli (3):
>    x86/mce: Avoid unnecessary padding in struct mce_bank
>    x86/mce: Define function to extract ErrorAddr from MCA_ADDR
>    x86/mce: Add support for Extended Physical Address MCA changes
>
>   arch/x86/include/asm/mce.h         |  4 ++++
>   arch/x86/kernel/cpu/mce/amd.c      | 35 ++++++++++++++++++++++--------
>   arch/x86/kernel/cpu/mce/core.c     | 20 +++++------------
>   arch/x86/kernel/cpu/mce/internal.h | 16 ++++++++++++++
>   4 files changed, 52 insertions(+), 23 deletions(-)
>