From: Tim Chang <jia-wei.chang@mediatek.com>
To: "Rafael J . Wysocki" <rafael@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Liam Girdwood <lgirdwood@gmail.com>,
Mark Brown <broonie@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Jia-Wei Chang <jia-wei.chang@mediatek.com>
Cc: <linux-pm@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <fan.chen@mediatek.com>,
<louis.yu@mediatek.com>, <roger.lu@mediatek.com>,
<Allen-yy.Lin@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
<hsinyi@google.com>,
Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
Subject: [PATCH 1/4] dt-bindings: cpufreq: mediatek: transform cpufreq-mediatek into yaml
Date: Mon, 7 Mar 2022 20:21:48 +0800 [thread overview]
Message-ID: <20220307122151.11666-2-jia-wei.chang@mediatek.com> (raw)
In-Reply-To: <20220307122151.11666-1-jia-wei.chang@mediatek.com>
convert Mediatek cpufreq devicetree binding to YAML.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.corp-partner.google.com>
---
.../bindings/cpufreq/cpufreq-mediatek.yaml | 131 ++++++++++++++++++
1 file changed, 131 insertions(+)
create mode 100644 Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
new file mode 100644
index 000000000000..584946eb3790
--- /dev/null
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-mediatek.yaml
@@ -0,0 +1,131 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cpufreq/cpufreq-mediatek.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek CPUFREQ driver Device Tree Bindings
+
+maintainers:
+ - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+
+description: |
+ CPUFREQ is used for scaling clock frequency of CPUs.
+ The module cooperates with CCI DEVFREQ to manage frequency for some Mediatek
+ SoCs.
+
+properties:
+ clocks:
+ items:
+ - description:
+ The first one is the multiplexer for clock input of CPU cluster.
+ - description:
+ The other is used as an intermediate clock source when the original
+ CPU is under transition and not stable yet.
+
+ clock-names:
+ items:
+ - const: "cpu"
+ - const: "intermediate"
+
+ operating-points-v2:
+ description:
+ For details, please refer to
+ Documentation/devicetree/bindings/opp/opp-v2.yaml
+
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator for CPU cluster that provides the supply
+ voltage.
+
+ sram-supply:
+ description:
+ Phandle of the regulator for sram of CPU cluster that provides the supply
+ voltage. When present, the cpufreq driver needs to do "voltage tracking"
+ to step by step scale up/down Vproc and Vsram to fit SoC specific needs.
+ When absent, the voltage scaling flow is handled by hardware, hence no
+ software "voltage tracking" is needed.
+
+ "#cooling-cells":
+ description:
+ For details, please refer to
+ Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml
+
+required:
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - proc-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ /* Example 1 (MT7623 SoC) */
+ #include <dt-bindings/clock/mt2701-clk.h>
+ cpu_opp_table: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-598000000 {
+ opp-hz = /bits/ 64 <598000000>;
+ opp-microvolt = <1050000>;
+ };
+
+ /* ... */
+
+ };
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x0>;
+ clocks = <&infracfg CLK_INFRA_CPUSEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cpu_opp_table>;
+ proc-supply = <&mt6380_vcpu_reg>;
+ #cooling-cells = <2>;
+ };
+
+ /* ... */
+
+ };
+
+ - |
+ /* Example 2 (MT8173 SoC) */
+ #include <dt-bindings/clock/mt8173-clk.h>
+ cluster1_opp: opp-table-1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp-507000000 {
+ opp-hz = /bits/ 64 <507000000>;
+ opp-microvolt = <828000>;
+ };
+
+ /* ... */
+
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a72";
+ reg = <0x100>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0>;
+ #cooling-cells = <2>;
+ clocks = <&infracfg CLK_INFRA_CA72SEL>, <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
+ proc-supply = <&mt6397_vpca15_reg>;
+ };
+
+ /* ... */
+
+ };
--
2.18.0
next prev parent reply other threads:[~2022-03-07 12:22 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-07 12:21 [PATCH 0/4] cpufreq: mediatek: introduce mtk cpufreq Tim Chang
2022-03-07 12:21 ` Tim Chang [this message]
2022-03-07 18:57 ` [PATCH 1/4] dt-bindings: cpufreq: mediatek: transform cpufreq-mediatek into yaml Krzysztof Kozlowski
2022-03-24 9:38 ` Jia-Wei Chang
2022-03-24 10:33 ` Krzysztof Kozlowski
2022-04-01 13:26 ` Jia-Wei Chang
2022-04-01 16:32 ` Krzysztof Kozlowski
2022-04-06 8:42 ` Jia-Wei Chang
2022-04-08 3:14 ` Rex-BC Chen
2022-03-07 12:21 ` [PATCH 2/4] dt-bindings: cpufreq: mediatek: add mt8186 cpufreq dt-bindings Tim Chang
2022-03-07 18:59 ` Krzysztof Kozlowski
2022-03-24 9:42 ` Jia-Wei Chang
2022-03-24 10:35 ` Krzysztof Kozlowski
2022-04-01 13:32 ` Jia-Wei Chang
2022-03-10 20:44 ` Rob Herring
2022-04-06 12:49 ` Jia-Wei Chang
2022-03-07 12:21 ` [PATCH 3/4] cpufreq: mediatek: clean up cpufreq driver Tim Chang
2022-03-07 19:02 ` Krzysztof Kozlowski
2022-03-24 9:47 ` Jia-Wei Chang
2022-03-08 4:40 ` Viresh Kumar
2022-03-07 12:21 ` [PATCH 4/4] cpufreq: mediatek: add platform data and clean up voltage tracking logic Tim Chang
2022-03-07 19:03 ` Krzysztof Kozlowski
2022-03-24 9:49 ` Jia-Wei Chang
2022-03-08 4:36 ` [PATCH 0/4] cpufreq: mediatek: introduce mtk cpufreq Viresh Kumar
2022-04-08 3:55 ` Rex-BC Chen
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