From: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: linux-kernel@vger.kernel.org
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
stable@vger.kernel.org, Joey Gouly <joey.gouly@arm.com>,
Will Deacon <will@kernel.org>, Marc Zyngier <maz@kernel.org>,
James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Reiji Watanabe <reijiw@google.com>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: [PATCH 5.16 14/37] arm64: add ID_AA64ISAR2_EL1 sys register
Date: Wed, 9 Mar 2022 17:00:15 +0100 [thread overview]
Message-ID: <20220309155859.503049666@linuxfoundation.org> (raw)
In-Reply-To: <20220309155859.086952723@linuxfoundation.org>
From: Joey Gouly <joey.gouly@arm.com>
commit 9e45365f1469ef2b934f9d035975dbc9ad352116 upstream.
This is a new ID register, introduced in 8.7.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Reiji Watanabe <reijiw@google.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
---
arch/arm64/include/asm/cpu.h | 1 +
arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++
arch/arm64/kernel/cpufeature.c | 9 +++++++++
arch/arm64/kernel/cpuinfo.c | 1 +
arch/arm64/kvm/sys_regs.c | 2 +-
5 files changed, 27 insertions(+), 1 deletion(-)
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -51,6 +51,7 @@ struct cpuinfo_arm64 {
u64 reg_id_aa64dfr1;
u64 reg_id_aa64isar0;
u64 reg_id_aa64isar1;
+ u64 reg_id_aa64isar2;
u64 reg_id_aa64mmfr0;
u64 reg_id_aa64mmfr1;
u64 reg_id_aa64mmfr2;
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -182,6 +182,7 @@
#define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
#define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
+#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)
#define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
#define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
@@ -771,6 +772,20 @@
#define ID_AA64ISAR1_GPI_NI 0x0
#define ID_AA64ISAR1_GPI_IMP_DEF 0x1
+/* id_aa64isar2 */
+#define ID_AA64ISAR2_RPRES_SHIFT 4
+#define ID_AA64ISAR2_WFXT_SHIFT 0
+
+#define ID_AA64ISAR2_RPRES_8BIT 0x0
+#define ID_AA64ISAR2_RPRES_12BIT 0x1
+/*
+ * Value 0x1 has been removed from the architecture, and is
+ * reserved, but has not yet been removed from the ARM ARM
+ * as of ARM DDI 0487G.b.
+ */
+#define ID_AA64ISAR2_WFXT_NI 0x0
+#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
+
/* id_aa64pfr0 */
#define ID_AA64PFR0_CSV3_SHIFT 60
#define ID_AA64PFR0_CSV2_SHIFT 56
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_i
ARM64_FTR_END,
};
+static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
+ ARM64_FTR_END,
+};
+
static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
@@ -637,6 +641,7 @@ static const struct __ftr_reg_entry {
ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
&id_aa64isar1_override),
+ ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),
/* Op1 = 0, CRn = 0, CRm = 7 */
ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
@@ -933,6 +938,7 @@ void __init init_cpu_features(struct cpu
init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
+ init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
@@ -1151,6 +1157,8 @@ void update_cpu_features(int cpu,
info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
+ taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
+ info->reg_id_aa64isar2, boot->reg_id_aa64isar2);
/*
* Differing PARange support is fine as long as all peripherals and
@@ -1272,6 +1280,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id
read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
+ read_sysreg_case(SYS_ID_AA64ISAR2_EL1);
read_sysreg_case(SYS_CNTFRQ_EL0);
read_sysreg_case(SYS_CTR_EL0);
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -391,6 +391,7 @@ static void __cpuinfo_store_cpu(struct c
info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
+ info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -1525,7 +1525,7 @@ static const struct sys_reg_desc sys_reg
/* CRm=6 */
ID_SANITISED(ID_AA64ISAR0_EL1),
ID_SANITISED(ID_AA64ISAR1_EL1),
- ID_UNALLOCATED(6,2),
+ ID_SANITISED(ID_AA64ISAR2_EL1),
ID_UNALLOCATED(6,3),
ID_UNALLOCATED(6,4),
ID_UNALLOCATED(6,5),
next prev parent reply other threads:[~2022-03-09 16:21 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-09 16:00 [PATCH 5.16 00/37] 5.16.14-rc1 review Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 01/37] x86/speculation: Rename RETPOLINE_AMD to RETPOLINE_LFENCE Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 02/37] x86/speculation: Add eIBRS + Retpoline options Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 03/37] Documentation/hw-vuln: Update spectre doc Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 04/37] x86/speculation: Include unprivileged eBPF status in Spectre v2 mitigation reporting Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 05/37] x86/speculation: Use generic retpoline by default on AMD Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 06/37] x86/speculation: Update link to AMD speculation whitepaper Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 07/37] x86/speculation: Warn about Spectre v2 LFENCE mitigation Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 08/37] x86/speculation: Warn about eIBRS + LFENCE + Unprivileged eBPF + SMT Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 09/37] ARM: report Spectre v2 status through sysfs Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 10/37] ARM: early traps initialisation Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 11/37] ARM: use LOADADDR() to get load address of sections Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 12/37] ARM: Spectre-BHB workaround Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 13/37] ARM: include unprivileged BPF status in Spectre V2 reporting Greg Kroah-Hartman
2022-03-09 16:00 ` Greg Kroah-Hartman [this message]
2022-03-09 16:00 ` [PATCH 5.16 15/37] arm64: cpufeature: add HWCAP for FEAT_AFP Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 16/37] arm64: cpufeature: add HWCAP for FEAT_RPRES Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 17/37] arm64: entry.S: Add ventry overflow sanity checks Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 18/37] arm64: spectre: Rename spectre_v4_patch_fw_mitigation_conduit Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 19/37] KVM: arm64: Allow indirect vectors to be used without SPECTRE_V3A Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 20/37] arm64: entry: Make the trampoline cleanup optional Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 21/37] arm64: entry: Free up another register on kptis tramp_exit path Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 22/37] arm64: entry: Move the trampoline data page before the text page Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 23/37] arm64: entry: Allow tramp_alias to access symbols after the 4K boundary Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 24/37] arm64: entry: Dont assume tramp_vectors is the start of the vectors Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 25/37] arm64: entry: Move trampoline macros out of ifdefd section Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 26/37] arm64: entry: Make the kpti trampolines kpti sequence optional Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 27/37] arm64: entry: Allow the trampoline text to occupy multiple pages Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 28/37] arm64: entry: Add non-kpti __bp_harden_el1_vectors for mitigations Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 29/37] arm64: entry: Add vectors that have the bhb mitigation sequences Greg Kroah-Hartman
2022-03-10 23:27 ` Pavel Machek
2022-03-11 8:15 ` Greg Kroah-Hartman
2022-03-11 8:39 ` Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 30/37] arm64: entry: Add macro for reading symbol addresses from the trampoline Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 31/37] arm64: Add percpu vectors for EL1 Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 32/37] arm64: proton-pack: Report Spectre-BHB vulnerabilities as part of Spectre-v2 Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 33/37] arm64: Mitigate spectre style branch history side channels Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 34/37] KVM: arm64: Allow SMCCC_ARCH_WORKAROUND_3 to be discovered and migrated Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 35/37] arm64: Use the clearbhb instruction in mitigations Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 36/37] arm64: proton-pack: Include unprivileged eBPF status in Spectre v2 mitigation reporting Greg Kroah-Hartman
2022-03-09 16:00 ` [PATCH 5.16 37/37] ARM: fix build error when BPF_SYSCALL is disabled Greg Kroah-Hartman
2022-03-09 19:05 ` [PATCH 5.16 00/37] 5.16.14-rc1 review Guenter Roeck
2022-03-09 20:01 ` Greg Kroah-Hartman
2022-03-09 21:17 ` Greg Kroah-Hartman
2022-03-09 20:23 ` Shuah Khan
2022-03-09 21:17 ` Daniel Díaz
2022-03-09 21:19 ` Daniel Díaz
2022-03-09 21:49 ` Fox Chen
2022-03-10 10:50 ` Bagas Sanjaya
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