From: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Cc: <Project_Global_Chrome_Upstream_Group@mediatek.com>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
"Chen-Yu Tsai" <wenst@chromium.org>,
Ryder Lee <ryder.lee@kernel.org>, Hui Liu <hui.liu@mediatek.com>,
Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Subject: [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes
Date: Fri, 18 Mar 2022 22:45:26 +0800 [thread overview]
Message-ID: <20220318144534.17996-15-allen-kh.cheng@mediatek.com> (raw)
In-Reply-To: <20220318144534.17996-1-allen-kh.cheng@mediatek.com>
Add m4u and smi nodes for mt8192 SoC
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 190 +++++++++++++++++++++++
1 file changed, 190 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 6b769fa5b427..4addf6ddd86d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/gce/mt8192-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8192-larb-port.h>
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt8192-power.h>
@@ -1204,24 +1205,114 @@
#clock-cells = <1>;
};
+ smi_common: smi@14002000 {
+ compatible = "mediatek,mt8192-smi-common";
+ reg = <0 0x14002000 0 0x1000>;
+ clocks = <&mmsys CLK_MM_SMI_COMMON>,
+ <&mmsys CLK_MM_SMI_INFRA>,
+ <&mmsys CLK_MM_SMI_GALS>,
+ <&mmsys CLK_MM_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb0: larb@14003000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ larb1: larb@14004000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ };
+
+ iommu0: m4u@1401d000 {
+ compatible = "mediatek,mt8192-m4u";
+ reg = <0 0x1401d000 0 0x1000>;
+ mediatek,larbs = <&larb0>, <&larb1>, <&larb2>,
+ <&larb4>, <&larb5>, <&larb7>,
+ <&larb9>, <&larb11>, <&larb13>,
+ <&larb14>, <&larb16>, <&larb17>,
+ <&larb18>, <&larb19>, <&larb20>;
+ interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&mmsys CLK_MM_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8192_POWER_DOMAIN_DISP>;
+ #iommu-cells = <1>;
+ };
+
imgsys: clock-controller@15020000 {
compatible = "mediatek,mt8192-imgsys";
reg = <0 0x15020000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@1502e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1502e000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP>;
+ };
+
imgsys2: clock-controller@15820000 {
compatible = "mediatek,mt8192-imgsys2";
reg = <0 0x15820000 0 0x1000>;
#clock-cells = <1>;
};
+ larb11: larb@1582e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1582e000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&imgsys2 CLK_IMG2_LARB11>,
+ <&imgsys2 CLK_IMG2_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
+ };
+
+ larb5: larb@1600d000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1600d000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
vdecsys_soc: clock-controller@1600f000 {
compatible = "mediatek,mt8192-vdecsys_soc";
reg = <0 0x1600f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb4: larb@1602e000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1602e000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vdecsys CLK_VDEC_SOC_LARB1>,
+ <&vdecsys CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys: clock-controller@1602f000 {
compatible = "mediatek,mt8192-vdecsys";
reg = <0 0x1602f000 0 0x1000>;
@@ -1234,12 +1325,78 @@
#clock-cells = <1>;
};
+ larb7: larb@17010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x17010000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&vencsys CLK_VENC_SET0_LARB>,
+ <&vencsys CLK_VENC_SET1_VENC>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_VENC>;
+ };
+
camsys: clock-controller@1a000000 {
compatible = "mediatek,mt8192-camsys";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@1a001000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB13>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@1a002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@1a00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a00f000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_CAM>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@1a010000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_CAM>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb18: larb@1a011000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1a011000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&camsys_rawc CLK_CAM_RAWC_LARBX>,
+ <&camsys_rawc CLK_CAM_RAWC_CAM>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_CAM_RAWC>;
+ };
+
camsys_rawa: clock-controller@1a04f000 {
compatible = "mediatek,mt8192-camsys_rawa";
reg = <0 0x1a04f000 0 0x1000>;
@@ -1264,10 +1421,43 @@
#clock-cells = <1>;
};
+ larb20: larb@1b00f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b00f000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB20>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
+ larb19: larb@1b10f000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1b10f000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&ipesys CLK_IPE_SMI_SUBCOM>,
+ <&ipesys CLK_IPE_LARB19>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_IPE>;
+ };
+
mdpsys: clock-controller@1f000000 {
compatible = "mediatek,mt8192-mdpsys";
reg = <0 0x1f000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ larb2: larb@1f002000 {
+ compatible = "mediatek,mt8192-smi-larb";
+ reg = <0 0x1f002000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common>;
+ clocks = <&mdpsys CLK_MDP_SMI0>,
+ <&mdpsys CLK_MDP_SMI0>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8192_POWER_DOMAIN_MDP>;
+ };
};
};
--
2.18.0
next prev parent reply other threads:[~2022-03-18 14:48 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-18 14:45 [PATCH v4 00/22] Add driver nodes for MT8192 SoC Allen-KH Cheng
2022-03-18 14:45 ` [PATCH v4 01/22] arm64: dts: mt8192: Add pwrap node Allen-KH Cheng
2022-03-23 17:15 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 02/22] arm64: dts: mt8192: Add spmi node Allen-KH Cheng
2022-03-23 17:16 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 03/22] arm64: dts: mt8192: Add gce node Allen-KH Cheng
2022-03-23 17:24 ` Matthias Brugger
2022-03-29 20:11 ` Nícolas F. R. A. Prado
2022-03-18 14:45 ` [PATCH v4 04/22] arm64: dts: mt8192: Add SCP node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-22 20:28 ` Nícolas F. R. A. Prado
2022-03-23 17:26 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 05/22] arm64: dts: mt8192: Add usb-phy node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-21 22:22 ` Nícolas F. R. A. Prado
2022-03-24 12:28 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 06/22] arm64: dts: mt8192: Add xhci node Allen-KH Cheng
2022-03-21 22:26 ` Nícolas F. R. A. Prado
2022-03-24 13:45 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 07/22] arm64: dts: mt8192: Add audio-related nodes Allen-KH Cheng
2022-03-24 14:45 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 08/22] arm64: dts: mt8192: Add infracfg_rst node Allen-KH Cheng
2022-03-22 21:57 ` Nícolas F. R. A. Prado
[not found] ` <17bc30c64db3f3280993669a39edf3a11f76fb68.camel@mediatek.com>
2022-03-24 13:57 ` Nícolas F. R. A. Prado
2022-03-18 14:45 ` [PATCH v4 09/22] arm64: dts: mt8192: Add PCIe node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-22 22:18 ` Nícolas F. R. A. Prado
2022-03-24 17:44 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 10/22] arm64: dts: mt8192: Fix nor_flash status disable typo Allen-KH Cheng
2022-03-18 23:52 ` Miles Chen
2022-03-21 22:30 ` Nícolas F. R. A. Prado
2022-03-24 17:45 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 11/22] arm64: dts: mt8192: Add efuse node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-22 15:10 ` Nícolas F. R. A. Prado
2022-03-24 17:46 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 12/22] arm64: dts: mt8192: Add mmc device nodes Allen-KH Cheng
2022-03-22 14:34 ` Nícolas F. R. A. Prado
2022-03-24 17:53 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 13/22] arm64: dts: mt8192: Add mipi_tx node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-21 22:41 ` Nícolas F. R. A. Prado
2022-03-18 14:45 ` Allen-KH Cheng [this message]
2022-03-25 10:58 ` [PATCH v4 14/22] arm64: dts: mt8192: Add m4u and smi nodes Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 15/22] arm64: dts: mt8192: Add H264 venc device node Allen-KH Cheng
2022-03-25 11:01 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 16/22] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-25 15:22 ` Matthias Brugger
[not found] ` <af19b42faf9a510578e48d6f497e7d2069327195.camel@mediatek.com>
2022-03-29 9:58 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 17/22] arm64: dts: mt8192: Add dpi node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-25 15:24 ` Matthias Brugger
[not found] ` <e4edbb8d599fe202aa89f4dea88e6addfbeb4e0d.camel@mediatek.com>
2022-03-29 10:01 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 18/22] arm64: dts: mt8192: Add display nodes Allen-KH Cheng
2022-03-21 23:26 ` Nícolas F. R. A. Prado
[not found] ` <28c6f778b312b53ec22aec536dadfb3d7d85c35e.camel@mediatek.com>
2022-03-22 14:19 ` Nícolas F. R. A. Prado
2022-03-25 15:47 ` Matthias Brugger
2022-03-28 10:04 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 19/22] arm64: dts: mt8192: Add the mmsys reset bit to reset the dsi0 Allen-KH Cheng
2022-03-21 23:38 ` Rob Herring
2022-03-22 20:16 ` Nícolas F. R. A. Prado
2022-03-25 13:55 ` AngeloGioacchino Del Regno
2022-03-28 10:57 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 20/22] arm64: dts: mt8192: Add dsi node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-22 20:13 ` Nícolas F. R. A. Prado
2022-03-28 11:01 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 21/22] arm64: dts: mt8192: Add gce info for display nodes Allen-KH Cheng
2022-03-22 21:25 ` Nícolas F. R. A. Prado
2022-03-25 13:56 ` AngeloGioacchino Del Regno
2022-03-28 11:06 ` Matthias Brugger
2022-03-18 14:45 ` [PATCH v4 22/22] arm64: dts: mt8192: Add pwm node Allen-KH Cheng
2022-03-21 12:04 ` AngeloGioacchino Del Regno
2022-03-21 22:18 ` Nícolas F. R. A. Prado
2022-03-28 11:10 ` Matthias Brugger
[not found] ` <6ab86a35394879cf35fd9d780f8b7ab1695c931b.camel@mediatek.com>
2022-03-29 10:03 ` Matthias Brugger
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