* [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths.
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-14 14:20 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 02/10] Coresight: Add coresight TPDM source driver Mao Jinlong
` (8 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Except stm, there could be other sources which are not associated
with cpus. Use IDR to store and search these sources' paths.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++------
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index bbf415c252f9..23ab16dd9b5d 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include <linux/device.h>
#include <linux/io.h>
+#include <linux/idr.h>
#include <linux/err.h>
#include <linux/export.h>
#include <linux/slab.h>
@@ -27,6 +28,13 @@
static DEFINE_MUTEX(coresight_mutex);
static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
+/*
+ * Use IDR to map the hash of the source's device name
+ * to the pointer of path for the source. The idr is for
+ * the sources which aren't associated with CPU.
+ */
+static DEFINE_IDR(path_idr);
+
/**
* struct coresight_node - elements of a path, from source to sink
* @csdev: Address of an element.
@@ -43,14 +51,6 @@ struct coresight_node {
*/
static DEFINE_PER_CPU(struct list_head *, tracer_path);
-/*
- * As of this writing only a single STM can be found in CS topologies. Since
- * there is no way to know if we'll ever see more and what kind of
- * configuration they will enact, for the time being only define a single path
- * for STM.
- */
-static struct list_head *stm_path;
-
/*
* Set up a global trace ID map.
* We may need a per sink ID map in future for larger / multi sink systems.
@@ -1061,6 +1061,7 @@ int coresight_enable(struct coresight_device *csdev)
struct coresight_device *sink;
struct list_head *path;
enum coresight_dev_subtype_source subtype;
+ u32 hash;
subtype = csdev->subtype.source_subtype;
@@ -1115,7 +1116,14 @@ int coresight_enable(struct coresight_device *csdev)
per_cpu(tracer_path, cpu) = path;
break;
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- stm_path = path;
+ /*
+ * Use the hash of source's device name as ID
+ * and map the ID to the pointer of the path.
+ */
+ hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
+ ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL);
+ if (ret)
+ goto err_source;
break;
default:
/* We can't be here */
@@ -1139,6 +1147,7 @@ void coresight_disable(struct coresight_device *csdev)
{
int cpu, ret;
struct list_head *path = NULL;
+ u32 hash;
mutex_lock(&coresight_mutex);
@@ -1156,14 +1165,20 @@ void coresight_disable(struct coresight_device *csdev)
per_cpu(tracer_path, cpu) = NULL;
break;
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
- path = stm_path;
- stm_path = NULL;
+ hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
+ /* Find the path by the hash. */
+ path = idr_find(&path_idr, hash);
+ if (path == NULL) {
+ pr_err("Path is not found for %s\n", dev_name(&csdev->dev));
+ goto out;
+ }
break;
default:
/* We can't be here */
break;
}
+ idr_remove(&path_idr, hash);
coresight_disable_path(path);
coresight_release_path(path);
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths.
2022-04-12 12:50 ` [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths Mao Jinlong
@ 2022-04-14 14:20 ` Mike Leach
0 siblings, 0 replies; 31+ messages in thread
From: Mike Leach @ 2022-04-14 14:20 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Except stm, there could be other sources which are not associated
> with cpus. Use IDR to store and search these sources' paths.
>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-core.c | 37 ++++++++++++++------
> 1 file changed, 26 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index bbf415c252f9..23ab16dd9b5d 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -8,6 +8,7 @@
> #include <linux/types.h>
> #include <linux/device.h>
> #include <linux/io.h>
> +#include <linux/idr.h>
> #include <linux/err.h>
> #include <linux/export.h>
> #include <linux/slab.h>
> @@ -27,6 +28,13 @@
> static DEFINE_MUTEX(coresight_mutex);
> static DEFINE_PER_CPU(struct coresight_device *, csdev_sink);
>
> +/*
> + * Use IDR to map the hash of the source's device name
> + * to the pointer of path for the source. The idr is for
> + * the sources which aren't associated with CPU.
> + */
> +static DEFINE_IDR(path_idr);
> +
> /**
> * struct coresight_node - elements of a path, from source to sink
> * @csdev: Address of an element.
> @@ -43,14 +51,6 @@ struct coresight_node {
> */
> static DEFINE_PER_CPU(struct list_head *, tracer_path);
>
> -/*
> - * As of this writing only a single STM can be found in CS topologies. Since
> - * there is no way to know if we'll ever see more and what kind of
> - * configuration they will enact, for the time being only define a single path
> - * for STM.
> - */
> -static struct list_head *stm_path;
> -
> /*
> * Set up a global trace ID map.
> * We may need a per sink ID map in future for larger / multi sink systems.
> @@ -1061,6 +1061,7 @@ int coresight_enable(struct coresight_device *csdev)
> struct coresight_device *sink;
> struct list_head *path;
> enum coresight_dev_subtype_source subtype;
> + u32 hash;
>
> subtype = csdev->subtype.source_subtype;
>
> @@ -1115,7 +1116,14 @@ int coresight_enable(struct coresight_device *csdev)
> per_cpu(tracer_path, cpu) = path;
> break;
> case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> - stm_path = path;
> + /*
> + * Use the hash of source's device name as ID
> + * and map the ID to the pointer of the path.
> + */
> + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
> + ret = idr_alloc_u32(&path_idr, path, &hash, hash, GFP_KERNEL);
> + if (ret)
> + goto err_source;
> break;
> default:
> /* We can't be here */
> @@ -1139,6 +1147,7 @@ void coresight_disable(struct coresight_device *csdev)
> {
> int cpu, ret;
> struct list_head *path = NULL;
> + u32 hash;
>
> mutex_lock(&coresight_mutex);
>
> @@ -1156,14 +1165,20 @@ void coresight_disable(struct coresight_device *csdev)
> per_cpu(tracer_path, cpu) = NULL;
> break;
> case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> - path = stm_path;
> - stm_path = NULL;
> + hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
> + /* Find the path by the hash. */
> + path = idr_find(&path_idr, hash);
> + if (path == NULL) {
> + pr_err("Path is not found for %s\n", dev_name(&csdev->dev));
> + goto out;
> + }
> break;
> default:
> /* We can't be here */
> break;
> }
>
> + idr_remove(&path_idr, hash);
> coresight_disable_path(path);
> coresight_release_path(path);
>
> --
> 2.17.1
>
Reviewed by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 02/10] Coresight: Add coresight TPDM source driver
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
2022-04-12 12:50 ` [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-14 14:53 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
` (7 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add driver to support Coresight device TPDM (Trace, Profiling and
Diagnostics Monitor). TPDM is a monitor to collect data from
different datasets. This change is to add probe/enable/disable
functions for tpdm source.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 13 ++
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-core.c | 5 +-
drivers/hwtracing/coresight/coresight-tpdm.c | 145 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 26 ++++
include/linux/coresight.h | 1 +
6 files changed, 190 insertions(+), 1 deletion(-)
create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 514a9b8086e3..5c506a1cd08f 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -201,4 +201,17 @@ config CORESIGHT_TRBE
To compile this driver as a module, choose M here: the module will be
called coresight-trbe.
+
+config CORESIGHT_TPDM
+ tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
+ select CORESIGHT_LINKS_AND_SINKS
+ help
+ This driver provides support for configuring monitor. Monitors are
+ primarily responsible for data set collection and support the
+ ability to collect any permutation of data set types. Monitors are
+ also responsible for interaction with system cross triggering.
+
+ To compile this driver as a module, choose M here: the module will be
+ called coresight-tpdm.
+
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 329a0c704b87..6bb9b1746bc7 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
+obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
index 23ab16dd9b5d..75fe1781df20 100644
--- a/drivers/hwtracing/coresight/coresight-core.c
+++ b/drivers/hwtracing/coresight/coresight-core.c
@@ -1047,7 +1047,8 @@ static int coresight_validate_source(struct coresight_device *csdev,
}
if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
- subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
+ subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
+ subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY) {
dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
return -EINVAL;
}
@@ -1116,6 +1117,7 @@ int coresight_enable(struct coresight_device *csdev)
per_cpu(tracer_path, cpu) = path;
break;
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
+ case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY:
/*
* Use the hash of source's device name as ID
* and map the ID to the pointer of the path.
@@ -1165,6 +1167,7 @@ void coresight_disable(struct coresight_device *csdev)
per_cpu(tracer_path, cpu) = NULL;
break;
case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
+ case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY:
hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
/* Find the path by the hash. */
path = idr_find(&path_idr, hash);
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
new file mode 100644
index 000000000000..3900ae50670a
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/bitmap.h>
+#include <linux/coresight.h>
+#include <linux/coresight-pmu.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+
+#include "coresight-priv.h"
+#include "coresight-tpdm.h"
+
+DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
+
+/* TPDM enable operations */
+static int tpdm_enable(struct coresight_device *csdev,
+ struct perf_event *event, u32 mode)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ if (drvdata->enable) {
+ mutex_unlock(&drvdata->lock);
+ return -EBUSY;
+ }
+
+ drvdata->enable = true;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDM tracing enabled\n");
+ return 0;
+}
+
+/* TPDM disable operations */
+static void tpdm_disable(struct coresight_device *csdev,
+ struct perf_event *event)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ if (!drvdata->enable) {
+ mutex_unlock(&drvdata->lock);
+ return;
+ }
+
+ drvdata->enable = false;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDM tracing disabled\n");
+}
+
+static const struct coresight_ops_source tpdm_source_ops = {
+ .enable = tpdm_enable,
+ .disable = tpdm_disable,
+};
+
+static const struct coresight_ops tpdm_cs_ops = {
+ .source_ops = &tpdm_source_ops,
+};
+
+static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ struct device *dev = &adev->dev;
+ struct coresight_platform_data *pdata;
+ struct tpdm_drvdata *drvdata;
+ struct coresight_desc desc = { 0 };
+
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ adev->dev.platform_data = pdata;
+
+ /* driver data*/
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+ drvdata->dev = &adev->dev;
+ dev_set_drvdata(dev, drvdata);
+
+ drvdata->base = devm_ioremap_resource(dev, &adev->res);
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ mutex_init(&drvdata->lock);
+
+ /* Set up coresight component description */
+ desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+ desc.type = CORESIGHT_DEV_TYPE_SOURCE;
+ desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY;
+ desc.ops = &tpdm_cs_ops;
+ desc.pdata = adev->dev.platform_data;
+ desc.dev = &adev->dev;
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev))
+ return PTR_ERR(drvdata->csdev);
+
+ /* Decrease pm refcount when probe is done.*/
+ pm_runtime_put(&adev->dev);
+
+ return 0;
+}
+
+static void __exit tpdm_remove(struct amba_device *adev)
+{
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
+
+ coresight_unregister(drvdata->csdev);
+}
+
+/*
+ * Different TPDM has different periph id.
+ * The difference is 0-7 bits' value. So ignore 0-7 bits.
+ */
+static struct amba_id tpdm_ids[] = {
+ {
+ .id = 0x000f0e00,
+ .mask = 0x000fff00,
+ },
+ { 0, 0},
+};
+
+static struct amba_driver tpdm_driver = {
+ .drv = {
+ .name = "coresight-tpdm",
+ .owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
+ },
+ .probe = tpdm_probe,
+ .id_table = tpdm_ids,
+};
+
+module_amba_driver(tpdm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
new file mode 100644
index 000000000000..94a7748a5426
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_TPDM_H
+#define _CORESIGHT_CORESIGHT_TPDM_H
+
+/**
+ * struct tpdm_drvdata - specifics associated to an TPDM component
+ * @base: memory mapped base address for this component.
+ * @dev: The device entity associated to this component.
+ * @csdev: component vitals needed by the framework.
+ * @lock: lock for the enable value.
+ * @enable: enable status of the component.
+ */
+
+struct tpdm_drvdata {
+ void __iomem *base;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct mutex lock;
+ bool enable;
+};
+
+#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 247147c11231..a9efac55029d 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -61,6 +61,7 @@ enum coresight_dev_subtype_source {
CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
+ CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY,
};
enum coresight_dev_subtype_helper {
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 02/10] Coresight: Add coresight TPDM source driver
2022-04-12 12:50 ` [PATCH v5 02/10] Coresight: Add coresight TPDM source driver Mao Jinlong
@ 2022-04-14 14:53 ` Mike Leach
0 siblings, 0 replies; 31+ messages in thread
From: Mike Leach @ 2022-04-14 14:53 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Add driver to support Coresight device TPDM (Trace, Profiling and
> Diagnostics Monitor). TPDM is a monitor to collect data from
> different datasets. This change is to add probe/enable/disable
> functions for tpdm source.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 13 ++
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-core.c | 5 +-
> drivers/hwtracing/coresight/coresight-tpdm.c | 145 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 26 ++++
> include/linux/coresight.h | 1 +
> 6 files changed, 190 insertions(+), 1 deletion(-)
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.c
> create mode 100644 drivers/hwtracing/coresight/coresight-tpdm.h
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 514a9b8086e3..5c506a1cd08f 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -201,4 +201,17 @@ config CORESIGHT_TRBE
>
> To compile this driver as a module, choose M here: the module will be
> called coresight-trbe.
> +
> +config CORESIGHT_TPDM
> + tristate "CoreSight Trace, Profiling & Diagnostics Monitor driver"
> + select CORESIGHT_LINKS_AND_SINKS
> + help
> + This driver provides support for configuring monitor. Monitors are
> + primarily responsible for data set collection and support the
> + ability to collect any permutation of data set types. Monitors are
> + also responsible for interaction with system cross triggering.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called coresight-tpdm.
> +
> endif
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 329a0c704b87..6bb9b1746bc7 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -25,5 +25,6 @@ obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
> +obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
> coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
> coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-core.c b/drivers/hwtracing/coresight/coresight-core.c
> index 23ab16dd9b5d..75fe1781df20 100644
> --- a/drivers/hwtracing/coresight/coresight-core.c
> +++ b/drivers/hwtracing/coresight/coresight-core.c
> @@ -1047,7 +1047,8 @@ static int coresight_validate_source(struct coresight_device *csdev,
> }
>
> if (subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_PROC &&
> - subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE) {
> + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE &&
> + subtype != CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY) {
> dev_err(&csdev->dev, "wrong device subtype in %s\n", function);
> return -EINVAL;
> }
> @@ -1116,6 +1117,7 @@ int coresight_enable(struct coresight_device *csdev)
> per_cpu(tracer_path, cpu) = path;
> break;
> case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> + case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY:
> /*
> * Use the hash of source's device name as ID
> * and map the ID to the pointer of the path.
> @@ -1165,6 +1167,7 @@ void coresight_disable(struct coresight_device *csdev)
> per_cpu(tracer_path, cpu) = NULL;
> break;
> case CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE:
> + case CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY:
> hash = hashlen_hash(hashlen_string(NULL, dev_name(&csdev->dev)));
> /* Find the path by the hash. */
> path = idr_find(&path_idr, hash);
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> new file mode 100644
> index 000000000000..3900ae50670a
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -0,0 +1,145 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/amba/bus.h>
> +#include <linux/bitmap.h>
> +#include <linux/coresight.h>
> +#include <linux/coresight-pmu.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +
> +#include "coresight-priv.h"
> +#include "coresight-tpdm.h"
> +
> +DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
> +
> +/* TPDM enable operations */
> +static int tpdm_enable(struct coresight_device *csdev,
> + struct perf_event *event, u32 mode)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + if (drvdata->enable) {
> + mutex_unlock(&drvdata->lock);
> + return -EBUSY;
> + }
> +
> + drvdata->enable = true;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDM tracing enabled\n");
> + return 0;
> +}
> +
> +/* TPDM disable operations */
> +static void tpdm_disable(struct coresight_device *csdev,
> + struct perf_event *event)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + if (!drvdata->enable) {
> + mutex_unlock(&drvdata->lock);
> + return;
> + }
> +
> + drvdata->enable = false;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDM tracing disabled\n");
> +}
> +
> +static const struct coresight_ops_source tpdm_source_ops = {
> + .enable = tpdm_enable,
> + .disable = tpdm_disable,
> +};
> +
> +static const struct coresight_ops tpdm_cs_ops = {
> + .source_ops = &tpdm_source_ops,
> +};
> +
> +static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + struct device *dev = &adev->dev;
> + struct coresight_platform_data *pdata;
> + struct tpdm_drvdata *drvdata;
> + struct coresight_desc desc = { 0 };
> +
> + pdata = coresight_get_platform_data(dev);
> + if (IS_ERR(pdata))
> + return PTR_ERR(pdata);
> + adev->dev.platform_data = pdata;
> +
> + /* driver data*/
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> + drvdata->dev = &adev->dev;
> + dev_set_drvdata(dev, drvdata);
> +
> + drvdata->base = devm_ioremap_resource(dev, &adev->res);
> + if (!drvdata->base)
> + return -ENOMEM;
> +
> + mutex_init(&drvdata->lock);
> +
> + /* Set up coresight component description */
> + desc.name = coresight_alloc_device_name(&tpdm_devs, dev);
> + if (!desc.name)
> + return -ENOMEM;
> + desc.type = CORESIGHT_DEV_TYPE_SOURCE;
> + desc.subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY;
> + desc.ops = &tpdm_cs_ops;
> + desc.pdata = adev->dev.platform_data;
> + desc.dev = &adev->dev;
> + drvdata->csdev = coresight_register(&desc);
> + if (IS_ERR(drvdata->csdev))
> + return PTR_ERR(drvdata->csdev);
> +
> + /* Decrease pm refcount when probe is done.*/
> + pm_runtime_put(&adev->dev);
> +
> + return 0;
> +}
> +
> +static void __exit tpdm_remove(struct amba_device *adev)
> +{
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(&adev->dev);
> +
> + coresight_unregister(drvdata->csdev);
> +}
How is this function called? The other coresight devices set the
.remove function pointer in the amba_driver structure.
> +/*
> + * Different TPDM has different periph id.
> + * The difference is 0-7 bits' value. So ignore 0-7 bits.
> + */
> +static struct amba_id tpdm_ids[] = {
> + {
> + .id = 0x000f0e00,
> + .mask = 0x000fff00,
> + },
> + { 0, 0},
> +};
> +
> +static struct amba_driver tpdm_driver = {
> + .drv = {
> + .name = "coresight-tpdm",
> + .owner = THIS_MODULE,
> + .suppress_bind_attrs = true,
> + },
> + .probe = tpdm_probe,
Do you need:-
.remove = tpdm_remove;
in here?
Regards
Mike
> + .id_table = tpdm_ids,
> +};
> +
> +module_amba_driver(tpdm_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Monitor driver");
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> new file mode 100644
> index 000000000000..94a7748a5426
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -0,0 +1,26 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _CORESIGHT_CORESIGHT_TPDM_H
> +#define _CORESIGHT_CORESIGHT_TPDM_H
> +
> +/**
> + * struct tpdm_drvdata - specifics associated to an TPDM component
> + * @base: memory mapped base address for this component.
> + * @dev: The device entity associated to this component.
> + * @csdev: component vitals needed by the framework.
> + * @lock: lock for the enable value.
> + * @enable: enable status of the component.
> + */
> +
> +struct tpdm_drvdata {
> + void __iomem *base;
> + struct device *dev;
> + struct coresight_device *csdev;
> + struct mutex lock;
> + bool enable;
> +};
> +
> +#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index 247147c11231..a9efac55029d 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -61,6 +61,7 @@ enum coresight_dev_subtype_source {
> CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
> CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
> CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
> + CORESIGHT_DEV_SUBTYPE_SOURCE_DATA_ONLY,
> };
>
> enum coresight_dev_subtype_helper {
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
2022-04-12 12:50 ` [PATCH v5 01/10] coresight: core: Use IDR for non-cpu bound sources' paths Mao Jinlong
2022-04-12 12:50 ` [PATCH v5 02/10] Coresight: Add coresight TPDM source driver Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-14 15:22 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
` (6 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Adds new coresight-tpdm.yaml file describing the bindings required
to define tpdm in the device trees.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../bindings/arm/coresight-tpdm.yaml | 99 +++++++++++++++++++
.../devicetree/bindings/arm/coresight.txt | 7 ++
MAINTAINERS | 1 +
3 files changed, 107 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
new file mode 100644
index 000000000000..05210e0fc262
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
@@ -0,0 +1,99 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trace, Profiling and Diagnostics Monitor - TPDM
+
+description: |
+ The TPDM or Monitor serves as data collection component for various dataset
+ types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
+ Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
+ Single Bit (DSB). It performs data collection in the data producing clock
+ domain and transfers it to the data collection time domain, generally ATB
+ clock domain.
+
+ The primary use case of the TPDM is to collect data from different data
+ sources and send it to a TPDA for packetization, timestamping, and funneling.
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+properties:
+ $nodename:
+ pattern: "^tpdm(@[0-9a-f]+)$"
+ compatible:
+ items:
+ - const: qcom,coresight-tpdm
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb_pclk
+
+ out-ports:
+ description: |
+ Output connections from the TPDM to coresight funnle/tpda.
+ $ref: /schemas/graph.yaml#/properties/ports
+ properties:
+ port:
+ description: Output connection from the TPDM to coresight
+ funnel/tpda.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ # minimum TPDM definition. TPDM connect to coresight funnel.
+ - |
+ tpdm@6980000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x6980000 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_turing_out_funnel_turing: endpoint {
+ remote-endpoint =
+ <&funnel_turing_in_tpdm_turing>;
+ };
+ };
+ };
+ };
+ # minimum TPDM definition. TPDM connect to coresight TPDA.
+ - |
+ tpdm@684c000 {
+ compatible = "qcom,coresight-tpdm", "arm,primecell";
+ reg = <0x684c000 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_prng_out_tpda_qdss: endpoint {
+ remote-endpoint =
+ <&tpda_qdss_in_tpdm_prng>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index c68d93a35b6c..f7ce8af48574 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -52,6 +52,10 @@ its hardware characteristcs.
"arm,coresight-cti", "arm,primecell";
See coresight-cti.yaml for full CTI definitions.
+ - Trace, Profiling and Diagnostics Monitor (TPDM):
+ "qcom,coresight-tpdm", "arm,primecell";
+ See coresight-tpdm.yaml for full TPDM definitions.
+
* reg: physical base address and length of the register
set(s) of the component.
@@ -82,6 +86,9 @@ its hardware characteristcs.
* Required properties for Coresight Cross Trigger Interface (CTI)
See coresight-cti.yaml for full CTI definitions.
+* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM)
+ See coresight-tpdm.yaml for full TPDM definitions.
+
* Required properties for devices that don't show up on the AMBA bus, such as
non-configurable replicators and non-configurable funnels:
diff --git a/MAINTAINERS b/MAINTAINERS
index 61d9f114c37f..0d39bb37935d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1977,6 +1977,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
+F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
F: Documentation/devicetree/bindings/arm/coresight.txt
F: Documentation/devicetree/bindings/arm/ete.yaml
F: Documentation/devicetree/bindings/arm/trbe.yaml
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions
2022-04-12 12:50 ` [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
@ 2022-04-14 15:22 ` Mike Leach
2022-04-15 9:56 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-14 15:22 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Adds new coresight-tpdm.yaml file describing the bindings required
> to define tpdm in the device trees.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../bindings/arm/coresight-tpdm.yaml | 99 +++++++++++++++++++
> .../devicetree/bindings/arm/coresight.txt | 7 ++
> MAINTAINERS | 1 +
> 3 files changed, 107 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> new file mode 100644
> index 000000000000..05210e0fc262
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> @@ -0,0 +1,99 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Trace, Profiling and Diagnostics Monitor - TPDM
> +
> +description: |
> + The TPDM or Monitor serves as data collection component for various dataset
> + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
> + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
> + Single Bit (DSB). It performs data collection in the data producing clock
> + domain and transfers it to the data collection time domain, generally ATB
> + clock domain.
> +
> + The primary use case of the TPDM is to collect data from different data
> + sources and send it to a TPDA for packetization, timestamping, and funneling.
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@arm.com>
> + - Mathieu Poirier <mathieu.poirier@linaro.org>
> +
These should be e-mail addresses of maintainers for this binding, not
the coresight sub-system.
See writing-schema.rst
> +properties:
> + $nodename:
> + pattern: "^tpdm(@[0-9a-f]+)$"
> + compatible:
> + items:
> + - const: qcom,coresight-tpdm
> + - const: arm,primecell
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: apb_pclk
> +
> + out-ports:
> + description: |
> + Output connections from the TPDM to coresight funnle/tpda.
> + $ref: /schemas/graph.yaml#/properties/ports
> + properties:
> + port:
> + description: Output connection from the TPDM to coresight
> + funnel/tpda.
> + $ref: /schemas/graph.yaml#/properties/port
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> +
> +additionalProperties: false
> +
> +examples:
> + # minimum TPDM definition. TPDM connect to coresight funnel.
> + - |
> + tpdm@6980000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x6980000 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + tpdm_turing_out_funnel_turing: endpoint {
> + remote-endpoint =
> + <&funnel_turing_in_tpdm_turing>;
> + };
> + };
> + };
> + };
> + # minimum TPDM definition. TPDM connect to coresight TPDA.
> + - |
> + tpdm@684c000 {
> + compatible = "qcom,coresight-tpdm", "arm,primecell";
> + reg = <0x684c000 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + tpdm_prng_out_tpda_qdss: endpoint {
> + remote-endpoint =
> + <&tpda_qdss_in_tpdm_prng>;
> + };
> + };
> + };
> + };
> +
> +...
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index c68d93a35b6c..f7ce8af48574 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -52,6 +52,10 @@ its hardware characteristcs.
> "arm,coresight-cti", "arm,primecell";
> See coresight-cti.yaml for full CTI definitions.
>
> + - Trace, Profiling and Diagnostics Monitor (TPDM):
> + "qcom,coresight-tpdm", "arm,primecell";
> + See coresight-tpdm.yaml for full TPDM definitions.
> +
> * reg: physical base address and length of the register
> set(s) of the component.
>
> @@ -82,6 +86,9 @@ its hardware characteristcs.
> * Required properties for Coresight Cross Trigger Interface (CTI)
> See coresight-cti.yaml for full CTI definitions.
>
> +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM)
> + See coresight-tpdm.yaml for full TPDM definitions.
> +
> * Required properties for devices that don't show up on the AMBA bus, such as
> non-configurable replicators and non-configurable funnels:
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 61d9f114c37f..0d39bb37935d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1977,6 +1977,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
> +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
> F: Documentation/devicetree/bindings/arm/coresight.txt
> F: Documentation/devicetree/bindings/arm/ete.yaml
> F: Documentation/devicetree/bindings/arm/trbe.yaml
> --
> 2.17.1
>
With the above:
Reviewed by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions
2022-04-14 15:22 ` Mike Leach
@ 2022-04-15 9:56 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-15 9:56 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi Mike,
On 4/14/2022 11:22 PM, Mike Leach wrote:
> Hi,
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> Adds new coresight-tpdm.yaml file describing the bindings required
>> to define tpdm in the device trees.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> .../bindings/arm/coresight-tpdm.yaml | 99 +++++++++++++++++++
>> .../devicetree/bindings/arm/coresight.txt | 7 ++
>> MAINTAINERS | 1 +
>> 3 files changed, 107 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>> new file mode 100644
>> index 000000000000..05210e0fc262
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>> @@ -0,0 +1,99 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/coresight-tpdm.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Trace, Profiling and Diagnostics Monitor - TPDM
>> +
>> +description: |
>> + The TPDM or Monitor serves as data collection component for various dataset
>> + types specified in the QPMDA spec. It covers Implementation defined ((ImplDef),
>> + Basic Counts (BC), Tenure Counts (TC), Continuous Multi-Bit (CMB), and Discrete
>> + Single Bit (DSB). It performs data collection in the data producing clock
>> + domain and transfers it to the data collection time domain, generally ATB
>> + clock domain.
>> +
>> + The primary use case of the TPDM is to collect data from different data
>> + sources and send it to a TPDA for packetization, timestamping, and funneling.
>> +
>> +maintainers:
>> + - Suzuki K Poulose <suzuki.poulose@arm.com>
>> + - Mathieu Poirier <mathieu.poirier@linaro.org>
>> +
> These should be e-mail addresses of maintainers for this binding, not
> the coresight sub-system.
> See writing-schema.rst
I will update.
>
>> +properties:
>> + $nodename:
>> + pattern: "^tpdm(@[0-9a-f]+)$"
>> + compatible:
>> + items:
>> + - const: qcom,coresight-tpdm
>> + - const: arm,primecell
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: apb_pclk
>> +
>> + out-ports:
>> + description: |
>> + Output connections from the TPDM to coresight funnle/tpda.
>> + $ref: /schemas/graph.yaml#/properties/ports
>> + properties:
>> + port:
>> + description: Output connection from the TPDM to coresight
>> + funnel/tpda.
>> + $ref: /schemas/graph.yaml#/properties/port
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + # minimum TPDM definition. TPDM connect to coresight funnel.
>> + - |
>> + tpdm@6980000 {
>> + compatible = "qcom,coresight-tpdm", "arm,primecell";
>> + reg = <0x6980000 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + tpdm_turing_out_funnel_turing: endpoint {
>> + remote-endpoint =
>> + <&funnel_turing_in_tpdm_turing>;
>> + };
>> + };
>> + };
>> + };
>> + # minimum TPDM definition. TPDM connect to coresight TPDA.
>> + - |
>> + tpdm@684c000 {
>> + compatible = "qcom,coresight-tpdm", "arm,primecell";
>> + reg = <0x684c000 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + tpdm_prng_out_tpda_qdss: endpoint {
>> + remote-endpoint =
>> + <&tpda_qdss_in_tpdm_prng>;
>> + };
>> + };
>> + };
>> + };
>> +
>> +...
>> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
>> index c68d93a35b6c..f7ce8af48574 100644
>> --- a/Documentation/devicetree/bindings/arm/coresight.txt
>> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
>> @@ -52,6 +52,10 @@ its hardware characteristcs.
>> "arm,coresight-cti", "arm,primecell";
>> See coresight-cti.yaml for full CTI definitions.
>>
>> + - Trace, Profiling and Diagnostics Monitor (TPDM):
>> + "qcom,coresight-tpdm", "arm,primecell";
>> + See coresight-tpdm.yaml for full TPDM definitions.
>> +
>> * reg: physical base address and length of the register
>> set(s) of the component.
>>
>> @@ -82,6 +86,9 @@ its hardware characteristcs.
>> * Required properties for Coresight Cross Trigger Interface (CTI)
>> See coresight-cti.yaml for full CTI definitions.
>>
>> +* Required properties for Trace, Profiling and Diagnostics Monitor (TPDM)
>> + See coresight-tpdm.yaml for full TPDM definitions.
>> +
>> * Required properties for devices that don't show up on the AMBA bus, such as
>> non-configurable replicators and non-configurable funnels:
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 61d9f114c37f..0d39bb37935d 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1977,6 +1977,7 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
>> F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
>> F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
>> F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
>> +F: Documentation/devicetree/bindings/arm/coresight-tpdm.yaml
>> F: Documentation/devicetree/bindings/arm/coresight.txt
>> F: Documentation/devicetree/bindings/arm/ete.yaml
>> F: Documentation/devicetree/bindings/arm/trbe.yaml
>> --
>> 2.17.1
>>
> With the above:
> Reviewed by: Mike Leach <mike.leach@linaro.org>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (2 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 03/10] dt-bindings: arm: Adds CoreSight TPDM hardware definitions Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-19 9:23 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 05/10] coresight-tpdm: Add integration test support Mao Jinlong
` (5 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
TPDM serves as data collection component for various dataset types.
DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
can be enabled for data collection by writing 1 to the first bit of
DSB_CR register. This change is to add enable/disable function for
DSB dataset by writing DSB_CR register.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++
2 files changed, 82 insertions(+)
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index 3900ae50670a..d7b970cdcf51 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -20,7 +20,28 @@
DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
+static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 1 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val | BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/* TPDM enable operations */
+static void _tpdm_enable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_enable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+}
+
static int tpdm_enable(struct coresight_device *csdev,
struct perf_event *event, u32 mode)
{
@@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
return -EBUSY;
}
+ _tpdm_enable(drvdata);
drvdata->enable = true;
mutex_unlock(&drvdata->lock);
@@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
return 0;
}
+static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
+{
+ u32 val;
+
+ /* Set the enable bit of DSB control register to 0 */
+ val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
+ val = val & ~BIT(0);
+ writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
+}
+
/* TPDM disable operations */
+static void _tpdm_disable(struct tpdm_drvdata *drvdata)
+{
+ CS_UNLOCK(drvdata->base);
+
+ /* Check if DSB datasets is present for TPDM. */
+ if (test_bit(TPDM_DS_DSB, drvdata->datasets))
+ tpdm_disable_dsb(drvdata);
+
+ CS_LOCK(drvdata->base);
+
+}
+
static void tpdm_disable(struct coresight_device *csdev,
struct perf_event *event)
{
@@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
return;
}
+ _tpdm_disable(drvdata);
drvdata->enable = false;
mutex_unlock(&drvdata->lock);
@@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
.source_ops = &tpdm_source_ops,
};
+static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
+{
+ int i;
+ u32 pidr;
+
+ CS_UNLOCK(drvdata->base);
+ /* Get the datasets present on the TPDM. */
+ pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
+ for (i = 0; i < TPDM_DATASETS; i++) {
+ if (pidr & BIT(i))
+ __set_bit(i, drvdata->datasets);
+ }
+ CS_LOCK(drvdata->base);
+}
+
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
@@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
+ tpdm_init_default_data(drvdata);
/* Decrease pm refcount when probe is done.*/
pm_runtime_put(&adev->dev);
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index 94a7748a5426..8f05070879c4 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -6,6 +6,25 @@
#ifndef _CORESIGHT_CORESIGHT_TPDM_H
#define _CORESIGHT_CORESIGHT_TPDM_H
+/* The max number of the datasets that TPDM supports */
+#define TPDM_DATASETS 7
+
+/* DSB Subunit Registers */
+#define TPDM_DSB_CR (0x780)
+
+/**
+ * This enum is for PERIPHIDR0 register of TPDM.
+ * The fields [6:0] of PERIPHIDR0 are used to determine what
+ * interfaces and subunits are present on a given TPDM.
+ *
+ * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
+ * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
+ */
+enum tpdm_dataset {
+ TPDM_DS_IMPLDEF,
+ TPDM_DS_DSB,
+};
+
/**
* struct tpdm_drvdata - specifics associated to an TPDM component
* @base: memory mapped base address for this component.
@@ -13,6 +32,7 @@
* @csdev: component vitals needed by the framework.
* @lock: lock for the enable value.
* @enable: enable status of the component.
+ * @datasets: The datasets types present of the TPDM.
*/
struct tpdm_drvdata {
@@ -21,6 +41,7 @@ struct tpdm_drvdata {
struct coresight_device *csdev;
struct mutex lock;
bool enable;
+ DECLARE_BITMAP(datasets, TPDM_DATASETS);
};
#endif /* _CORESIGHT_CORESIGHT_TPDM_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support
2022-04-12 12:50 ` [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
@ 2022-04-19 9:23 ` Mike Leach
2022-04-20 14:41 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-19 9:23 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi,
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> TPDM serves as data collection component for various dataset types.
> DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
> can be enabled for data collection by writing 1 to the first bit of
> DSB_CR register. This change is to add enable/disable function for
> DSB dataset by writing DSB_CR register.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++
> 2 files changed, 82 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index 3900ae50670a..d7b970cdcf51 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -20,7 +20,28 @@
>
> DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
>
> +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
> +{
> + u32 val;
> +
> + /* Set the enable bit of DSB control register to 1 */
> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> + val = val | BIT(0);
Please use #defined values, declared in the header file rather than
BIT(x) here. (the etm4x drivers have been recently updated to use the
same pattern).
e.g.
val |= TPDM_DSB_CR_ENA;
> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
> /* TPDM enable operations */
> +static void _tpdm_enable(struct tpdm_drvdata *drvdata)
> +{
> + CS_UNLOCK(drvdata->base);
> +
> + /* Check if DSB datasets is present for TPDM. */
> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> + tpdm_enable_dsb(drvdata);
> +
> + CS_LOCK(drvdata->base);
> +}
> +
> static int tpdm_enable(struct coresight_device *csdev,
> struct perf_event *event, u32 mode)
> {
> @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
> return -EBUSY;
> }
>
> + _tpdm_enable(drvdata);
> drvdata->enable = true;
> mutex_unlock(&drvdata->lock);
>
> @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
> return 0;
> }
>
> +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
> +{
> + u32 val;
> +
> + /* Set the enable bit of DSB control register to 0 */
> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
> + val = val & ~BIT(0);
val &= ~TPDM_DSB_CR_ENA;
> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
> +}
> +
> /* TPDM disable operations */
> +static void _tpdm_disable(struct tpdm_drvdata *drvdata)
> +{
> + CS_UNLOCK(drvdata->base);
> +
> + /* Check if DSB datasets is present for TPDM. */
> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
> + tpdm_disable_dsb(drvdata);
> +
> + CS_LOCK(drvdata->base);
> +
> +}
> +
> static void tpdm_disable(struct coresight_device *csdev,
> struct perf_event *event)
> {
> @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
> return;
> }
>
> + _tpdm_disable(drvdata);
> drvdata->enable = false;
> mutex_unlock(&drvdata->lock);
>
> @@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
> .source_ops = &tpdm_source_ops,
> };
>
> +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
> +{
> + int i;
> + u32 pidr;
> +
> + CS_UNLOCK(drvdata->base);
> + /* Get the datasets present on the TPDM. */
> + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
> + for (i = 0; i < TPDM_DATASETS; i++) {
> + if (pidr & BIT(i))
> + __set_bit(i, drvdata->datasets);
Could this be considerably simpified? - there are a maximum of 7 bits
for datasets - and you are setting the same bit in drvdata->datasets
for each bit in pidr
e.g. if the datasets declaration is a simple unsigned long, then the
following is easier to read and understand:
drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);
The tests above could then become:
if (drvdata->datasets & BIT(TPDM_DS_DSB)) ...
> + }
> + CS_LOCK(drvdata->base);
> +}
> +
> static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> {
> struct device *dev = &adev->dev;
> @@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> if (IS_ERR(drvdata->csdev))
> return PTR_ERR(drvdata->csdev);
>
> + tpdm_init_default_data(drvdata);
> /* Decrease pm refcount when probe is done.*/
> pm_runtime_put(&adev->dev);
>
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> index 94a7748a5426..8f05070879c4 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -6,6 +6,25 @@
> #ifndef _CORESIGHT_CORESIGHT_TPDM_H
> #define _CORESIGHT_CORESIGHT_TPDM_H
>
> +/* The max number of the datasets that TPDM supports */
> +#define TPDM_DATASETS 7
> +
> +/* DSB Subunit Registers */
> +#define TPDM_DSB_CR (0x780)
> +
declare the enable bit here with comment documenting usage - see above.
> +/**
> + * This enum is for PERIPHIDR0 register of TPDM.
> + * The fields [6:0] of PERIPHIDR0 are used to determine what
> + * interfaces and subunits are present on a given TPDM.
> + *
> + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
> + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
> + */
> +enum tpdm_dataset {
> + TPDM_DS_IMPLDEF,
> + TPDM_DS_DSB,
> +};
> +
> /**
> * struct tpdm_drvdata - specifics associated to an TPDM component
> * @base: memory mapped base address for this component.
> @@ -13,6 +32,7 @@
> * @csdev: component vitals needed by the framework.
> * @lock: lock for the enable value.
> * @enable: enable status of the component.
> + * @datasets: The datasets types present of the TPDM.
> */
>
> struct tpdm_drvdata {
> @@ -21,6 +41,7 @@ struct tpdm_drvdata {
> struct coresight_device *csdev;
> struct mutex lock;
> bool enable;
> + DECLARE_BITMAP(datasets, TPDM_DATASETS);
Could this simply be declared as an unsigned long? - then simplify the
code in the .c file.
Regards
Mike
> };
>
> #endif /* _CORESIGHT_CORESIGHT_TPDM_H */
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support
2022-04-19 9:23 ` Mike Leach
@ 2022-04-20 14:41 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-20 14:41 UTC (permalink / raw)
To: Mike Leach
Cc: Alexander Shishkin, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Thank you Mike for the review.
On 4/19/2022 5:23 PM, Mike Leach wrote:
> Hi,
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> TPDM serves as data collection component for various dataset types.
>> DSB(Discrete Single Bit) is one of the dataset types. DSB subunit
>> can be enabled for data collection by writing 1 to the first bit of
>> DSB_CR register. This change is to add enable/disable function for
>> DSB dataset by writing DSB_CR register.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> drivers/hwtracing/coresight/coresight-tpdm.c | 61 ++++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-tpdm.h | 21 +++++++
>> 2 files changed, 82 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
>> index 3900ae50670a..d7b970cdcf51 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>> @@ -20,7 +20,28 @@
>>
>> DEFINE_CORESIGHT_DEVLIST(tpdm_devs, "tpdm");
>>
>> +static void tpdm_enable_dsb(struct tpdm_drvdata *drvdata)
>> +{
>> + u32 val;
>> +
>> + /* Set the enable bit of DSB control register to 1 */
>> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
>> + val = val | BIT(0);
> Please use #defined values, declared in the header file rather than
> BIT(x) here. (the etm4x drivers have been recently updated to use the
> same pattern).
> e.g.
> val |= TPDM_DSB_CR_ENA;
I will update in next version.
>> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
>> +}
>> +
>> /* TPDM enable operations */
>> +static void _tpdm_enable(struct tpdm_drvdata *drvdata)
>> +{
>> + CS_UNLOCK(drvdata->base);
>> +
>> + /* Check if DSB datasets is present for TPDM. */
>> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
>> + tpdm_enable_dsb(drvdata);
>> +
>> + CS_LOCK(drvdata->base);
>> +}
>> +
>> static int tpdm_enable(struct coresight_device *csdev,
>> struct perf_event *event, u32 mode)
>> {
>> @@ -32,6 +53,7 @@ static int tpdm_enable(struct coresight_device *csdev,
>> return -EBUSY;
>> }
>>
>> + _tpdm_enable(drvdata);
>> drvdata->enable = true;
>> mutex_unlock(&drvdata->lock);
>>
>> @@ -39,7 +61,29 @@ static int tpdm_enable(struct coresight_device *csdev,
>> return 0;
>> }
>>
>> +static void tpdm_disable_dsb(struct tpdm_drvdata *drvdata)
>> +{
>> + u32 val;
>> +
>> + /* Set the enable bit of DSB control register to 0 */
>> + val = readl_relaxed(drvdata->base + TPDM_DSB_CR);
>> + val = val & ~BIT(0);
> val &= ~TPDM_DSB_CR_ENA;
I will update in next version.
>
>> + writel_relaxed(val, drvdata->base + TPDM_DSB_CR);
>> +}
>> +
>> /* TPDM disable operations */
>> +static void _tpdm_disable(struct tpdm_drvdata *drvdata)
>> +{
>> + CS_UNLOCK(drvdata->base);
>> +
>> + /* Check if DSB datasets is present for TPDM. */
>> + if (test_bit(TPDM_DS_DSB, drvdata->datasets))
>> + tpdm_disable_dsb(drvdata);
>> +
>> + CS_LOCK(drvdata->base);
>> +
>> +}
>> +
>> static void tpdm_disable(struct coresight_device *csdev,
>> struct perf_event *event)
>> {
>> @@ -51,6 +95,7 @@ static void tpdm_disable(struct coresight_device *csdev,
>> return;
>> }
>>
>> + _tpdm_disable(drvdata);
>> drvdata->enable = false;
>> mutex_unlock(&drvdata->lock);
>>
>> @@ -66,6 +111,21 @@ static const struct coresight_ops tpdm_cs_ops = {
>> .source_ops = &tpdm_source_ops,
>> };
>>
>> +static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
>> +{
>> + int i;
>> + u32 pidr;
>> +
>> + CS_UNLOCK(drvdata->base);
>> + /* Get the datasets present on the TPDM. */
>> + pidr = readl_relaxed(drvdata->base + CORESIGHT_PERIPHIDR0);
>> + for (i = 0; i < TPDM_DATASETS; i++) {
>> + if (pidr & BIT(i))
>> + __set_bit(i, drvdata->datasets);
> Could this be considerably simpified? - there are a maximum of 7 bits
> for datasets - and you are setting the same bit in drvdata->datasets
> for each bit in pidr
>
> e.g. if the datasets declaration is a simple unsigned long, then the
> following is easier to read and understand:
>
> drvdata->datasets |= pidr & GENMASK(TPDM_DATASETS - 1, 0);
>
> The tests above could then become:
> if (drvdata->datasets & BIT(TPDM_DS_DSB)) ...
>
I will check your suggestion and update in next version.
>> + }
>> + CS_LOCK(drvdata->base);
>> +}
>> +
>> static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>> {
>> struct device *dev = &adev->dev;
>> @@ -104,6 +164,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>> if (IS_ERR(drvdata->csdev))
>> return PTR_ERR(drvdata->csdev);
>>
>> + tpdm_init_default_data(drvdata);
>> /* Decrease pm refcount when probe is done.*/
>> pm_runtime_put(&adev->dev);
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
>> index 94a7748a5426..8f05070879c4 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
>> @@ -6,6 +6,25 @@
>> #ifndef _CORESIGHT_CORESIGHT_TPDM_H
>> #define _CORESIGHT_CORESIGHT_TPDM_H
>>
>> +/* The max number of the datasets that TPDM supports */
>> +#define TPDM_DATASETS 7
>> +
>> +/* DSB Subunit Registers */
>> +#define TPDM_DSB_CR (0x780)
>> +
> declare the enable bit here with comment documenting usage - see above.
>
>> +/**
>> + * This enum is for PERIPHIDR0 register of TPDM.
>> + * The fields [6:0] of PERIPHIDR0 are used to determine what
>> + * interfaces and subunits are present on a given TPDM.
>> + *
>> + * PERIPHIDR0[0] : Fix to 1 if ImplDef subunit present, else 0
>> + * PERIPHIDR0[1] : Fix to 1 if DSB subunit present, else 0
>> + */
>> +enum tpdm_dataset {
>> + TPDM_DS_IMPLDEF,
>> + TPDM_DS_DSB,
>> +};
>> +
>> /**
>> * struct tpdm_drvdata - specifics associated to an TPDM component
>> * @base: memory mapped base address for this component.
>> @@ -13,6 +32,7 @@
>> * @csdev: component vitals needed by the framework.
>> * @lock: lock for the enable value.
>> * @enable: enable status of the component.
>> + * @datasets: The datasets types present of the TPDM.
>> */
>>
>> struct tpdm_drvdata {
>> @@ -21,6 +41,7 @@ struct tpdm_drvdata {
>> struct coresight_device *csdev;
>> struct mutex lock;
>> bool enable;
>> + DECLARE_BITMAP(datasets, TPDM_DATASETS);
> Could this simply be declared as an unsigned long? - then simplify the
> code in the .c file.
>
> Regards
>
> Mike
>
>> };
>>
>> #endif /* _CORESIGHT_CORESIGHT_TPDM_H */
>> --
>> 2.17.1
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 05/10] coresight-tpdm: Add integration test support
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (3 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 04/10] coresight-tpdm: Add DSB dataset support Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-13 13:57 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
` (4 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Integration test for tpdm can help to generate the data for
verification of the topology during TPDM software bring up.
Sample:
echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test
echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test
cat /dev/tmc_etf0 > /data/etf-tpdm1.bin
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 9 +++
drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++
3 files changed, 87 insertions(+)
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 5c506a1cd08f..60248fef4089 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -214,4 +214,13 @@ config CORESIGHT_TPDM
To compile this driver as a module, choose M here: the module will be
called coresight-tpdm.
+config CORESIGHT_TPDM_INTEGRATION_TEST
+ bool "Enable CoreSight Integration Test For TPDM"
+ depends on CORESIGHT_TPDM
+ help
+ This option adds support for the CoreSight integration test on this
+ devie. Coresight architecture provides integration control modes of
+ operation to facilitate integration testing and software bringup
+ and/or to instrument topology discovery. The TPDM utilizes integration
+ mode to accomplish integration testing and software bringup.
endif
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
index d7b970cdcf51..14bccbff467d 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.c
+++ b/drivers/hwtracing/coresight/coresight-tpdm.c
@@ -126,6 +126,69 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
CS_LOCK(drvdata->base);
}
+/*
+ * Define CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST to enable
+ * integration_test sysfs nodes. It will help to generate
+ * tpdm data to make sure that the trace path is enabled
+ * and the funnel configurations are fine.
+ */
+#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
+/*
+ * value 1: 64 bits test data
+ * value 2: 32 bits test data
+ */
+static ssize_t integration_test_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t size)
+{
+ int i, ret = 0;
+ unsigned long val;
+ struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
+
+ ret = kstrtoul(buf, 10, &val);
+ if (ret)
+ return ret;
+
+ if (val != 1 && val != 2)
+ return -EINVAL;
+
+ if (!drvdata->enable)
+ return -EINVAL;
+
+ if (val == 1)
+ val = ATBCNTRL_VAL_64;
+ else
+ val = ATBCNTRL_VAL_32;
+ CS_UNLOCK(drvdata->base);
+ writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
+
+ for (i = 1; i < INTEGRATION_TEST_CYCLE; i++)
+ writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
+
+ writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
+ CS_LOCK(drvdata->base);
+ return size;
+}
+static DEVICE_ATTR_WO(integration_test);
+#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
+
+static struct attribute *tpdm_attrs[] = {
+#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
+ &dev_attr_integration_test.attr,
+#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
+ NULL,
+};
+
+static struct attribute_group tpdm_attr_grp = {
+ .attrs = tpdm_attrs,
+};
+
+static const struct attribute_group *tpdm_attr_grps[] = {
+ &tpdm_attr_grp,
+ NULL,
+};
+
static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
{
struct device *dev = &adev->dev;
@@ -160,6 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
desc.ops = &tpdm_cs_ops;
desc.pdata = adev->dev.platform_data;
desc.dev = &adev->dev;
+ desc.groups = tpdm_attr_grps;
drvdata->csdev = coresight_register(&desc);
if (IS_ERR(drvdata->csdev))
return PTR_ERR(drvdata->csdev);
diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
index 8f05070879c4..ea457ba5434e 100644
--- a/drivers/hwtracing/coresight/coresight-tpdm.h
+++ b/drivers/hwtracing/coresight/coresight-tpdm.h
@@ -12,6 +12,20 @@
/* DSB Subunit Registers */
#define TPDM_DSB_CR (0x780)
+/* TPDM integration test registers */
+#define TPDM_ITATBCNTRL (0xEF0)
+#define TPDM_ITCNTRL (0xF00)
+
+/* Register value for integration test */
+#define ATBCNTRL_VAL_32 0xC00F1409
+#define ATBCNTRL_VAL_64 0xC01F1409
+
+/*
+ * Number of cycles to write value when
+ * integration test.
+ */
+#define INTEGRATION_TEST_CYCLE 10
+
/**
* This enum is for PERIPHIDR0 register of TPDM.
* The fields [6:0] of PERIPHIDR0 are used to determine what
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 05/10] coresight-tpdm: Add integration test support
2022-04-12 12:50 ` [PATCH v5 05/10] coresight-tpdm: Add integration test support Mao Jinlong
@ 2022-04-13 13:57 ` Mike Leach
2022-04-13 16:53 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-13 13:57 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Integration test for tpdm can help to generate the data for
> verification of the topology during TPDM software bring up.
>
> Sample:
> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
> echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
> echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test
> echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test
> cat /dev/tmc_etf0 > /data/etf-tpdm1.bin
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 9 +++
> drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++
> 3 files changed, 87 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 5c506a1cd08f..60248fef4089 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -214,4 +214,13 @@ config CORESIGHT_TPDM
> To compile this driver as a module, choose M here: the module will be
> called coresight-tpdm.
>
> +config CORESIGHT_TPDM_INTEGRATION_TEST
> + bool "Enable CoreSight Integration Test For TPDM"
> + depends on CORESIGHT_TPDM
> + help
> + This option adds support for the CoreSight integration test on this
> + devie. Coresight architecture provides integration control modes of
> + operation to facilitate integration testing and software bringup
> + and/or to instrument topology discovery. The TPDM utilizes integration
> + mode to accomplish integration testing and software bringup.
> endif
For the last patchset you mentioned that you were making this
configurable because the CTI intgration tests were also configurable.
The reason that the CTI intergration test registers were done in this
way is that some of the CoreSight components were not guaranteed to
return to a usable state once integration test was disabled.
Thus after use of the integration test, a complete board reset was
recommended. Therefore we ensured that these features would only be
used by those specifically configuring them and who were hopefully
aware of the potentail limitations
If your hardware can reliably enable and disable integration test
without adverse effects, then you may wish to consider making the
integration test a permanent feature of the driver.
Regards
Mike
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
> index d7b970cdcf51..14bccbff467d 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
> @@ -126,6 +126,69 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
> CS_LOCK(drvdata->base);
> }
>
> +/*
> + * Define CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST to enable
> + * integration_test sysfs nodes. It will help to generate
> + * tpdm data to make sure that the trace path is enabled
> + * and the funnel configurations are fine.
> + */
> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
> +/*
> + * value 1: 64 bits test data
> + * value 2: 32 bits test data
> + */
> +static ssize_t integration_test_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t size)
> +{
> + int i, ret = 0;
> + unsigned long val;
> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
> +
> + ret = kstrtoul(buf, 10, &val);
> + if (ret)
> + return ret;
> +
> + if (val != 1 && val != 2)
> + return -EINVAL;
> +
> + if (!drvdata->enable)
> + return -EINVAL;
> +
> + if (val == 1)
> + val = ATBCNTRL_VAL_64;
> + else
> + val = ATBCNTRL_VAL_32;
> + CS_UNLOCK(drvdata->base);
> + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
> +
> + for (i = 1; i < INTEGRATION_TEST_CYCLE; i++)
> + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
> +
> + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
> + CS_LOCK(drvdata->base);
> + return size;
> +}
> +static DEVICE_ATTR_WO(integration_test);
> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
> +
> +static struct attribute *tpdm_attrs[] = {
> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
> + &dev_attr_integration_test.attr,
> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
> + NULL,
> +};
> +
> +static struct attribute_group tpdm_attr_grp = {
> + .attrs = tpdm_attrs,
> +};
> +
> +static const struct attribute_group *tpdm_attr_grps[] = {
> + &tpdm_attr_grp,
> + NULL,
> +};
> +
> static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> {
> struct device *dev = &adev->dev;
> @@ -160,6 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
> desc.ops = &tpdm_cs_ops;
> desc.pdata = adev->dev.platform_data;
> desc.dev = &adev->dev;
> + desc.groups = tpdm_attr_grps;
> drvdata->csdev = coresight_register(&desc);
> if (IS_ERR(drvdata->csdev))
> return PTR_ERR(drvdata->csdev);
> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
> index 8f05070879c4..ea457ba5434e 100644
> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
> @@ -12,6 +12,20 @@
> /* DSB Subunit Registers */
> #define TPDM_DSB_CR (0x780)
>
> +/* TPDM integration test registers */
> +#define TPDM_ITATBCNTRL (0xEF0)
> +#define TPDM_ITCNTRL (0xF00)
> +
> +/* Register value for integration test */
> +#define ATBCNTRL_VAL_32 0xC00F1409
> +#define ATBCNTRL_VAL_64 0xC01F1409
> +
> +/*
> + * Number of cycles to write value when
> + * integration test.
> + */
> +#define INTEGRATION_TEST_CYCLE 10
> +
> /**
> * This enum is for PERIPHIDR0 register of TPDM.
> * The fields [6:0] of PERIPHIDR0 are used to determine what
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 05/10] coresight-tpdm: Add integration test support
2022-04-13 13:57 ` Mike Leach
@ 2022-04-13 16:53 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-13 16:53 UTC (permalink / raw)
To: Mike Leach
Cc: Alexander Shishkin, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Hi Mike,
Thank you for review.
On 4/13/2022 9:57 PM, Mike Leach wrote:
> Hi
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> Integration test for tpdm can help to generate the data for
>> verification of the topology during TPDM software bring up.
>>
>> Sample:
>> echo 1 > /sys/bus/coresight/devices/tmc_etf0/enable_sink
>> echo 1 > /sys/bus/coresight/devices/tpdm1/enable_source
>> echo 1 > /sys/bus/coresight/devices/tpdm1/integration_test
>> echo 2 > /sys/bus/coresight/devices/tpdm1/integration_test
>> cat /dev/tmc_etf0 > /data/etf-tpdm1.bin
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> drivers/hwtracing/coresight/Kconfig | 9 +++
>> drivers/hwtracing/coresight/coresight-tpdm.c | 64 ++++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-tpdm.h | 14 +++++
>> 3 files changed, 87 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index 5c506a1cd08f..60248fef4089 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -214,4 +214,13 @@ config CORESIGHT_TPDM
>> To compile this driver as a module, choose M here: the module will be
>> called coresight-tpdm.
>>
>> +config CORESIGHT_TPDM_INTEGRATION_TEST
>> + bool "Enable CoreSight Integration Test For TPDM"
>> + depends on CORESIGHT_TPDM
>> + help
>> + This option adds support for the CoreSight integration test on this
>> + devie. Coresight architecture provides integration control modes of
>> + operation to facilitate integration testing and software bringup
>> + and/or to instrument topology discovery. The TPDM utilizes integration
>> + mode to accomplish integration testing and software bringup.
>> endif
> For the last patchset you mentioned that you were making this
> configurable because the CTI intgration tests were also configurable.
> The reason that the CTI intergration test registers were done in this
> way is that some of the CoreSight components were not guaranteed to
> return to a usable state once integration test was disabled.
> Thus after use of the integration test, a complete board reset was
> recommended. Therefore we ensured that these features would only be
> used by those specifically configuring them and who were hopefully
> aware of the potentail limitations
>
> If your hardware can reliably enable and disable integration test
> without adverse effects, then you may wish to consider making the
> integration test a permanent feature of the driver.
>
> Regards
>
> Mike
TPDM has integration mode control register. The register can control the
component to enable/disable integration mode.
There is no adverse effects which we have do many tests with integration
mode for TPDM.
I will remove this config.
Thanks
Jinlong Mao
>
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.c b/drivers/hwtracing/coresight/coresight-tpdm.c
>> index d7b970cdcf51..14bccbff467d 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.c
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.c
>> @@ -126,6 +126,69 @@ static void tpdm_init_default_data(struct tpdm_drvdata *drvdata)
>> CS_LOCK(drvdata->base);
>> }
>>
>> +/*
>> + * Define CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST to enable
>> + * integration_test sysfs nodes. It will help to generate
>> + * tpdm data to make sure that the trace path is enabled
>> + * and the funnel configurations are fine.
>> + */
>> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
>> +/*
>> + * value 1: 64 bits test data
>> + * value 2: 32 bits test data
>> + */
>> +static ssize_t integration_test_store(struct device *dev,
>> + struct device_attribute *attr,
>> + const char *buf,
>> + size_t size)
>> +{
>> + int i, ret = 0;
>> + unsigned long val;
>> + struct tpdm_drvdata *drvdata = dev_get_drvdata(dev->parent);
>> +
>> + ret = kstrtoul(buf, 10, &val);
>> + if (ret)
>> + return ret;
>> +
>> + if (val != 1 && val != 2)
>> + return -EINVAL;
>> +
>> + if (!drvdata->enable)
>> + return -EINVAL;
>> +
>> + if (val == 1)
>> + val = ATBCNTRL_VAL_64;
>> + else
>> + val = ATBCNTRL_VAL_32;
>> + CS_UNLOCK(drvdata->base);
>> + writel_relaxed(0x1, drvdata->base + TPDM_ITCNTRL);
>> +
>> + for (i = 1; i < INTEGRATION_TEST_CYCLE; i++)
>> + writel_relaxed(val, drvdata->base + TPDM_ITATBCNTRL);
>> +
>> + writel_relaxed(0, drvdata->base + TPDM_ITCNTRL);
>> + CS_LOCK(drvdata->base);
>> + return size;
>> +}
>> +static DEVICE_ATTR_WO(integration_test);
>> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
>> +
>> +static struct attribute *tpdm_attrs[] = {
>> +#ifdef CONFIG_CORESIGHT_TPDM_INTEGRATION_TEST
>> + &dev_attr_integration_test.attr,
>> +#endif /* CORESIGHT_TPDM_INTEGRATION_TEST */
>> + NULL,
>> +};
>> +
>> +static struct attribute_group tpdm_attr_grp = {
>> + .attrs = tpdm_attrs,
>> +};
>> +
>> +static const struct attribute_group *tpdm_attr_grps[] = {
>> + &tpdm_attr_grp,
>> + NULL,
>> +};
>> +
>> static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>> {
>> struct device *dev = &adev->dev;
>> @@ -160,6 +223,7 @@ static int tpdm_probe(struct amba_device *adev, const struct amba_id *id)
>> desc.ops = &tpdm_cs_ops;
>> desc.pdata = adev->dev.platform_data;
>> desc.dev = &adev->dev;
>> + desc.groups = tpdm_attr_grps;
>> drvdata->csdev = coresight_register(&desc);
>> if (IS_ERR(drvdata->csdev))
>> return PTR_ERR(drvdata->csdev);
>> diff --git a/drivers/hwtracing/coresight/coresight-tpdm.h b/drivers/hwtracing/coresight/coresight-tpdm.h
>> index 8f05070879c4..ea457ba5434e 100644
>> --- a/drivers/hwtracing/coresight/coresight-tpdm.h
>> +++ b/drivers/hwtracing/coresight/coresight-tpdm.h
>> @@ -12,6 +12,20 @@
>> /* DSB Subunit Registers */
>> #define TPDM_DSB_CR (0x780)
>>
>> +/* TPDM integration test registers */
>> +#define TPDM_ITATBCNTRL (0xEF0)
>> +#define TPDM_ITCNTRL (0xF00)
>> +
>> +/* Register value for integration test */
>> +#define ATBCNTRL_VAL_32 0xC00F1409
>> +#define ATBCNTRL_VAL_64 0xC01F1409
>> +
>> +/*
>> + * Number of cycles to write value when
>> + * integration test.
>> + */
>> +#define INTEGRATION_TEST_CYCLE 10
>> +
>> /**
>> * This enum is for PERIPHIDR0 register of TPDM.
>> * The fields [6:0] of PERIPHIDR0 are used to determine what
>> --
>> 2.17.1
>>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (4 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 05/10] coresight-tpdm: Add integration test support Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-19 9:25 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 07/10] Coresight: Add TPDA link driver Mao Jinlong
` (3 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add API usage document for sysfs API in TPDM driver.
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../ABI/testing/sysfs-bus-coresight-devices-tpdm | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
new file mode 100644
index 000000000000..d70ba429f38d
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
@@ -0,0 +1,13 @@
+What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
+Date: April 2022
+KernelVersion 5.18
+Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
+Description:
+ (Write) Run integration test for tpdm. Integration test
+ will generate test data for tpdm. It can help to make
+ sure that the trace path is enabled and the link configurations
+ are fine.
+
+ value to this sysfs node:
+ 1 : Genreate 64 bits data
+ 2 : Generate 32 bits data
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
2022-04-12 12:50 ` [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
@ 2022-04-19 9:25 ` Mike Leach
2022-04-20 14:42 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-19 9:25 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Add API usage document for sysfs API in TPDM driver.
>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> new file mode 100644
> index 000000000000..d70ba429f38d
> --- /dev/null
> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
> @@ -0,0 +1,13 @@
> +What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
> +Date: April 2022
> +KernelVersion 5.18
> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
> +Description:
> + (Write) Run integration test for tpdm. Integration test
> + will generate test data for tpdm. It can help to make
> + sure that the trace path is enabled and the link configurations
> + are fine.
> +
> + value to this sysfs node:
> + 1 : Genreate 64 bits data
s/Genreate/Generate
> + 2 : Generate 32 bits data
> --
> 2.17.1
>
Reviewed by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM
2022-04-19 9:25 ` Mike Leach
@ 2022-04-20 14:42 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-20 14:42 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
On 4/19/2022 5:25 PM, Mike Leach wrote:
> Hi
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> Add API usage document for sysfs API in TPDM driver.
>>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> .../ABI/testing/sysfs-bus-coresight-devices-tpdm | 13 +++++++++++++
>> 1 file changed, 13 insertions(+)
>> create mode 100644 Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>>
>> diff --git a/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>> new file mode 100644
>> index 000000000000..d70ba429f38d
>> --- /dev/null
>> +++ b/Documentation/ABI/testing/sysfs-bus-coresight-devices-tpdm
>> @@ -0,0 +1,13 @@
>> +What: /sys/bus/coresight/devices/<tpdm-name>/integration_test
>> +Date: April 2022
>> +KernelVersion 5.18
>> +Contact: Jinlong Mao (QUIC) <quic_jinlmao@quicinc.com>, Tao Zhang (QUIC) <quic_taozha@quicinc.com>
>> +Description:
>> + (Write) Run integration test for tpdm. Integration test
>> + will generate test data for tpdm. It can help to make
>> + sure that the trace path is enabled and the link configurations
>> + are fine.
>> +
>> + value to this sysfs node:
>> + 1 : Genreate 64 bits data
> s/Genreate/Generate
I will update this.
>
>> + 2 : Generate 32 bits data
>> --
>> 2.17.1
>>
> Reviewed by: Mike Leach <mike.leach@linaro.org>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 07/10] Coresight: Add TPDA link driver
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (5 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 06/10] docs: sysfs: coresight: Add sysfs ABI documentation for TPDM Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-19 9:51 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
` (2 subsequent siblings)
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
TPDA(Trace, Profiling and Diagnostics Aggregator) is
to provide packetization, funneling and timestamping of
TPDM data. Multiple monitors are connected to different
input ports of TPDA.This change is to add tpda
enable/disable/probe functions for coresight tpda driver.
- - - - - - - - - - - -
| TPDM 0| | TPDM 1 | | TPDM 2|
- - - - - - - - - - - -
| | |
|_ _ _ _ _ _ | _ _ _ _ |
| | |
| | |
------------------
| TPDA |
------------------
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
drivers/hwtracing/coresight/Kconfig | 11 ++
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++++++++++++++++
drivers/hwtracing/coresight/coresight-tpda.h | 32 ++++
4 files changed, 236 insertions(+)
create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 60248fef4089..317c5e7f4819 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST
operation to facilitate integration testing and software bringup
and/or to instrument topology discovery. The TPDM utilizes integration
mode to accomplish integration testing and software bringup.
+
+config CORESIGHT_TPDA
+ tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
+ help
+ This driver provides support for configuring aggregator. This is
+ primarily useful for pulling the data sets from one or more
+ attached monitors and pushing the resultant data out. Multiple
+ monitors are connected on different input ports of TPDA.
+
+ To compile this driver as a module, choose M here: the module will be
+ called coresight-tpda.
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index 6bb9b1746bc7..1712d82e7260 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
+obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o
coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
coresight-cti-sysfs.o
diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
new file mode 100644
index 000000000000..9519990c68e2
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpda.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#include <linux/amba/bus.h>
+#include <linux/bitmap.h>
+#include <linux/coresight.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/fs.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include "coresight-priv.h"
+#include "coresight-tpda.h"
+#include "coresight-trace-id.h"
+
+DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
+
+/* Settings pre enabling port control register */
+static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
+{
+ u32 val;
+
+ val = readl_relaxed(drvdata->base + TPDA_CR);
+ val |= (drvdata->atid << 6);
+ writel_relaxed(val, drvdata->base + TPDA_CR);
+}
+
+static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)
+{
+ u32 val;
+
+ val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
+ /* Enable the port */
+ val = val | BIT(0);
+ writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
+}
+
+static void _tpda_enable(struct tpda_drvdata *drvdata, int port)
+{
+ CS_UNLOCK(drvdata->base);
+
+ if (!drvdata->enable)
+ tpda_enable_pre_port(drvdata);
+
+ tpda_enable_port(drvdata, port);
+
+ CS_LOCK(drvdata->base);
+}
+
+static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ _tpda_enable(drvdata, inport);
+ drvdata->enable = true;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport);
+ return 0;
+}
+
+static void _tpda_disable(struct tpda_drvdata *drvdata, int port)
+{
+ u32 val;
+
+ CS_UNLOCK(drvdata->base);
+
+ val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
+ val = val & ~BIT(0);
+ writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
+
+ CS_LOCK(drvdata->base);
+}
+
+static void tpda_disable(struct coresight_device *csdev, int inport,
+ int outport)
+{
+ struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
+
+ mutex_lock(&drvdata->lock);
+ _tpda_disable(drvdata, inport);
+ drvdata->enable = false;
+ mutex_unlock(&drvdata->lock);
+
+ dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport);
+}
+
+static const struct coresight_ops_link tpda_link_ops = {
+ .enable = tpda_enable,
+ .disable = tpda_disable,
+};
+
+static const struct coresight_ops tpda_cs_ops = {
+ .link_ops = &tpda_link_ops,
+};
+
+static int tpda_init_default_data(struct tpda_drvdata *drvdata)
+{
+ int atid;
+ /*
+ * TPDA must has a unique atid. This atid can uniquely
+ * identify the TPDM trace source connect to the TPDA.
+ */
+ atid = coresight_trace_id_get_system_id(coresight_get_trace_id_map());
+ if (atid < 0)
+ return atid;
+
+ drvdata->atid = atid;
+ return 0;
+}
+
+static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ int ret;
+ struct device *dev = &adev->dev;
+ struct coresight_platform_data *pdata;
+ struct tpda_drvdata *drvdata;
+ struct coresight_desc desc = { 0 };
+
+ pdata = coresight_get_platform_data(dev);
+ if (IS_ERR(pdata))
+ return PTR_ERR(pdata);
+ adev->dev.platform_data = pdata;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ drvdata->dev = &adev->dev;
+ dev_set_drvdata(dev, drvdata);
+
+ drvdata->base = devm_ioremap_resource(dev, &adev->res);
+ if (!drvdata->base)
+ return -ENOMEM;
+
+ mutex_init(&drvdata->lock);
+
+ ret = tpda_init_default_data(drvdata);
+ if (ret)
+ return ret;
+
+ desc.name = coresight_alloc_device_name(&tpda_devs, dev);
+ if (!desc.name)
+ return -ENOMEM;
+ desc.type = CORESIGHT_DEV_TYPE_LINK;
+ desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
+ desc.ops = &tpda_cs_ops;
+ desc.pdata = adev->dev.platform_data;
+ desc.dev = &adev->dev;
+ drvdata->csdev = coresight_register(&desc);
+ if (IS_ERR(drvdata->csdev))
+ return PTR_ERR(drvdata->csdev);
+
+ pm_runtime_put(&adev->dev);
+
+ dev_dbg(drvdata->dev, "TPDA initialized\n");
+ return 0;
+}
+
+/*
+ * Different TPDA has different periph id.
+ * The difference is 0-7 bits' value. So ignore 0-7 bits.
+ */
+static struct amba_id tpda_ids[] = {
+ {
+ .id = 0x000f0f00,
+ .mask = 0x000fff00,
+ },
+ { 0, 0},
+};
+
+static struct amba_driver tpda_driver = {
+ .drv = {
+ .name = "coresight-tpda",
+ .owner = THIS_MODULE,
+ .suppress_bind_attrs = true,
+ },
+ .probe = tpda_probe,
+ .id_table = tpda_ids,
+};
+
+module_amba_driver(tpda_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver");
diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
new file mode 100644
index 000000000000..6ac33b9c1ea4
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-tpda.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _CORESIGHT_CORESIGHT_TPDA_H
+#define _CORESIGHT_CORESIGHT_TPDA_H
+
+#define TPDA_CR (0x000)
+#define TPDA_Pn_CR(n) (0x004 + (n * 4))
+
+#define TPDA_MAX_INPORTS 32
+
+/**
+ * struct tpda_drvdata - specifics associated to an TPDA component
+ * @base: memory mapped base address for this component.
+ * @dev: The device entity associated to this component.
+ * @csdev: component vitals needed by the framework.
+ * @lock: lock for the enable value.
+ * @enable: enable status of the component.
+ * @traceid: trace source identification for the data packet by TPDA.
+ */
+struct tpda_drvdata {
+ void __iomem *base;
+ struct device *dev;
+ struct coresight_device *csdev;
+ struct mutex lock;
+ bool enable;
+ u32 atid;
+};
+
+#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 07/10] Coresight: Add TPDA link driver
2022-04-12 12:50 ` [PATCH v5 07/10] Coresight: Add TPDA link driver Mao Jinlong
@ 2022-04-19 9:51 ` Mike Leach
2022-04-20 14:43 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-19 9:51 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> TPDA(Trace, Profiling and Diagnostics Aggregator) is
> to provide packetization, funneling and timestamping of
> TPDM data. Multiple monitors are connected to different
> input ports of TPDA.This change is to add tpda
> enable/disable/probe functions for coresight tpda driver.
>
> - - - - - - - - - - - -
> | TPDM 0| | TPDM 1 | | TPDM 2|
> - - - - - - - - - - - -
> | | |
> |_ _ _ _ _ _ | _ _ _ _ |
> | | |
> | | |
> ------------------
> | TPDA |
> ------------------
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> drivers/hwtracing/coresight/Kconfig | 11 ++
> drivers/hwtracing/coresight/Makefile | 1 +
> drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++++++++++++++++
> drivers/hwtracing/coresight/coresight-tpda.h | 32 ++++
> 4 files changed, 236 insertions(+)
> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index 60248fef4089..317c5e7f4819 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST
> operation to facilitate integration testing and software bringup
> and/or to instrument topology discovery. The TPDM utilizes integration
> mode to accomplish integration testing and software bringup.
> +
> +config CORESIGHT_TPDA
> + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
> + help
> + This driver provides support for configuring aggregator. This is
> + primarily useful for pulling the data sets from one or more
> + attached monitors and pushing the resultant data out. Multiple
> + monitors are connected on different input ports of TPDA.
> +
> + To compile this driver as a module, choose M here: the module will be
> + called coresight-tpda.
> endif
TDPA / TDPM are functionally linked - it does not make sense to
configure one without the other.
Kernel configuration should reflect this - as a minimum TDPM
configuration should select TDPA.
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 6bb9b1746bc7..1712d82e7260 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
> obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
> obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
> obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
> +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o
> coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
> coresight-cti-sysfs.o
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
> new file mode 100644
> index 000000000000..9519990c68e2
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
> @@ -0,0 +1,192 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#include <linux/amba/bus.h>
> +#include <linux/bitmap.h>
> +#include <linux/coresight.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/fs.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +
> +#include "coresight-priv.h"
> +#include "coresight-tpda.h"
> +#include "coresight-trace-id.h"
> +
> +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
> +
> +/* Settings pre enabling port control register */
> +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
> +{
> + u32 val;
> +
> + val = readl_relaxed(drvdata->base + TPDA_CR);
> + val |= (drvdata->atid << 6);
> + writel_relaxed(val, drvdata->base + TPDA_CR);
> +}
> +
> +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)
> +{
> + u32 val;
> +
> + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
> + /* Enable the port */
> + val = val | BIT(0);
#define a constant in the header to use here.
> + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
> +}
> +
> +static void _tpda_enable(struct tpda_drvdata *drvdata, int port)
> +{
> + CS_UNLOCK(drvdata->base);
> +
> + if (!drvdata->enable)
> + tpda_enable_pre_port(drvdata);
> +
> + tpda_enable_port(drvdata, port);
> +
> + CS_LOCK(drvdata->base);
> +}
> +
> +static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + _tpda_enable(drvdata, inport);
> + drvdata->enable = true;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport);
> + return 0;
> +}
> +
> +static void _tpda_disable(struct tpda_drvdata *drvdata, int port)
> +{
> + u32 val;
> +
> + CS_UNLOCK(drvdata->base);
> +
> + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
> + val = val & ~BIT(0);
use a #defined constant.
> + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
> +
> + CS_LOCK(drvdata->base);
> +}
> +
> +static void tpda_disable(struct coresight_device *csdev, int inport,
> + int outport)
> +{
> + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> +
> + mutex_lock(&drvdata->lock);
> + _tpda_disable(drvdata, inport);
> + drvdata->enable = false;
> + mutex_unlock(&drvdata->lock);
> +
> + dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport);
> +}
> +
> +static const struct coresight_ops_link tpda_link_ops = {
> + .enable = tpda_enable,
> + .disable = tpda_disable,
> +};
> +
> +static const struct coresight_ops tpda_cs_ops = {
> + .link_ops = &tpda_link_ops,
> +};
> +
> +static int tpda_init_default_data(struct tpda_drvdata *drvdata)
> +{
> + int atid;
> + /*
> + * TPDA must has a unique atid. This atid can uniquely
> + * identify the TPDM trace source connect to the TPDA.
> + */
> + atid = coresight_trace_id_get_system_id(coresight_get_trace_id_map());
> + if (atid < 0)
> + return atid;
> +
> + drvdata->atid = atid;
> + return 0;
> +}
> +
> +static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + int ret;
> + struct device *dev = &adev->dev;
> + struct coresight_platform_data *pdata;
> + struct tpda_drvdata *drvdata;
> + struct coresight_desc desc = { 0 };
> +
> + pdata = coresight_get_platform_data(dev);
> + if (IS_ERR(pdata))
> + return PTR_ERR(pdata);
> + adev->dev.platform_data = pdata;
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> +
> + drvdata->dev = &adev->dev;
> + dev_set_drvdata(dev, drvdata);
> +
> + drvdata->base = devm_ioremap_resource(dev, &adev->res);
> + if (!drvdata->base)
> + return -ENOMEM;
> +
> + mutex_init(&drvdata->lock);
> +
> + ret = tpda_init_default_data(drvdata);
> + if (ret)
> + return ret;
> +
> + desc.name = coresight_alloc_device_name(&tpda_devs, dev);
> + if (!desc.name)
> + return -ENOMEM;
> + desc.type = CORESIGHT_DEV_TYPE_LINK;
> + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
> + desc.ops = &tpda_cs_ops;
> + desc.pdata = adev->dev.platform_data;
> + desc.dev = &adev->dev;
> + drvdata->csdev = coresight_register(&desc);
> + if (IS_ERR(drvdata->csdev))
> + return PTR_ERR(drvdata->csdev);
> +
> + pm_runtime_put(&adev->dev);
> +
> + dev_dbg(drvdata->dev, "TPDA initialized\n");
> + return 0;
> +}
> +
> +/*
> + * Different TPDA has different periph id.
> + * The difference is 0-7 bits' value. So ignore 0-7 bits.
> + */
> +static struct amba_id tpda_ids[] = {
> + {
> + .id = 0x000f0f00,
> + .mask = 0x000fff00,
> + },
> + { 0, 0},
> +};
> +
> +static struct amba_driver tpda_driver = {
> + .drv = {
> + .name = "coresight-tpda",
> + .owner = THIS_MODULE,
> + .suppress_bind_attrs = true,
> + },
> + .probe = tpda_probe,
> + .id_table = tpda_ids,
> +};
> +
There is no code to release resources when this module is unloaded.
You need a .remove function, that as a minimum calls
coresight_unregister().
Regards
Mike
> +module_amba_driver(tpda_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver");
> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
> new file mode 100644
> index 000000000000..6ac33b9c1ea4
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
> @@ -0,0 +1,32 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +#ifndef _CORESIGHT_CORESIGHT_TPDA_H
> +#define _CORESIGHT_CORESIGHT_TPDA_H
> +
> +#define TPDA_CR (0x000)
> +#define TPDA_Pn_CR(n) (0x004 + (n * 4))
> +
> +#define TPDA_MAX_INPORTS 32
> +
> +/**
> + * struct tpda_drvdata - specifics associated to an TPDA component
> + * @base: memory mapped base address for this component.
> + * @dev: The device entity associated to this component.
> + * @csdev: component vitals needed by the framework.
> + * @lock: lock for the enable value.
> + * @enable: enable status of the component.
> + * @traceid: trace source identification for the data packet by TPDA.
> + */
> +struct tpda_drvdata {
> + void __iomem *base;
> + struct device *dev;
> + struct coresight_device *csdev;
> + struct mutex lock;
> + bool enable;
> + u32 atid;
> +};
> +
> +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 07/10] Coresight: Add TPDA link driver
2022-04-19 9:51 ` Mike Leach
@ 2022-04-20 14:43 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-20 14:43 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi Mike,
On 4/19/2022 5:51 PM, Mike Leach wrote:
> Hi
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> TPDA(Trace, Profiling and Diagnostics Aggregator) is
>> to provide packetization, funneling and timestamping of
>> TPDM data. Multiple monitors are connected to different
>> input ports of TPDA.This change is to add tpda
>> enable/disable/probe functions for coresight tpda driver.
>>
>> - - - - - - - - - - - -
>> | TPDM 0| | TPDM 1 | | TPDM 2|
>> - - - - - - - - - - - -
>> | | |
>> |_ _ _ _ _ _ | _ _ _ _ |
>> | | |
>> | | |
>> ------------------
>> | TPDA |
>> ------------------
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> drivers/hwtracing/coresight/Kconfig | 11 ++
>> drivers/hwtracing/coresight/Makefile | 1 +
>> drivers/hwtracing/coresight/coresight-tpda.c | 192 +++++++++++++++++++
>> drivers/hwtracing/coresight/coresight-tpda.h | 32 ++++
>> 4 files changed, 236 insertions(+)
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.c
>> create mode 100644 drivers/hwtracing/coresight/coresight-tpda.h
>>
>> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
>> index 60248fef4089..317c5e7f4819 100644
>> --- a/drivers/hwtracing/coresight/Kconfig
>> +++ b/drivers/hwtracing/coresight/Kconfig
>> @@ -223,4 +223,15 @@ config CORESIGHT_TPDM_INTEGRATION_TEST
>> operation to facilitate integration testing and software bringup
>> and/or to instrument topology discovery. The TPDM utilizes integration
>> mode to accomplish integration testing and software bringup.
>> +
>> +config CORESIGHT_TPDA
>> + tristate "CoreSight Trace, Profiling & Diagnostics Aggregator driver"
>> + help
>> + This driver provides support for configuring aggregator. This is
>> + primarily useful for pulling the data sets from one or more
>> + attached monitors and pushing the resultant data out. Multiple
>> + monitors are connected on different input ports of TPDA.
>> +
>> + To compile this driver as a module, choose M here: the module will be
>> + called coresight-tpda.
>> endif
> TDPA / TDPM are functionally linked - it does not make sense to
> configure one without the other.
> Kernel configuration should reflect this - as a minimum TDPM
> configuration should select TDPA.
>
>
>
>> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
>> index 6bb9b1746bc7..1712d82e7260 100644
>> --- a/drivers/hwtracing/coresight/Makefile
>> +++ b/drivers/hwtracing/coresight/Makefile
>> @@ -26,5 +26,6 @@ obj-$(CONFIG_CORESIGHT_CATU) += coresight-catu.o
>> obj-$(CONFIG_CORESIGHT_CTI) += coresight-cti.o
>> obj-$(CONFIG_CORESIGHT_TRBE) += coresight-trbe.o
>> obj-$(CONFIG_CORESIGHT_TPDM) += coresight-tpdm.o
>> +obj-$(CONFIG_CORESIGHT_TPDA) += coresight-tpda.o
>> coresight-cti-y := coresight-cti-core.o coresight-cti-platform.o \
>> coresight-cti-sysfs.o
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.c b/drivers/hwtracing/coresight/coresight-tpda.c
>> new file mode 100644
>> index 000000000000..9519990c68e2
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.c
>> @@ -0,0 +1,192 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#include <linux/amba/bus.h>
>> +#include <linux/bitmap.h>
>> +#include <linux/coresight.h>
>> +#include <linux/device.h>
>> +#include <linux/err.h>
>> +#include <linux/fs.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/platform_device.h>
>> +
>> +#include "coresight-priv.h"
>> +#include "coresight-tpda.h"
>> +#include "coresight-trace-id.h"
>> +
>> +DEFINE_CORESIGHT_DEVLIST(tpda_devs, "tpda");
>> +
>> +/* Settings pre enabling port control register */
>> +static void tpda_enable_pre_port(struct tpda_drvdata *drvdata)
>> +{
>> + u32 val;
>> +
>> + val = readl_relaxed(drvdata->base + TPDA_CR);
>> + val |= (drvdata->atid << 6);
>> + writel_relaxed(val, drvdata->base + TPDA_CR);
>> +}
>> +
>> +static void tpda_enable_port(struct tpda_drvdata *drvdata, int port)
>> +{
>> + u32 val;
>> +
>> + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
>> + /* Enable the port */
>> + val = val | BIT(0);
> #define a constant in the header to use here.
I will update it.
>
>> + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
>> +}
>> +
>> +static void _tpda_enable(struct tpda_drvdata *drvdata, int port)
>> +{
>> + CS_UNLOCK(drvdata->base);
>> +
>> + if (!drvdata->enable)
>> + tpda_enable_pre_port(drvdata);
>> +
>> + tpda_enable_port(drvdata, port);
>> +
>> + CS_LOCK(drvdata->base);
>> +}
>> +
>> +static int tpda_enable(struct coresight_device *csdev, int inport, int outport)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> + mutex_lock(&drvdata->lock);
>> + _tpda_enable(drvdata, inport);
>> + drvdata->enable = true;
>> + mutex_unlock(&drvdata->lock);
>> +
>> + dev_info(drvdata->dev, "TPDA inport %d enabled\n", inport);
>> + return 0;
>> +}
>> +
>> +static void _tpda_disable(struct tpda_drvdata *drvdata, int port)
>> +{
>> + u32 val;
>> +
>> + CS_UNLOCK(drvdata->base);
>> +
>> + val = readl_relaxed(drvdata->base + TPDA_Pn_CR(port));
>> + val = val & ~BIT(0);
> use a #defined constant.
>
>> + writel_relaxed(val, drvdata->base + TPDA_Pn_CR(port));
>> +
>> + CS_LOCK(drvdata->base);
>> +}
>> +
>> +static void tpda_disable(struct coresight_device *csdev, int inport,
>> + int outport)
>> +{
>> + struct tpda_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
>> +
>> + mutex_lock(&drvdata->lock);
>> + _tpda_disable(drvdata, inport);
>> + drvdata->enable = false;
>> + mutex_unlock(&drvdata->lock);
>> +
>> + dev_info(drvdata->dev, "TPDA inport %d disabled\n", inport);
>> +}
>> +
>> +static const struct coresight_ops_link tpda_link_ops = {
>> + .enable = tpda_enable,
>> + .disable = tpda_disable,
>> +};
>> +
>> +static const struct coresight_ops tpda_cs_ops = {
>> + .link_ops = &tpda_link_ops,
>> +};
>> +
>> +static int tpda_init_default_data(struct tpda_drvdata *drvdata)
>> +{
>> + int atid;
>> + /*
>> + * TPDA must has a unique atid. This atid can uniquely
>> + * identify the TPDM trace source connect to the TPDA.
>> + */
>> + atid = coresight_trace_id_get_system_id(coresight_get_trace_id_map());
>> + if (atid < 0)
>> + return atid;
>> +
>> + drvdata->atid = atid;
>> + return 0;
>> +}
>> +
>> +static int tpda_probe(struct amba_device *adev, const struct amba_id *id)
>> +{
>> + int ret;
>> + struct device *dev = &adev->dev;
>> + struct coresight_platform_data *pdata;
>> + struct tpda_drvdata *drvdata;
>> + struct coresight_desc desc = { 0 };
>> +
>> + pdata = coresight_get_platform_data(dev);
>> + if (IS_ERR(pdata))
>> + return PTR_ERR(pdata);
>> + adev->dev.platform_data = pdata;
>> +
>> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
>> + if (!drvdata)
>> + return -ENOMEM;
>> +
>> + drvdata->dev = &adev->dev;
>> + dev_set_drvdata(dev, drvdata);
>> +
>> + drvdata->base = devm_ioremap_resource(dev, &adev->res);
>> + if (!drvdata->base)
>> + return -ENOMEM;
>> +
>> + mutex_init(&drvdata->lock);
>> +
>> + ret = tpda_init_default_data(drvdata);
>> + if (ret)
>> + return ret;
>> +
>> + desc.name = coresight_alloc_device_name(&tpda_devs, dev);
>> + if (!desc.name)
>> + return -ENOMEM;
>> + desc.type = CORESIGHT_DEV_TYPE_LINK;
>> + desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_MERG;
>> + desc.ops = &tpda_cs_ops;
>> + desc.pdata = adev->dev.platform_data;
>> + desc.dev = &adev->dev;
>> + drvdata->csdev = coresight_register(&desc);
>> + if (IS_ERR(drvdata->csdev))
>> + return PTR_ERR(drvdata->csdev);
>> +
>> + pm_runtime_put(&adev->dev);
>> +
>> + dev_dbg(drvdata->dev, "TPDA initialized\n");
>> + return 0;
>> +}
>> +
>> +/*
>> + * Different TPDA has different periph id.
>> + * The difference is 0-7 bits' value. So ignore 0-7 bits.
>> + */
>> +static struct amba_id tpda_ids[] = {
>> + {
>> + .id = 0x000f0f00,
>> + .mask = 0x000fff00,
>> + },
>> + { 0, 0},
>> +};
>> +
>> +static struct amba_driver tpda_driver = {
>> + .drv = {
>> + .name = "coresight-tpda",
>> + .owner = THIS_MODULE,
>> + .suppress_bind_attrs = true,
>> + },
>> + .probe = tpda_probe,
>> + .id_table = tpda_ids,
>> +};
>> +
> There is no code to release resources when this module is unloaded.
> You need a .remove function, that as a minimum calls
> coresight_unregister().
>
> Regards
>
> Mike
Yes. Need add remove function for tpda driver.
>
>> +module_amba_driver(tpda_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_DESCRIPTION("Trace, Profiling & Diagnostic Aggregator driver");
>> diff --git a/drivers/hwtracing/coresight/coresight-tpda.h b/drivers/hwtracing/coresight/coresight-tpda.h
>> new file mode 100644
>> index 000000000000..6ac33b9c1ea4
>> --- /dev/null
>> +++ b/drivers/hwtracing/coresight/coresight-tpda.h
>> @@ -0,0 +1,32 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> + */
>> +
>> +#ifndef _CORESIGHT_CORESIGHT_TPDA_H
>> +#define _CORESIGHT_CORESIGHT_TPDA_H
>> +
>> +#define TPDA_CR (0x000)
>> +#define TPDA_Pn_CR(n) (0x004 + (n * 4))
>> +
>> +#define TPDA_MAX_INPORTS 32
>> +
>> +/**
>> + * struct tpda_drvdata - specifics associated to an TPDA component
>> + * @base: memory mapped base address for this component.
>> + * @dev: The device entity associated to this component.
>> + * @csdev: component vitals needed by the framework.
>> + * @lock: lock for the enable value.
>> + * @enable: enable status of the component.
>> + * @traceid: trace source identification for the data packet by TPDA.
>> + */
>> +struct tpda_drvdata {
>> + void __iomem *base;
>> + struct device *dev;
>> + struct coresight_device *csdev;
>> + struct mutex lock;
>> + bool enable;
>> + u32 atid;
>> +};
>> +
>> +#endif /* _CORESIGHT_CORESIGHT_TPDA_H */
>> --
>> 2.17.1
>>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (6 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 07/10] Coresight: Add TPDA link driver Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-19 8:32 ` Mike Leach
2022-04-12 12:50 ` [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
2022-04-12 12:50 ` [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250 Mao Jinlong
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Adds new coresight-tpda.yaml file describing the bindings required
to define tpda in the device trees.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++
1 file changed, 119 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
new file mode 100644
index 000000000000..2c79de0a7928
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
@@ -0,0 +1,119 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Trace, Profiling and Diagnostics Aggregator - TPDA
+
+description: |
+ TPDAs are responsible for packetization and timestamping of data sets
+ utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
+ more attached TPDM and pushing the resultant (packetized) data out a
+ master ATB interface. Performing an arbitrated ATB interleaving (funneling)
+ task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
+
+maintainers:
+ - Suzuki K Poulose <suzuki.poulose@arm.com>
+ - Mathieu Poirier <mathieu.poirier@linaro.org>
+
+properties:
+ $nodename:
+ pattern: "^tpda(@[0-9a-f]+)$"
+ compatible:
+ items:
+ - const: qcom,coresight-tpda
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: apb_pclk
+
+ in-ports:
+ type: object
+ description: |
+ Input connections from TPDM to TPDA
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ patternProperties:
+ "^port@[0-9a-f]+$":
+ type: object
+ required:
+ - reg
+
+ required:
+ - '#size-cells'
+ - '#address-cells'
+
+ out-ports:
+ type: object
+ description: |
+ Output connections from the TPDA to legacy CoreSight trace bus.
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port:
+ description:
+ Output connection from the TPDA to legacy CoreSight Trace bus.
+ $ref: /schemas/graph.yaml#/properties/port
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - in-ports
+ - out-ports
+
+additionalProperties: false
+
+examples:
+ # minimum tpda definition.
+ - |
+ tpda@6004000 {
+ compatible = "qcom,coresight-tpda", "arm,primecell";
+ reg = <0x6004000 0x1000>;
+
+ qcom,tpda-atid = <65>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ tpda_qdss_0_in_tpdm_dcc: endpoint {
+ remote-endpoint =
+ <&tpdm_dcc_out_tpda_qdss_0>;
+ };
+ };
+ };
+
+ out-ports {
+ port {
+ tpda_qdss_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_tpda_qdss>;
+ };
+ };
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions
2022-04-12 12:50 ` [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
@ 2022-04-19 8:32 ` Mike Leach
2022-04-20 14:37 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-19 8:32 UTC (permalink / raw)
To: Mao Jinlong
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
Hi
On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>
> Adds new coresight-tpda.yaml file describing the bindings required
> to define tpda in the device trees.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++
> 1 file changed, 119 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
> new file mode 100644
> index 000000000000..2c79de0a7928
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
> @@ -0,0 +1,119 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Trace, Profiling and Diagnostics Aggregator - TPDA
> +
> +description: |
> + TPDAs are responsible for packetization and timestamping of data sets
> + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
> + more attached TPDM and pushing the resultant (packetized) data out a
> + master ATB interface. Performing an arbitrated ATB interleaving (funneling)
> + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
> +
> +maintainers:
> + - Suzuki K Poulose <suzuki.poulose@arm.com>
> + - Mathieu Poirier <mathieu.poirier@linaro.org>
> +
as mentioned in patch 03 - these should be bindings maintainers.
with the above change
Reviewed by: Mike Leach <mike.leach@linaro.org>
> +properties:
> + $nodename:
> + pattern: "^tpda(@[0-9a-f]+)$"
> + compatible:
> + items:
> + - const: qcom,coresight-tpda
> + - const: arm,primecell
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> +
> + clock-names:
> + items:
> + - const: apb_pclk
> +
> + in-ports:
> + type: object
> + description: |
> + Input connections from TPDM to TPDA
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
> +
> + patternProperties:
> + "^port@[0-9a-f]+$":
> + type: object
> + required:
> + - reg
> +
> + required:
> + - '#size-cells'
> + - '#address-cells'
> +
> + out-ports:
> + type: object
> + description: |
> + Output connections from the TPDA to legacy CoreSight trace bus.
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port:
> + description:
> + Output connection from the TPDA to legacy CoreSight Trace bus.
> + $ref: /schemas/graph.yaml#/properties/port
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - in-ports
> + - out-ports
> +
> +additionalProperties: false
> +
> +examples:
> + # minimum tpda definition.
> + - |
> + tpda@6004000 {
> + compatible = "qcom,coresight-tpda", "arm,primecell";
> + reg = <0x6004000 0x1000>;
> +
> + qcom,tpda-atid = <65>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + tpda_qdss_0_in_tpdm_dcc: endpoint {
> + remote-endpoint =
> + <&tpdm_dcc_out_tpda_qdss_0>;
> + };
> + };
> + };
> +
> + out-ports {
> + port {
> + tpda_qdss_out_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel_in0_in_tpda_qdss>;
> + };
> + };
> + };
> + };
> +
> +...
> --
> 2.17.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions
2022-04-19 8:32 ` Mike Leach
@ 2022-04-20 14:37 ` Jinlong Mao
0 siblings, 0 replies; 31+ messages in thread
From: Jinlong Mao @ 2022-04-20 14:37 UTC (permalink / raw)
To: Mike Leach
Cc: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin, Leo Yan,
Greg Kroah-Hartman, coresight, linux-arm-kernel, linux-kernel,
Tingwei Zhang, Yuanfang Zhang, Tao Zhang, Trilok Soni, Hao Zhang,
linux-arm-msm
On 4/19/2022 4:32 PM, Mike Leach wrote:
> Hi
>
> On Tue, 12 Apr 2022 at 13:51, Mao Jinlong <quic_jinlmao@quicinc.com> wrote:
>> Adds new coresight-tpda.yaml file describing the bindings required
>> to define tpda in the device trees.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> .../bindings/arm/coresight-tpda.yaml | 119 ++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight-tpda.yaml b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>> new file mode 100644
>> index 000000000000..2c79de0a7928
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/coresight-tpda.yaml
>> @@ -0,0 +1,119 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +# Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/coresight-tpda.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Trace, Profiling and Diagnostics Aggregator - TPDA
>> +
>> +description: |
>> + TPDAs are responsible for packetization and timestamping of data sets
>> + utilizing the MIPI STPv2 packet protocol. Pulling data sets from one or
>> + more attached TPDM and pushing the resultant (packetized) data out a
>> + master ATB interface. Performing an arbitrated ATB interleaving (funneling)
>> + task for free-flowing data from TPDM (i.e. CMB and DSB data set flows).
>> +
>> +maintainers:
>> + - Suzuki K Poulose <suzuki.poulose@arm.com>
>> + - Mathieu Poirier <mathieu.poirier@linaro.org>
>> +
> as mentioned in patch 03 - these should be bindings maintainers.
>
> with the above change
>
> Reviewed by: Mike Leach <mike.leach@linaro.org>
>
>
Thank you Mike. I will address the comments in next version.
>
>> +properties:
>> + $nodename:
>> + pattern: "^tpda(@[0-9a-f]+)$"
>> + compatible:
>> + items:
>> + - const: qcom,coresight-tpda
>> + - const: arm,primecell
>> +
>> + reg:
>> + maxItems: 1
>> +
>> + clocks:
>> + maxItems: 1
>> +
>> + clock-names:
>> + items:
>> + - const: apb_pclk
>> +
>> + in-ports:
>> + type: object
>> + description: |
>> + Input connections from TPDM to TPDA
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + properties:
>> + '#address-cells':
>> + const: 1
>> +
>> + '#size-cells':
>> + const: 0
>> +
>> + patternProperties:
>> + "^port@[0-9a-f]+$":
>> + type: object
>> + required:
>> + - reg
>> +
>> + required:
>> + - '#size-cells'
>> + - '#address-cells'
>> +
>> + out-ports:
>> + type: object
>> + description: |
>> + Output connections from the TPDA to legacy CoreSight trace bus.
>> + $ref: /schemas/graph.yaml#/properties/ports
>> +
>> + properties:
>> + port:
>> + description:
>> + Output connection from the TPDA to legacy CoreSight Trace bus.
>> + $ref: /schemas/graph.yaml#/properties/port
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - clocks
>> + - clock-names
>> + - in-ports
>> + - out-ports
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + # minimum tpda definition.
>> + - |
>> + tpda@6004000 {
>> + compatible = "qcom,coresight-tpda", "arm,primecell";
>> + reg = <0x6004000 0x1000>;
>> +
>> + qcom,tpda-atid = <65>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + tpda_qdss_0_in_tpdm_dcc: endpoint {
>> + remote-endpoint =
>> + <&tpdm_dcc_out_tpda_qdss_0>;
>> + };
>> + };
>> + };
>> +
>> + out-ports {
>> + port {
>> + tpda_qdss_out_funnel_in0: endpoint {
>> + remote-endpoint =
>> + <&funnel_in0_in_tpda_qdss>;
>> + };
>> + };
>> + };
>> + };
>> +
>> +...
>> --
>> 2.17.1
>>
>
> --
> Mike Leach
> Principal Engineer, ARM Ltd.
> Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (7 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 08/10] dt-bindings: arm: Adds CoreSight TPDA hardware definitions Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-13 9:58 ` Konrad Dybcio
2022-04-12 12:50 ` [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250 Mao Jinlong
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add coresight device tree for sm8250. STM/ETM are added.
Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++
arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
2 files changed, 528 insertions(+)
create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
new file mode 100644
index 000000000000..1de42fd39248
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+&soc {
+
+ stm@6002000 {
+ compatible = "arm,coresight-stm", "arm,primecell";
+ reg = <0 0x06002000 0 0x1000>,
+ <0 0x16280000 0 0x180000>;
+ reg-names = "stm-base", "stm-stimulus-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ stm_out: endpoint {
+ remote-endpoint =
+ <&funnel0_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@6041000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06041000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel0_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in0>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel0_in7: endpoint {
+ remote-endpoint = <&stm_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6042000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06042000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel2_out: endpoint {
+ remote-endpoint =
+ <&merge_funnel_in2>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <4>;
+ funnel2_in5: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ funnel@6b04000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ arm,primecell-periphid = <0x000bb908>;
+
+ reg = <0 0x6b04000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&etf_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@7 {
+ reg = <7>;
+ funnel_swao_in_funnel_merg: endpoint {
+ remote-endpoint=
+ <&funnel_merg_out_funnel_swao>;
+ };
+ };
+ };
+
+ };
+
+ funnel@6045000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x06045000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_merg_out_funnel_swao: endpoint {
+ remote-endpoint = <&funnel_swao_in_funnel_merg>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0>;
+ merge_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel0_out>;
+ };
+ };
+
+ port@2 {
+ reg = <1>;
+ merge_funnel_in2: endpoint {
+ remote-endpoint =
+ <&funnel2_out>;
+ };
+ };
+ };
+ };
+
+ replicator@6046000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06046000 0 0x1000>;
+
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_out: endpoint {
+ remote-endpoint = <&etr_in>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_cx_in_swao_out: endpoint {
+ remote-endpoint = <&replicator_swao_out_cx_in>;
+ };
+ };
+ };
+ };
+
+ replicator@6b06000 {
+ compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
+ reg = <0 0x06b06000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ replicator_swao_out_cx_in: endpoint {
+ remote-endpoint = <&replicator_cx_in_swao_out>;
+ };
+ };
+ };
+
+ in-ports {
+ port {
+ replicator_in: endpoint {
+ remote-endpoint = <&etf_out>;
+ };
+ };
+ };
+ };
+
+ etf@6b05000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x6b05000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ etf_out: endpoint {
+ remote-endpoint =
+ <&replicator_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <0>;
+ etf_in: endpoint {
+ remote-endpoint =
+ <&merge_funnel_out>;
+ };
+ };
+ };
+ };
+
+ etr@6048000 {
+ compatible = "arm,coresight-tmc", "arm,primecell";
+ reg = <0 0x06048000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,scatter-gather;
+
+ in-ports {
+ port {
+ etr_in: endpoint {
+ remote-endpoint =
+ <&replicator_out>;
+ };
+ };
+ };
+ };
+
+ etm@7040000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07040000 0 0x1000>;
+
+ cpu = <&CPU0>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm0_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in0>;
+ };
+ };
+ };
+ };
+
+ etm@7140000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07140000 0 0x1000>;
+
+ cpu = <&CPU1>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm1_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in1>;
+ };
+ };
+ };
+ };
+
+ etm@7240000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07240000 0 0x1000>;
+
+ cpu = <&CPU2>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm2_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in2>;
+ };
+ };
+ };
+ };
+
+ etm@7340000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07340000 0 0x1000>;
+
+ cpu = <&CPU3>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm3_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in3>;
+ };
+ };
+ };
+ };
+
+ etm@7440000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07440000 0 0x1000>;
+
+ cpu = <&CPU4>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm4_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in4>;
+ };
+ };
+ };
+ };
+
+ etm@7540000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07540000 0 0x1000>;
+
+ cpu = <&CPU5>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm5_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in5>;
+ };
+ };
+ };
+ };
+
+ etm@7640000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07640000 0 0x1000>;
+
+ cpu = <&CPU6>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm6_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in6>;
+ };
+ };
+ };
+ };
+
+ etm@7740000 {
+ compatible = "arm,coresight-etm4x", "arm,primecell";
+ reg = <0 0x07740000 0 0x1000>;
+
+ cpu = <&CPU7>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+ arm,coresight-loses-context-with-cpu;
+
+ out-ports {
+ port {
+ etm7_out: endpoint {
+ remote-endpoint =
+ <&apss_funnel_in7>;
+ };
+ };
+ };
+ };
+
+ funnel@7800000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07800000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_funnel_out: endpoint {
+ remote-endpoint =
+ <&apss_merge_funnel_in>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ apss_funnel_in0: endpoint {
+ remote-endpoint =
+ <&etm0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ apss_funnel_in1: endpoint {
+ remote-endpoint =
+ <&etm1_out>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ apss_funnel_in2: endpoint {
+ remote-endpoint =
+ <&etm2_out>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ apss_funnel_in3: endpoint {
+ remote-endpoint =
+ <&etm3_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ apss_funnel_in4: endpoint {
+ remote-endpoint =
+ <&etm4_out>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+ apss_funnel_in5: endpoint {
+ remote-endpoint =
+ <&etm5_out>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+ apss_funnel_in6: endpoint {
+ remote-endpoint =
+ <&etm6_out>;
+ };
+ };
+
+ port@7 {
+ reg = <7>;
+ apss_funnel_in7: endpoint {
+ remote-endpoint =
+ <&etm7_out>;
+ };
+ };
+ };
+ };
+
+ funnel@7810000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+ reg = <0 0x07810000 0 0x1000>;
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ apss_merge_funnel_out: endpoint {
+ remote-endpoint =
+ <&funnel2_in5>;
+ };
+ };
+ };
+
+ in-ports {
+ port@1 {
+ reg = <0>;
+ apss_merge_funnel_in: endpoint {
+ remote-endpoint =
+ <&apss_funnel_out>;
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index af8f22636436..115623392183 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -5434,3 +5434,5 @@
};
};
};
+
+#include "sm8250-coresight.dtsi"
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-12 12:50 ` [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
@ 2022-04-13 9:58 ` Konrad Dybcio
2022-04-13 16:45 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Konrad Dybcio @ 2022-04-13 9:58 UTC (permalink / raw)
To: Mao Jinlong, Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm,
Bjorn Andersson
Hi,
I added Bjorn, the linux-arm-msm maintainer to CC as he was missing for
some reason.
On 12/04/2022 14:50, Mao Jinlong wrote:
> Add coresight device tree for sm8250. STM/ETM are added.
>
> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
> 2 files changed, 528 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> new file mode 100644
> index 000000000000..1de42fd39248
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> @@ -0,0 +1,526 @@
> +// SPDX-License-Identifier: GPL-2.0
sm8250.dtsi is BSD-3-Clause. Please consider relicensing.
> +/*
> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
> + */
> +
> +&soc {
> +
> + stm@6002000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x06002000 0 0x1000>,
You don't need to break the line at so few characters.
> + <0 0x16280000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + stm_out: endpoint {
> + remote-endpoint =
> + <&funnel0_in7>;
Same here.
> + };
> + };
> + };
> + };
> +
> + funnel@6041000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06041000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel0_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in0>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel0_in7: endpoint {
> + remote-endpoint = <&stm_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6042000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06042000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel2_out: endpoint {
> + remote-endpoint =
> + <&merge_funnel_in2>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@2 {
> + reg = <4>;
> + funnel2_in5: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + funnel@6b04000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + arm,primecell-periphid = <0x000bb908>;
> +
> + reg = <0 0x6b04000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&etf_in>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@7 {
> + reg = <7>;
> + funnel_swao_in_funnel_merg: endpoint {
> + remote-endpoint=
And here.
> + <&funnel_merg_out_funnel_swao>;
> + };
> + };
> + };
> +
> + };
> +
> + funnel@6045000 {
The nodes are not sorted properly (by address). Please fix that.
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x06045000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_merg_out_funnel_swao: endpoint {
> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <0>;
> + merge_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel0_out>;
> + };
> + };
> +
> + port@2 {
> + reg = <1>;
> + merge_funnel_in2: endpoint {
> + remote-endpoint =
> + <&funnel2_out>;
> + };
> + };
> + };
> + };
> +
> + replicator@6046000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0 0x06046000 0 0x1000>;
> +
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + replicator_out: endpoint {
> + remote-endpoint = <&etr_in>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_cx_in_swao_out: endpoint {
> + remote-endpoint = <&replicator_swao_out_cx_in>;
> + };
> + };
> + };
> + };
> +
> + replicator@6b06000 {
> + compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
> + reg = <0 0x06b06000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + replicator_swao_out_cx_in: endpoint {
> + remote-endpoint = <&replicator_cx_in_swao_out>;
> + };
> + };
> + };
> +
> + in-ports {
> + port {
> + replicator_in: endpoint {
> + remote-endpoint = <&etf_out>;
> + };
> + };
> + };
> + };
> +
> + etf@6b05000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x6b05000 0 0x1000>;
Please pad the address to 8 chars.
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + etf_out: endpoint {
> + remote-endpoint =
> + <&replicator_in>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <0>;
> + etf_in: endpoint {
> + remote-endpoint =
> + <&merge_funnel_out>;
> + };
> + };
> + };
> + };
> +
> + etr@6048000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x06048000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,scatter-gather;
> +
> + in-ports {
> + port {
> + etr_in: endpoint {
> + remote-endpoint =
> + <&replicator_out>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7040000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07040000 0 0x1000>;
> +
> + cpu = <&CPU0>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in0>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7140000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07140000 0 0x1000>;
> +
> + cpu = <&CPU1>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in1>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7240000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07240000 0 0x1000>;
> +
> + cpu = <&CPU2>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in2>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7340000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07340000 0 0x1000>;
> +
> + cpu = <&CPU3>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in3>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07440000 0 0x1000>;
> +
> + cpu = <&CPU4>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in4>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07540000 0 0x1000>;
> +
> + cpu = <&CPU5>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in5>;
And here.
> + };
> + };
> + };
> + };
> +
> + etm@7640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07640000 0 0x1000>;
> +
> + cpu = <&CPU6>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in6>;
> + };
> + };
> + };
> + };
> +
> + etm@7740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x07740000 0 0x1000>;
> +
> + cpu = <&CPU7>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> + arm,coresight-loses-context-with-cpu;
> +
> + out-ports {
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&apss_funnel_in7>;
And here.
> + };
> + };
> + };
> + };
> +
> + funnel@7800000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x07800000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + apss_funnel_out: endpoint {
> + remote-endpoint =
> + <&apss_merge_funnel_in>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + apss_funnel_in0: endpoint {
> + remote-endpoint =
> + <&etm0_out>;
And here.
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + apss_funnel_in1: endpoint {
> + remote-endpoint =
> + <&etm1_out>;
And here.
> + };
> + };
> +
> + port@2 {
> + reg = <2>;
> + apss_funnel_in2: endpoint {
> + remote-endpoint =
> + <&etm2_out>;
And here.
> + };
> + };
> +
> + port@3 {
> + reg = <3>;
> + apss_funnel_in3: endpoint {
> + remote-endpoint =
> + <&etm3_out>;
And here.
> + };
> + };
> +
> + port@4 {
> + reg = <4>;
> + apss_funnel_in4: endpoint {
> + remote-endpoint =
> + <&etm4_out>;
And here.
> + };
> + };
> +
> + port@5 {
> + reg = <5>;
> + apss_funnel_in5: endpoint {
> + remote-endpoint =
> + <&etm5_out>;
And here.
> + };
> + };
> +
> + port@6 {
> + reg = <6>;
> + apss_funnel_in6: endpoint {
> + remote-endpoint =
> + <&etm6_out>;
And here.
> + };
> + };
> +
> + port@7 {
> + reg = <7>;
> + apss_funnel_in7: endpoint {
> + remote-endpoint =
> + <&etm7_out>;
And here.
> + };
> + };
> + };
> + };
> +
> + funnel@7810000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> + reg = <0 0x07810000 0 0x1000>;
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + apss_merge_funnel_out: endpoint {
> + remote-endpoint =
> + <&funnel2_in5>;
And here.
> + };
> + };
> + };
> +
> + in-ports {
> + port@1 {
> + reg = <0>;
> + apss_merge_funnel_in: endpoint {
> + remote-endpoint =
> + <&apss_funnel_out>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index af8f22636436..115623392183 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -5434,3 +5434,5 @@
> };
> };
> };
> +
> +#include "sm8250-coresight.dtsi"
Why should everybody want coresight? It's not enabled on (most)
production devices and may cause a platform crash when you try to use it
on such ones.
These nodes should probably be added to sm8250.dtsi, all with status =
"disabled" by default, so that they don't break the devices that do not
support it due to fuse configuration.
Konrad
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-13 9:58 ` Konrad Dybcio
@ 2022-04-13 16:45 ` Jinlong Mao
2022-04-14 13:40 ` Mike Leach
0 siblings, 1 reply; 31+ messages in thread
From: Jinlong Mao @ 2022-04-13 16:45 UTC (permalink / raw)
To: Konrad Dybcio, Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm,
Bjorn Andersson
Hi Konrad,
Thank you for the review.
On 4/13/2022 5:58 PM, Konrad Dybcio wrote:
> Hi,
>
>
> I added Bjorn, the linux-arm-msm maintainer to CC as he was missing
> for some reason.
>
>
> On 12/04/2022 14:50, Mao Jinlong wrote:
>> Add coresight device tree for sm8250. STM/ETM are added.
>>
>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>> ---
>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>> 2 files changed, 528 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>> new file mode 100644
>> index 000000000000..1de42fd39248
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>> @@ -0,0 +1,526 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> sm8250.dtsi is BSD-3-Clause. Please consider relicensing.
>
>
>> +/*
>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>> reserved.
>> + */
>> +
>> +&soc {
>> +
>> + stm@6002000 {
>> + compatible = "arm,coresight-stm", "arm,primecell";
>> + reg = <0 0x06002000 0 0x1000>,
>
> You don't need to break the line at so few characters.
>
>
>> + <0 0x16280000 0 0x180000>;
>> + reg-names = "stm-base", "stm-stimulus-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + stm_out: endpoint {
>> + remote-endpoint =
>> + <&funnel0_in7>;
>
> Same here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@6041000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0 0x06041000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel0_out: endpoint {
>> + remote-endpoint =
>> + <&merge_funnel_in0>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@7 {
>> + reg = <7>;
>> + funnel0_in7: endpoint {
>> + remote-endpoint = <&stm_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@6042000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0 0x06042000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel2_out: endpoint {
>> + remote-endpoint =
>> + <&merge_funnel_in2>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@2 {
>> + reg = <4>;
>> + funnel2_in5: endpoint {
>> + remote-endpoint =
>> + <&apss_merge_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@6b04000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + arm,primecell-periphid = <0x000bb908>;
>> +
>> + reg = <0 0x6b04000 0 0x1000>;
>> + reg-names = "funnel-base";
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + merge_funnel_out: endpoint {
>> + remote-endpoint =
>> + <&etf_in>;
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@7 {
>> + reg = <7>;
>> + funnel_swao_in_funnel_merg: endpoint {
>> + remote-endpoint=
>
> And here.
>
>
>> + <&funnel_merg_out_funnel_swao>;
>> + };
>> + };
>> + };
>> +
>> + };
>> +
>> + funnel@6045000 {
>
> The nodes are not sorted properly (by address). Please fix that.
>
>
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0 0x06045000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + funnel_merg_out_funnel_swao: endpoint {
>> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + reg = <0>;
>> + merge_funnel_in0: endpoint {
>> + remote-endpoint =
>> + <&funnel0_out>;
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <1>;
>> + merge_funnel_in2: endpoint {
>> + remote-endpoint =
>> + <&funnel2_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@6046000 {
>> + compatible = "arm,coresight-dynamic-replicator",
>> "arm,primecell";
>> + reg = <0 0x06046000 0 0x1000>;
>> +
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + replicator_out: endpoint {
>> + remote-endpoint = <&etr_in>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port {
>> + replicator_cx_in_swao_out: endpoint {
>> + remote-endpoint = <&replicator_swao_out_cx_in>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + replicator@6b06000 {
>> + compatible = "arm,coresight-dynamic-replicator",
>> "arm,primecell";
>> + reg = <0 0x06b06000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + replicator_swao_out_cx_in: endpoint {
>> + remote-endpoint = <&replicator_cx_in_swao_out>;
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port {
>> + replicator_in: endpoint {
>> + remote-endpoint = <&etf_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etf@6b05000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x6b05000 0 0x1000>;
>
> Please pad the address to 8 chars.
>
>
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + etf_out: endpoint {
>> + remote-endpoint =
>> + <&replicator_in>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + reg = <0>;
>> + etf_in: endpoint {
>> + remote-endpoint =
>> + <&merge_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etr@6048000 {
>> + compatible = "arm,coresight-tmc", "arm,primecell";
>> + reg = <0 0x06048000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,scatter-gather;
>> +
>> + in-ports {
>> + port {
>> + etr_in: endpoint {
>> + remote-endpoint =
>> + <&replicator_out>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7040000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07040000 0 0x1000>;
>> +
>> + cpu = <&CPU0>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm0_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in0>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7140000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07140000 0 0x1000>;
>> +
>> + cpu = <&CPU1>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm1_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in1>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7240000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07240000 0 0x1000>;
>> +
>> + cpu = <&CPU2>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm2_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in2>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7340000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07340000 0 0x1000>;
>> +
>> + cpu = <&CPU3>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm3_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in3>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7440000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07440000 0 0x1000>;
>> +
>> + cpu = <&CPU4>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm4_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in4>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7540000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07540000 0 0x1000>;
>> +
>> + cpu = <&CPU5>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm5_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in5>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7640000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07640000 0 0x1000>;
>> +
>> + cpu = <&CPU6>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm6_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in6>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + etm@7740000 {
>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>> + reg = <0 0x07740000 0 0x1000>;
>> +
>> + cpu = <&CPU7>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> + arm,coresight-loses-context-with-cpu;
>> +
>> + out-ports {
>> + port {
>> + etm7_out: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_in7>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@7800000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0 0x07800000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + apss_funnel_out: endpoint {
>> + remote-endpoint =
>> + <&apss_merge_funnel_in>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + apss_funnel_in0: endpoint {
>> + remote-endpoint =
>> + <&etm0_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + apss_funnel_in1: endpoint {
>> + remote-endpoint =
>> + <&etm1_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@2 {
>> + reg = <2>;
>> + apss_funnel_in2: endpoint {
>> + remote-endpoint =
>> + <&etm2_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@3 {
>> + reg = <3>;
>> + apss_funnel_in3: endpoint {
>> + remote-endpoint =
>> + <&etm3_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@4 {
>> + reg = <4>;
>> + apss_funnel_in4: endpoint {
>> + remote-endpoint =
>> + <&etm4_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@5 {
>> + reg = <5>;
>> + apss_funnel_in5: endpoint {
>> + remote-endpoint =
>> + <&etm5_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@6 {
>> + reg = <6>;
>> + apss_funnel_in6: endpoint {
>> + remote-endpoint =
>> + <&etm6_out>;
>
> And here.
>
>
>> + };
>> + };
>> +
>> + port@7 {
>> + reg = <7>;
>> + apss_funnel_in7: endpoint {
>> + remote-endpoint =
>> + <&etm7_out>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> + };
>> +
>> + funnel@7810000 {
>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>> + reg = <0 0x07810000 0 0x1000>;
>> +
>> + clocks = <&aoss_qmp>;
>> + clock-names = "apb_pclk";
>> +
>> + out-ports {
>> + port {
>> + apss_merge_funnel_out: endpoint {
>> + remote-endpoint =
>> + <&funnel2_in5>;
>
> And here.
>
>
>> + };
>> + };
>> + };
>> +
>> + in-ports {
>> + port@1 {
>> + reg = <0>;
>> + apss_merge_funnel_in: endpoint {
>> + remote-endpoint =
>> + <&apss_funnel_out>;
>> + };
>> + };
>> + };
>> + };
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index af8f22636436..115623392183 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -5434,3 +5434,5 @@
>> };
>> };
>> };
>> +
>> +#include "sm8250-coresight.dtsi"
>
> Why should everybody want coresight? It's not enabled on (most)
> production devices and may cause a platform crash when you try to use
> it on such ones.
>
>
> These nodes should probably be added to sm8250.dtsi, all with status =
> "disabled" by default, so that they don't break the devices that do
> not support it due to fuse configuration.
>
I will address your comments above.
I create coresight dtsi because of that there are dozens of coresight
nodes for qualcomm HW.
Add all the nodes in a separate file is easy to maintain.
For disabling all the nodes by default, i will check internally and get
back to you.
Thanks
Jinlong Mao
>
> Konrad
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-13 16:45 ` Jinlong Mao
@ 2022-04-14 13:40 ` Mike Leach
2022-04-15 9:53 ` Jinlong Mao
0 siblings, 1 reply; 31+ messages in thread
From: Mike Leach @ 2022-04-14 13:40 UTC (permalink / raw)
To: Jinlong Mao
Cc: Konrad Dybcio, Mathieu Poirier, Suzuki K Poulose,
Alexander Shishkin, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm,
Bjorn Andersson
Hi
On Wed, 13 Apr 2022 at 17:45, Jinlong Mao <quic_jinlmao@quicinc.com> wrote:
>
> Hi Konrad,
>
> Thank you for the review.
>
> On 4/13/2022 5:58 PM, Konrad Dybcio wrote:
> > Hi,
> >
> >
> > I added Bjorn, the linux-arm-msm maintainer to CC as he was missing
> > for some reason.
> >
> >
> > On 12/04/2022 14:50, Mao Jinlong wrote:
> >> Add coresight device tree for sm8250. STM/ETM are added.
> >>
> >> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
> >> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> >> ---
> >> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
> >> 2 files changed, 528 insertions(+)
> >> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> >> b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> >> new file mode 100644
> >> index 000000000000..1de42fd39248
> >> --- /dev/null
> >> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> >> @@ -0,0 +1,526 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >
> > sm8250.dtsi is BSD-3-Clause. Please consider relicensing.
> >
> >
> >> +/*
> >> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
> >> reserved.
> >> + */
> >> +
> >> +&soc {
> >> +
> >> + stm@6002000 {
> >> + compatible = "arm,coresight-stm", "arm,primecell";
> >> + reg = <0 0x06002000 0 0x1000>,
> >
> > You don't need to break the line at so few characters.
> >
> >
> >> + <0 0x16280000 0 0x180000>;
> >> + reg-names = "stm-base", "stm-stimulus-base";
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + stm_out: endpoint {
> >> + remote-endpoint =
> >> + <&funnel0_in7>;
> >
> > Same here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + funnel@6041000 {
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + reg = <0 0x06041000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + funnel0_out: endpoint {
> >> + remote-endpoint =
> >> + <&merge_funnel_in0>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@7 {
> >> + reg = <7>;
> >> + funnel0_in7: endpoint {
> >> + remote-endpoint = <&stm_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + funnel@6042000 {
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + reg = <0 0x06042000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + funnel2_out: endpoint {
> >> + remote-endpoint =
> >> + <&merge_funnel_in2>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@2 {
> >> + reg = <4>;
> >> + funnel2_in5: endpoint {
> >> + remote-endpoint =
> >> + <&apss_merge_funnel_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + funnel@6b04000 {
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + arm,primecell-periphid = <0x000bb908>;
> >> +
> >> + reg = <0 0x6b04000 0 0x1000>;
> >> + reg-names = "funnel-base";
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + merge_funnel_out: endpoint {
> >> + remote-endpoint =
> >> + <&etf_in>;
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@7 {
> >> + reg = <7>;
> >> + funnel_swao_in_funnel_merg: endpoint {
> >> + remote-endpoint=
> >
> > And here.
> >
> >
> >> + <&funnel_merg_out_funnel_swao>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + };
> >> +
> >> + funnel@6045000 {
> >
> > The nodes are not sorted properly (by address). Please fix that.
> >
> >
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + reg = <0 0x06045000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + funnel_merg_out_funnel_swao: endpoint {
> >> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@1 {
> >> + reg = <0>;
> >> + merge_funnel_in0: endpoint {
> >> + remote-endpoint =
> >> + <&funnel0_out>;
> >> + };
> >> + };
> >> +
> >> + port@2 {
> >> + reg = <1>;
> >> + merge_funnel_in2: endpoint {
> >> + remote-endpoint =
> >> + <&funnel2_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + replicator@6046000 {
> >> + compatible = "arm,coresight-dynamic-replicator",
> >> "arm,primecell";
> >> + reg = <0 0x06046000 0 0x1000>;
> >> +
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + replicator_out: endpoint {
> >> + remote-endpoint = <&etr_in>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + port {
> >> + replicator_cx_in_swao_out: endpoint {
> >> + remote-endpoint = <&replicator_swao_out_cx_in>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + replicator@6b06000 {
> >> + compatible = "arm,coresight-dynamic-replicator",
> >> "arm,primecell";
> >> + reg = <0 0x06b06000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + replicator_swao_out_cx_in: endpoint {
> >> + remote-endpoint = <&replicator_cx_in_swao_out>;
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + port {
> >> + replicator_in: endpoint {
> >> + remote-endpoint = <&etf_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etf@6b05000 {
> >> + compatible = "arm,coresight-tmc", "arm,primecell";
> >> + reg = <0 0x6b05000 0 0x1000>;
> >
> > Please pad the address to 8 chars.
> >
> >
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + etf_out: endpoint {
> >> + remote-endpoint =
> >> + <&replicator_in>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@1 {
> >> + reg = <0>;
> >> + etf_in: endpoint {
> >> + remote-endpoint =
> >> + <&merge_funnel_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etr@6048000 {
> >> + compatible = "arm,coresight-tmc", "arm,primecell";
> >> + reg = <0 0x06048000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,scatter-gather;
> >> +
> >> + in-ports {
> >> + port {
> >> + etr_in: endpoint {
> >> + remote-endpoint =
> >> + <&replicator_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7040000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07040000 0 0x1000>;
> >> +
> >> + cpu = <&CPU0>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm0_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in0>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7140000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07140000 0 0x1000>;
> >> +
> >> + cpu = <&CPU1>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm1_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in1>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7240000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07240000 0 0x1000>;
> >> +
> >> + cpu = <&CPU2>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm2_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in2>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7340000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07340000 0 0x1000>;
> >> +
> >> + cpu = <&CPU3>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm3_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in3>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7440000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07440000 0 0x1000>;
> >> +
> >> + cpu = <&CPU4>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm4_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in4>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7540000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07540000 0 0x1000>;
> >> +
> >> + cpu = <&CPU5>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm5_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in5>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7640000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07640000 0 0x1000>;
> >> +
> >> + cpu = <&CPU6>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm6_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in6>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + etm@7740000 {
> >> + compatible = "arm,coresight-etm4x", "arm,primecell";
> >> + reg = <0 0x07740000 0 0x1000>;
> >> +
> >> + cpu = <&CPU7>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> + arm,coresight-loses-context-with-cpu;
> >> +
> >> + out-ports {
> >> + port {
> >> + etm7_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_in7>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + funnel@7800000 {
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + reg = <0 0x07800000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + apss_funnel_out: endpoint {
> >> + remote-endpoint =
> >> + <&apss_merge_funnel_in>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@0 {
> >> + reg = <0>;
> >> + apss_funnel_in0: endpoint {
> >> + remote-endpoint =
> >> + <&etm0_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@1 {
> >> + reg = <1>;
> >> + apss_funnel_in1: endpoint {
> >> + remote-endpoint =
> >> + <&etm1_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@2 {
> >> + reg = <2>;
> >> + apss_funnel_in2: endpoint {
> >> + remote-endpoint =
> >> + <&etm2_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@3 {
> >> + reg = <3>;
> >> + apss_funnel_in3: endpoint {
> >> + remote-endpoint =
> >> + <&etm3_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@4 {
> >> + reg = <4>;
> >> + apss_funnel_in4: endpoint {
> >> + remote-endpoint =
> >> + <&etm4_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@5 {
> >> + reg = <5>;
> >> + apss_funnel_in5: endpoint {
> >> + remote-endpoint =
> >> + <&etm5_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@6 {
> >> + reg = <6>;
> >> + apss_funnel_in6: endpoint {
> >> + remote-endpoint =
> >> + <&etm6_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> +
> >> + port@7 {
> >> + reg = <7>;
> >> + apss_funnel_in7: endpoint {
> >> + remote-endpoint =
> >> + <&etm7_out>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + funnel@7810000 {
> >> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> >> + reg = <0 0x07810000 0 0x1000>;
> >> +
> >> + clocks = <&aoss_qmp>;
> >> + clock-names = "apb_pclk";
> >> +
> >> + out-ports {
> >> + port {
> >> + apss_merge_funnel_out: endpoint {
> >> + remote-endpoint =
> >> + <&funnel2_in5>;
> >
> > And here.
> >
> >
> >> + };
> >> + };
> >> + };
> >> +
> >> + in-ports {
> >> + port@1 {
> >> + reg = <0>;
> >> + apss_merge_funnel_in: endpoint {
> >> + remote-endpoint =
> >> + <&apss_funnel_out>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> >> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> >> index af8f22636436..115623392183 100644
> >> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> >> @@ -5434,3 +5434,5 @@
> >> };
> >> };
> >> };
> >> +
> >> +#include "sm8250-coresight.dtsi"
> >
> > Why should everybody want coresight? It's not enabled on (most)
> > production devices and may cause a platform crash when you try to use
> > it on such ones.
> >
> >
> > These nodes should probably be added to sm8250.dtsi, all with status =
> > "disabled" by default, so that they don't break the devices that do
> > not support it due to fuse configuration.
> >
> I will address your comments above.
> I create coresight dtsi because of that there are dozens of coresight
> nodes for qualcomm HW.
> Add all the nodes in a separate file is easy to maintain.
> For disabling all the nodes by default, i will check internally and get
> back to you.
>
If the nodes are "disabled", then the base .dts files for platforms
that do include coresight would have to be updated to enable all those
nodes - which leaves potential for errors if nodes are accidentally
omitted.
Because sm8250-coresight.dtsi contains only Coresight devices, would
it not be better to include this directly in the base .dts file for
platforms that do have Coresight, and omit it from those that do not.
Regards
Mike
>
> Thanks
> Jinlong Mao
>
>
> >
> > Konrad
> >
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-14 13:40 ` Mike Leach
@ 2022-04-15 9:53 ` Jinlong Mao
2022-04-20 17:07 ` Konrad Dybcio
0 siblings, 1 reply; 31+ messages in thread
From: Jinlong Mao @ 2022-04-15 9:53 UTC (permalink / raw)
To: Mike Leach
Cc: Konrad Dybcio, Alexander Shishkin, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm,
Bjorn Andersson
Hi Mike & Konrad,
On 4/14/2022 9:40 PM, Mike Leach wrote:
> Hi
>
> On Wed, 13 Apr 2022 at 17:45, Jinlong Mao <quic_jinlmao@quicinc.com> wrote:
>> Hi Konrad,
>>
>> Thank you for the review.
>>
>> On 4/13/2022 5:58 PM, Konrad Dybcio wrote:
>>> Hi,
>>>
>>>
>>> I added Bjorn, the linux-arm-msm maintainer to CC as he was missing
>>> for some reason.
>>>
>>>
>>> On 12/04/2022 14:50, Mao Jinlong wrote:
>>>> Add coresight device tree for sm8250. STM/ETM are added.
>>>>
>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>>>> ---
>>>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526 ++++++++++++++++++
>>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>>>> 2 files changed, 528 insertions(+)
>>>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>> b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>> new file mode 100644
>>>> index 000000000000..1de42fd39248
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>> @@ -0,0 +1,526 @@
>>>> +// SPDX-License-Identifier: GPL-2.0
>>> sm8250.dtsi is BSD-3-Clause. Please consider relicensing.
>>>
>>>
>>>> +/*
>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>>>> reserved.
>>>> + */
>>>> +
>>>> +&soc {
>>>> +
>>>> + stm@6002000 {
>>>> + compatible = "arm,coresight-stm", "arm,primecell";
>>>> + reg = <0 0x06002000 0 0x1000>,
>>> You don't need to break the line at so few characters.
>>>
>>>
>>>> + <0 0x16280000 0 0x180000>;
>>>> + reg-names = "stm-base", "stm-stimulus-base";
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + stm_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&funnel0_in7>;
>>> Same here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel@6041000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0x06041000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + funnel0_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&merge_funnel_in0>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@7 {
>>>> + reg = <7>;
>>>> + funnel0_in7: endpoint {
>>>> + remote-endpoint = <&stm_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel@6042000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0x06042000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + funnel2_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&merge_funnel_in2>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@2 {
>>>> + reg = <4>;
>>>> + funnel2_in5: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_merge_funnel_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel@6b04000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + arm,primecell-periphid = <0x000bb908>;
>>>> +
>>>> + reg = <0 0x6b04000 0 0x1000>;
>>>> + reg-names = "funnel-base";
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + merge_funnel_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&etf_in>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@7 {
>>>> + reg = <7>;
>>>> + funnel_swao_in_funnel_merg: endpoint {
>>>> + remote-endpoint=
>>> And here.
>>>
>>>
>>>> + <&funnel_merg_out_funnel_swao>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + };
>>>> +
>>>> + funnel@6045000 {
>>> The nodes are not sorted properly (by address). Please fix that.
>>>
>>>
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0x06045000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + funnel_merg_out_funnel_swao: endpoint {
>>>> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@1 {
>>>> + reg = <0>;
>>>> + merge_funnel_in0: endpoint {
>>>> + remote-endpoint =
>>>> + <&funnel0_out>;
>>>> + };
>>>> + };
>>>> +
>>>> + port@2 {
>>>> + reg = <1>;
>>>> + merge_funnel_in2: endpoint {
>>>> + remote-endpoint =
>>>> + <&funnel2_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + replicator@6046000 {
>>>> + compatible = "arm,coresight-dynamic-replicator",
>>>> "arm,primecell";
>>>> + reg = <0 0x06046000 0 0x1000>;
>>>> +
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + replicator_out: endpoint {
>>>> + remote-endpoint = <&etr_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + port {
>>>> + replicator_cx_in_swao_out: endpoint {
>>>> + remote-endpoint = <&replicator_swao_out_cx_in>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + replicator@6b06000 {
>>>> + compatible = "arm,coresight-dynamic-replicator",
>>>> "arm,primecell";
>>>> + reg = <0 0x06b06000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + replicator_swao_out_cx_in: endpoint {
>>>> + remote-endpoint = <&replicator_cx_in_swao_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + port {
>>>> + replicator_in: endpoint {
>>>> + remote-endpoint = <&etf_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etf@6b05000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0x6b05000 0 0x1000>;
>>> Please pad the address to 8 chars.
>>>
>>>
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etf_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_in>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@1 {
>>>> + reg = <0>;
>>>> + etf_in: endpoint {
>>>> + remote-endpoint =
>>>> + <&merge_funnel_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etr@6048000 {
>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>> + reg = <0 0x06048000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,scatter-gather;
>>>> +
>>>> + in-ports {
>>>> + port {
>>>> + etr_in: endpoint {
>>>> + remote-endpoint =
>>>> + <&replicator_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7040000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07040000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU0>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm0_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in0>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7140000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07140000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU1>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm1_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in1>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7240000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07240000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU2>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm2_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in2>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7340000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07340000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU3>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm3_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in3>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7440000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07440000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU4>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm4_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in4>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7540000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07540000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU5>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm5_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in5>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7640000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07640000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU6>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm6_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in6>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + etm@7740000 {
>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>> + reg = <0 0x07740000 0 0x1000>;
>>>> +
>>>> + cpu = <&CPU7>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> + arm,coresight-loses-context-with-cpu;
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + etm7_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_in7>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel@7800000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0x07800000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + apss_funnel_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_merge_funnel_in>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + #address-cells = <1>;
>>>> + #size-cells = <0>;
>>>> +
>>>> + port@0 {
>>>> + reg = <0>;
>>>> + apss_funnel_in0: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm0_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@1 {
>>>> + reg = <1>;
>>>> + apss_funnel_in1: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm1_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@2 {
>>>> + reg = <2>;
>>>> + apss_funnel_in2: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm2_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@3 {
>>>> + reg = <3>;
>>>> + apss_funnel_in3: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm3_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@4 {
>>>> + reg = <4>;
>>>> + apss_funnel_in4: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm4_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@5 {
>>>> + reg = <5>;
>>>> + apss_funnel_in5: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm5_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@6 {
>>>> + reg = <6>;
>>>> + apss_funnel_in6: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm6_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> +
>>>> + port@7 {
>>>> + reg = <7>;
>>>> + apss_funnel_in7: endpoint {
>>>> + remote-endpoint =
>>>> + <&etm7_out>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + funnel@7810000 {
>>>> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
>>>> + reg = <0 0x07810000 0 0x1000>;
>>>> +
>>>> + clocks = <&aoss_qmp>;
>>>> + clock-names = "apb_pclk";
>>>> +
>>>> + out-ports {
>>>> + port {
>>>> + apss_merge_funnel_out: endpoint {
>>>> + remote-endpoint =
>>>> + <&funnel2_in5>;
>>> And here.
>>>
>>>
>>>> + };
>>>> + };
>>>> + };
>>>> +
>>>> + in-ports {
>>>> + port@1 {
>>>> + reg = <0>;
>>>> + apss_merge_funnel_in: endpoint {
>>>> + remote-endpoint =
>>>> + <&apss_funnel_out>;
>>>> + };
>>>> + };
>>>> + };
>>>> + };
>>>> +};
>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> index af8f22636436..115623392183 100644
>>>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>> @@ -5434,3 +5434,5 @@
>>>> };
>>>> };
>>>> };
>>>> +
>>>> +#include "sm8250-coresight.dtsi"
>>> Why should everybody want coresight? It's not enabled on (most)
>>> production devices and may cause a platform crash when you try to use
>>> it on such ones.
>>>
>>>
>>> These nodes should probably be added to sm8250.dtsi, all with status =
>>> "disabled" by default, so that they don't break the devices that do
>>> not support it due to fuse configuration.
>>>
>> I will address your comments above.
>> I create coresight dtsi because of that there are dozens of coresight
>> nodes for qualcomm HW.
>> Add all the nodes in a separate file is easy to maintain.
>> For disabling all the nodes by default, i will check internally and get
>> back to you.
>>
> If the nodes are "disabled", then the base .dts files for platforms
> that do include coresight would have to be updated to enable all those
> nodes - which leaves potential for errors if nodes are accidentally
> omitted.
>
> Because sm8250-coresight.dtsi contains only Coresight devices, would
> it not be better to include this directly in the base .dts file for
> platforms that do have Coresight, and omit it from those that do not.
>
> Regards
>
> Mike
>
I checked internally. These coresight nodes are tested on our secure device.
They won't cause any crash issue on secure device with fuse blown.
If any platform doesn't need to coresight support, it can control by the
coresight kernel configs.
Regards
Jinlong Mao
>> Thanks
>> Jinlong Mao
>>
>>
>>> Konrad
>>>
>
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250
2022-04-15 9:53 ` Jinlong Mao
@ 2022-04-20 17:07 ` Konrad Dybcio
0 siblings, 0 replies; 31+ messages in thread
From: Konrad Dybcio @ 2022-04-20 17:07 UTC (permalink / raw)
To: Jinlong Mao, Mike Leach
Cc: Alexander Shishkin, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm,
Bjorn Andersson
On 15/04/2022 11:53, Jinlong Mao wrote:
> Hi Mike & Konrad,
>
>
> On 4/14/2022 9:40 PM, Mike Leach wrote:
>> Hi
>>
>> On Wed, 13 Apr 2022 at 17:45, Jinlong Mao <quic_jinlmao@quicinc.com>
>> wrote:
>>> Hi Konrad,
>>>
>>> Thank you for the review.
>>>
>>> On 4/13/2022 5:58 PM, Konrad Dybcio wrote:
>>>> Hi,
>>>>
>>>>
>>>> I added Bjorn, the linux-arm-msm maintainer to CC as he was missing
>>>> for some reason.
>>>>
>>>>
>>>> On 12/04/2022 14:50, Mao Jinlong wrote:
>>>>> Add coresight device tree for sm8250. STM/ETM are added.
>>>>>
>>>>> Signed-off-by: Tao Zhang <quic_taozha@quicinc.com>
>>>>> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
>>>>> ---
>>>>> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 526
>>>>> ++++++++++++++++++
>>>>> arch/arm64/boot/dts/qcom/sm8250.dtsi | 2 +
>>>>> 2 files changed, 528 insertions(+)
>>>>> create mode 100644 arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>>> b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>>> new file mode 100644
>>>>> index 000000000000..1de42fd39248
>>>>> --- /dev/null
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
>>>>> @@ -0,0 +1,526 @@
>>>>> +// SPDX-License-Identifier: GPL-2.0
>>>> sm8250.dtsi is BSD-3-Clause. Please consider relicensing.
>>>>
>>>>
>>>>> +/*
>>>>> + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights
>>>>> reserved.
>>>>> + */
>>>>> +
>>>>> +&soc {
>>>>> +
>>>>> + stm@6002000 {
>>>>> + compatible = "arm,coresight-stm", "arm,primecell";
>>>>> + reg = <0 0x06002000 0 0x1000>,
>>>> You don't need to break the line at so few characters.
>>>>
>>>>
>>>>> + <0 0x16280000 0 0x180000>;
>>>>> + reg-names = "stm-base", "stm-stimulus-base";
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + stm_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&funnel0_in7>;
>>>> Same here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + funnel@6041000 {
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x06041000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + funnel0_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&merge_funnel_in0>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@7 {
>>>>> + reg = <7>;
>>>>> + funnel0_in7: endpoint {
>>>>> + remote-endpoint = <&stm_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + funnel@6042000 {
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x06042000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + funnel2_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&merge_funnel_in2>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@2 {
>>>>> + reg = <4>;
>>>>> + funnel2_in5: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_merge_funnel_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + funnel@6b04000 {
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + arm,primecell-periphid = <0x000bb908>;
>>>>> +
>>>>> + reg = <0 0x6b04000 0 0x1000>;
>>>>> + reg-names = "funnel-base";
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + merge_funnel_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etf_in>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@7 {
>>>>> + reg = <7>;
>>>>> + funnel_swao_in_funnel_merg: endpoint {
>>>>> + remote-endpoint=
>>>> And here.
>>>>
>>>>
>>>>> + <&funnel_merg_out_funnel_swao>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + };
>>>>> +
>>>>> + funnel@6045000 {
>>>> The nodes are not sorted properly (by address). Please fix that.
>>>>
>>>>
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x06045000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + funnel_merg_out_funnel_swao: endpoint {
>>>>> + remote-endpoint = <&funnel_swao_in_funnel_merg>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@1 {
>>>>> + reg = <0>;
>>>>> + merge_funnel_in0: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&funnel0_out>;
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@2 {
>>>>> + reg = <1>;
>>>>> + merge_funnel_in2: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&funnel2_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + replicator@6046000 {
>>>>> + compatible = "arm,coresight-dynamic-replicator",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x06046000 0 0x1000>;
>>>>> +
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + replicator_out: endpoint {
>>>>> + remote-endpoint = <&etr_in>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + port {
>>>>> + replicator_cx_in_swao_out: endpoint {
>>>>> + remote-endpoint = <&replicator_swao_out_cx_in>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + replicator@6b06000 {
>>>>> + compatible = "arm,coresight-dynamic-replicator",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x06b06000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + replicator_swao_out_cx_in: endpoint {
>>>>> + remote-endpoint = <&replicator_cx_in_swao_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + port {
>>>>> + replicator_in: endpoint {
>>>>> + remote-endpoint = <&etf_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etf@6b05000 {
>>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>>> + reg = <0 0x6b05000 0 0x1000>;
>>>> Please pad the address to 8 chars.
>>>>
>>>>
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etf_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&replicator_in>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@1 {
>>>>> + reg = <0>;
>>>>> + etf_in: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&merge_funnel_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etr@6048000 {
>>>>> + compatible = "arm,coresight-tmc", "arm,primecell";
>>>>> + reg = <0 0x06048000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,scatter-gather;
>>>>> +
>>>>> + in-ports {
>>>>> + port {
>>>>> + etr_in: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&replicator_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7040000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07040000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU0>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm0_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in0>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7140000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07140000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU1>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm1_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in1>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7240000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07240000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU2>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm2_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in2>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7340000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07340000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU3>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm3_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in3>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7440000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07440000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU4>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm4_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in4>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7540000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07540000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU5>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm5_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in5>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7640000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07640000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU6>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm6_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in6>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + etm@7740000 {
>>>>> + compatible = "arm,coresight-etm4x", "arm,primecell";
>>>>> + reg = <0 0x07740000 0 0x1000>;
>>>>> +
>>>>> + cpu = <&CPU7>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> + arm,coresight-loses-context-with-cpu;
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + etm7_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_in7>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + funnel@7800000 {
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x07800000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + apss_funnel_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_merge_funnel_in>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + #address-cells = <1>;
>>>>> + #size-cells = <0>;
>>>>> +
>>>>> + port@0 {
>>>>> + reg = <0>;
>>>>> + apss_funnel_in0: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm0_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@1 {
>>>>> + reg = <1>;
>>>>> + apss_funnel_in1: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm1_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@2 {
>>>>> + reg = <2>;
>>>>> + apss_funnel_in2: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm2_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@3 {
>>>>> + reg = <3>;
>>>>> + apss_funnel_in3: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm3_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@4 {
>>>>> + reg = <4>;
>>>>> + apss_funnel_in4: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm4_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@5 {
>>>>> + reg = <5>;
>>>>> + apss_funnel_in5: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm5_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@6 {
>>>>> + reg = <6>;
>>>>> + apss_funnel_in6: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm6_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + port@7 {
>>>>> + reg = <7>;
>>>>> + apss_funnel_in7: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&etm7_out>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + funnel@7810000 {
>>>>> + compatible = "arm,coresight-dynamic-funnel",
>>>>> "arm,primecell";
>>>>> + reg = <0 0x07810000 0 0x1000>;
>>>>> +
>>>>> + clocks = <&aoss_qmp>;
>>>>> + clock-names = "apb_pclk";
>>>>> +
>>>>> + out-ports {
>>>>> + port {
>>>>> + apss_merge_funnel_out: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&funnel2_in5>;
>>>> And here.
>>>>
>>>>
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +
>>>>> + in-ports {
>>>>> + port@1 {
>>>>> + reg = <0>;
>>>>> + apss_merge_funnel_in: endpoint {
>>>>> + remote-endpoint =
>>>>> + <&apss_funnel_out>;
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> + };
>>>>> +};
>>>>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>>> index af8f22636436..115623392183 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>>>>> @@ -5434,3 +5434,5 @@
>>>>> };
>>>>> };
>>>>> };
>>>>> +
>>>>> +#include "sm8250-coresight.dtsi"
>>>> Why should everybody want coresight? It's not enabled on (most)
>>>> production devices and may cause a platform crash when you try to use
>>>> it on such ones.
>>>>
>>>>
>>>> These nodes should probably be added to sm8250.dtsi, all with status =
>>>> "disabled" by default, so that they don't break the devices that do
>>>> not support it due to fuse configuration.
>>>>
>>> I will address your comments above.
>>> I create coresight dtsi because of that there are dozens of coresight
>>> nodes for qualcomm HW.
>>> Add all the nodes in a separate file is easy to maintain.
>>> For disabling all the nodes by default, i will check internally and get
>>> back to you.
>>>
>> If the nodes are "disabled", then the base .dts files for platforms
>> that do include coresight would have to be updated to enable all those
>> nodes - which leaves potential for errors if nodes are accidentally
>> omitted.
>>
>> Because sm8250-coresight.dtsi contains only Coresight devices, would
>> it not be better to include this directly in the base .dts file for
>> platforms that do have Coresight, and omit it from those that do not.
>>
>> Regards
>>
>> Mike
>>
> I checked internally. These coresight nodes are tested on our secure
> device.
I had an opportunity to confirm this, sorry for spreading unnecessary
FUD, but this used to be an issue on some older boards.
> They won't cause any crash issue on secure device with fuse blown.
> If any platform doesn't need to coresight support, it can control by
> the coresight kernel configs.
No, the arm64 kernel is supposed to run on hundreds if not thousands of
boards with a common config (just like on x86/_64 machines). Our job is
to make it fully functional with the arm64 defconfig, and that's what
the status property is effectively for in device trees. You don't get to
decide what is enabled or not in the config based on individual device
capabilities.
Since we've established that Coresight doesn't break secure devices, I
take back that status = "disabled" comment, it's not necessary. Please
move all the nodes to the SoC dtsi though, as they are specific only to
sm8250 and won't be included anywhere else.
Konrad
>
>
> Regards
> Jinlong Mao
>
>
>>> Thanks
>>> Jinlong Mao
>>>
>>>
>>>> Konrad
>>>>
>>
>>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250
2022-04-12 12:50 [PATCH v5 00/10] Coresight: Add support for TPDM and TPDA Mao Jinlong
` (8 preceding siblings ...)
2022-04-12 12:50 ` [PATCH v5 09/10] ARM: dts: msm: Add coresight components for SM8250 Mao Jinlong
@ 2022-04-12 12:50 ` Mao Jinlong
2022-04-13 10:01 ` Konrad Dybcio
9 siblings, 1 reply; 31+ messages in thread
From: Mao Jinlong @ 2022-04-12 12:50 UTC (permalink / raw)
To: Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mao Jinlong, Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
Add tpdm mm and tpdm prng for sm8250.
+---------------+ +-------------+
| tpdm@6c08000 | |tpdm@684C000 |
+-------|-------+ +------|------+
| |
+-------|-------+ |
| funnel@6c0b000| |
+-------|-------+ |
| |
+-------|-------+ |
|funnel@6c2d000 | |
+-------|-------+ |
| |
| +---------------+ |
+----- tpda@6004000 -----------+
+-------|-------+
|
+-------|-------+
|funnel@6005000 |
+---------------+
Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
---
.../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 182 ++++++++++++++++++
1 file changed, 182 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
index 1de42fd39248..9c710b69a804 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
@@ -44,6 +44,14 @@
#address-cells = <1>;
#size-cells = <0>;
+ port@6 {
+ reg = <6>;
+ funnel_in0_in_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_out_funnel_in0>;
+ };
+ };
+
port@7 {
reg = <7>;
funnel0_in7: endpoint {
@@ -523,4 +531,178 @@
};
};
};
+
+ tpdm@6c08000 {
+ compatible = "arm,primecell";
+ reg = <0 0x6c08000 0 0x1000>;
+ reg-names = "tpdm-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_mm_out_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_in_tpdm_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c0b000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0 0x6c0b000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_dl_mm_out_funnel_dl_center: endpoint {
+ remote-endpoint =
+ <&funnel_dl_center_in_funnel_dl_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@3 {
+ reg = <3>;
+ funnel_dl_mm_in_tpdm_mm: endpoint {
+ remote-endpoint =
+ <&tpdm_mm_out_funnel_dl_mm>;
+ };
+ };
+ };
+ };
+
+ funnel@6c2d000 {
+ compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
+
+ reg = <0 0x6c2d000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port {
+ tpdm_mm_out_tpda9: endpoint {
+ remote-endpoint =
+ <&tpda_9_in_tpdm_mm>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@2 {
+ reg = <2>;
+ funnel_dl_center_in_funnel_dl_mm: endpoint {
+ remote-endpoint =
+ <&funnel_dl_mm_out_funnel_dl_center>;
+ };
+ };
+ };
+ };
+
+ tpdm@684C000 {
+ compatible = "arm,primecell";
+ reg = <0 0x684C000 0 0x1000>;
+ reg-names = "tpdm-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ tpdm_prng_out_tpda_23: endpoint {
+ remote-endpoint =
+ <&tpda_23_in_tpdm_prng>;
+ };
+ };
+ };
+ };
+
+ tpda@6004000 {
+ compatible = "arm,primecell";
+ reg = <0 0x6004000 0 0x1000>;
+ reg-names = "tpda-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ reg = <0>;
+ tpda_out_funnel_qatb: endpoint {
+ remote-endpoint =
+ <&funnel_qatb_in_tpda>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@9 {
+ reg = <9>;
+ tpda_9_in_tpdm_mm: endpoint {
+ remote-endpoint =
+ <&tpdm_mm_out_tpda9>;
+ };
+ };
+
+ port@23 {
+ reg = <23>;
+ tpda_23_in_tpdm_prng: endpoint {
+ remote-endpoint =
+ <&tpdm_prng_out_tpda_23>;
+ };
+ };
+ };
+ };
+
+ funnel@6005000 {
+ compatible = "arm,primecell";
+
+ reg = <0 0x6005000 0 0x1000>;
+ reg-names = "funnel-base";
+
+ clocks = <&aoss_qmp>;
+ clock-names = "apb_pclk";
+
+ out-ports {
+ port {
+ funnel_qatb_out_funnel_in0: endpoint {
+ remote-endpoint =
+ <&funnel_in0_in_funnel_qatb>;
+ };
+ };
+ };
+
+ in-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ funnel_qatb_in_tpda: endpoint {
+ remote-endpoint =
+ <&tpda_out_funnel_qatb>;
+ };
+ };
+ };
+ };
};
--
2.17.1
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250
2022-04-12 12:50 ` [PATCH v5 10/10] ARM: dts: msm: Add tpdm mm/prng for sm8250 Mao Jinlong
@ 2022-04-13 10:01 ` Konrad Dybcio
0 siblings, 0 replies; 31+ messages in thread
From: Konrad Dybcio @ 2022-04-13 10:01 UTC (permalink / raw)
To: Mao Jinlong, Mathieu Poirier, Suzuki K Poulose, Alexander Shishkin
Cc: Mike Leach, Leo Yan, Greg Kroah-Hartman, coresight,
linux-arm-kernel, linux-kernel, Tingwei Zhang, Yuanfang Zhang,
Tao Zhang, Trilok Soni, Hao Zhang, linux-arm-msm
On 12/04/2022 14:50, Mao Jinlong wrote:
> Add tpdm mm and tpdm prng for sm8250.
>
> +---------------+ +-------------+
> | tpdm@6c08000 | |tpdm@684C000 |
> +-------|-------+ +------|------+
> | |
> +-------|-------+ |
> | funnel@6c0b000| |
> +-------|-------+ |
> | |
> +-------|-------+ |
> |funnel@6c2d000 | |
> +-------|-------+ |
> | |
> | +---------------+ |
> +----- tpda@6004000 -----------+
> +-------|-------+
> |
> +-------|-------+
> |funnel@6005000 |
> +---------------+
>
> Signed-off-by: Mao Jinlong <quic_jinlmao@quicinc.com>
> ---
> .../arm64/boot/dts/qcom/sm8250-coresight.dtsi | 182 ++++++++++++++++++
> 1 file changed, 182 insertions(+)
Same comments as in 9/10: title, sorting, status=disabled, line breaks..
Also, please make sure to use lowercase hex throughout the file (i.e.
0x684c000 not 0x684C000).
Konrad
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> index 1de42fd39248..9c710b69a804 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250-coresight.dtsi
> @@ -44,6 +44,14 @@
> #address-cells = <1>;
> #size-cells = <0>;
>
> + port@6 {
> + reg = <6>;
> + funnel_in0_in_funnel_qatb: endpoint {
> + remote-endpoint =
> + <&funnel_qatb_out_funnel_in0>;
> + };
> + };
> +
> port@7 {
> reg = <7>;
> funnel0_in7: endpoint {
> @@ -523,4 +531,178 @@
> };
> };
> };
> +
> + tpdm@6c08000 {
> + compatible = "arm,primecell";
> + reg = <0 0x6c08000 0 0x1000>;
> + reg-names = "tpdm-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + tpdm_mm_out_funnel_dl_mm: endpoint {
> + remote-endpoint =
> + <&funnel_dl_mm_in_tpdm_mm>;
> + };
> + };
> + };
> + };
> +
> + funnel@6c0b000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +
> + reg = <0 0x6c0b000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_dl_mm_out_funnel_dl_center: endpoint {
> + remote-endpoint =
> + <&funnel_dl_center_in_funnel_dl_mm>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@3 {
> + reg = <3>;
> + funnel_dl_mm_in_tpdm_mm: endpoint {
> + remote-endpoint =
> + <&tpdm_mm_out_funnel_dl_mm>;
> + };
> + };
> + };
> + };
> +
> + funnel@6c2d000 {
> + compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
> +
> + reg = <0 0x6c2d000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port {
> + tpdm_mm_out_tpda9: endpoint {
> + remote-endpoint =
> + <&tpda_9_in_tpdm_mm>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@2 {
> + reg = <2>;
> + funnel_dl_center_in_funnel_dl_mm: endpoint {
> + remote-endpoint =
> + <&funnel_dl_mm_out_funnel_dl_center>;
> + };
> + };
> + };
> + };
> +
> + tpdm@684C000 {
> + compatible = "arm,primecell";
> + reg = <0 0x684C000 0 0x1000>;
> + reg-names = "tpdm-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + tpdm_prng_out_tpda_23: endpoint {
> + remote-endpoint =
> + <&tpda_23_in_tpdm_prng>;
> + };
> + };
> + };
> + };
> +
> + tpda@6004000 {
> + compatible = "arm,primecell";
> + reg = <0 0x6004000 0 0x1000>;
> + reg-names = "tpda-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + reg = <0>;
> + tpda_out_funnel_qatb: endpoint {
> + remote-endpoint =
> + <&funnel_qatb_in_tpda>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@9 {
> + reg = <9>;
> + tpda_9_in_tpdm_mm: endpoint {
> + remote-endpoint =
> + <&tpdm_mm_out_tpda9>;
> + };
> + };
> +
> + port@23 {
> + reg = <23>;
> + tpda_23_in_tpdm_prng: endpoint {
> + remote-endpoint =
> + <&tpdm_prng_out_tpda_23>;
> + };
> + };
> + };
> + };
> +
> + funnel@6005000 {
> + compatible = "arm,primecell";
> +
> + reg = <0 0x6005000 0 0x1000>;
> + reg-names = "funnel-base";
> +
> + clocks = <&aoss_qmp>;
> + clock-names = "apb_pclk";
> +
> + out-ports {
> + port {
> + funnel_qatb_out_funnel_in0: endpoint {
> + remote-endpoint =
> + <&funnel_in0_in_funnel_qatb>;
> + };
> + };
> + };
> +
> + in-ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + funnel_qatb_in_tpda: endpoint {
> + remote-endpoint =
> + <&tpda_out_funnel_qatb>;
> + };
> + };
> + };
> + };
> };
>
^ permalink raw reply [flat|nested] 31+ messages in thread