* [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines
@ 2022-04-12 21:51 Bjorn Andersson
2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Bjorn Andersson @ 2022-04-12 21:51 UTC (permalink / raw)
To: Bjorn Andersson, Vinod Koul
Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree,
linux-kernel
The Qualcomm SM8350 has three GPI DMA engines, add definitions for
these.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 73 ++++++++++++++++++++++++++++
1 file changed, 73 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index a68231634da2..7e585d9e4c68 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -3,6 +3,7 @@
* Copyright (c) 2020, Linaro Limited
*/
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,dispcc-sm8350.h>
@@ -678,6 +679,28 @@ opp-120000000 {
};
};
+ gpi_dma2: dma-controller@800000 {
+ compatible = "qcom,sm8350-gpi-dma";
+ reg = <0 0x00800000 0 0x60000>;
+ interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0xff>;
+ iommus = <&apps_smmu 0x5f6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_2: geniqup@8c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x008c0000 0x0 0x6000>;
@@ -843,12 +866,37 @@ spi19: spi@894000 {
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
+ dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma2 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
+ gpi_dma0: dma-controller@900000 {
+ compatible = "qcom,sm8350-gpi-dma";
+ reg = <0 0x09800000 0 0x60000>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0x7e>;
+ iommus = <&apps_smmu 0x5b6 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x009c0000 0x0 0x6000>;
@@ -1081,12 +1129,37 @@ spi7: spi@99c000 {
interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8350_CX>;
operating-points-v2 = <&qup_opp_table_100mhz>;
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 7 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
};
+ gpi_dma1: dma-controller@a00000 {
+ compatible = "qcom,sm8350-gpi-dma";
+ reg = <0 0x00a00000 0 0x60000>;
+ interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ dma-channels = <12>;
+ dma-channel-mask = <0xff>;
+ iommus = <&apps_smmu 0x56 0x0>;
+ #dma-cells = <3>;
+ status = "disabled";
+ };
+
qupv3_id_1: geniqup@ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x00ac0000 0x0 0x6000>;
--
2.35.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels 2022-04-12 21:51 [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Bjorn Andersson @ 2022-04-12 21:51 ` Bjorn Andersson 2022-04-13 3:14 ` Vinod Koul 2022-04-18 8:01 ` Vinod Koul 2022-04-12 21:51 ` [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Bjorn Andersson ` (2 subsequent siblings) 3 siblings, 2 replies; 10+ messages in thread From: Bjorn Andersson @ 2022-04-12 21:51 UTC (permalink / raw) To: Bjorn Andersson, Vinod Koul Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel The GENI I2C and SPI controllers may use the GPI DMA engine, define the rx and tx channels for these controllers to enable this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ 1 file changed, 108 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 7e585d9e4c68..8547c0b2f060 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -721,6 +721,9 @@ i2c14: i2c@880000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c14_default>; interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -734,6 +737,9 @@ spi14: spi@880000 { interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -747,6 +753,9 @@ i2c15: i2c@884000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c15_default>; interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -760,6 +769,9 @@ spi15: spi@884000 { interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -773,6 +785,9 @@ i2c16: i2c@888000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c16_default>; interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -786,6 +801,9 @@ spi16: spi@888000 { interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -799,6 +817,9 @@ i2c17: i2c@88c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c17_default>; interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -812,6 +833,9 @@ spi17: spi@88c000 { interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -827,6 +851,9 @@ spi18: spi@890000 { interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -853,6 +880,9 @@ i2c19: i2c@894000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c19_default>; interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -917,6 +947,9 @@ i2c0: i2c@980000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c0_default>; interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -930,6 +963,9 @@ spi0: spi@980000 { interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -943,6 +979,9 @@ i2c1: i2c@984000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c1_default>; interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -956,6 +995,9 @@ spi1: spi@984000 { interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -969,6 +1011,9 @@ i2c2: i2c@988000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c2_default>; interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -982,6 +1027,9 @@ spi2: spi@988000 { interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1012,6 +1060,9 @@ spi3: spi@98c000 { interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, + <&gpi_dma0 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1025,6 +1076,9 @@ i2c4: i2c@990000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c4_default>; interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, + <&gpi_dma0 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1038,6 +1092,9 @@ spi4: spi@990000 { interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, + <&gpi_dma0 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1051,6 +1108,9 @@ i2c5: i2c@994000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c5_default>; interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, + <&gpi_dma0 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1064,6 +1124,9 @@ spi5: spi@994000 { interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, + <&gpi_dma0 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1077,6 +1140,9 @@ i2c6: i2c@998000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c6_default>; interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, + <&gpi_dma0 1 6 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1090,6 +1156,9 @@ spi6: spi@998000 { interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, + <&gpi_dma0 1 6 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1116,6 +1185,9 @@ i2c7: i2c@99c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c7_default>; interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, + <&gpi_dma0 1 7 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1180,6 +1252,9 @@ i2c8: i2c@a80000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c8_default>; interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1193,6 +1268,9 @@ spi8: spi@a80000 { interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_120mhz>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1206,6 +1284,9 @@ i2c9: i2c@a84000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c9_default>; interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1219,6 +1300,9 @@ spi9: spi@a84000 { interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1232,6 +1316,9 @@ i2c10: i2c@a88000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c10_default>; interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1245,6 +1332,9 @@ spi10: spi@a88000 { interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1258,6 +1348,9 @@ i2c11: i2c@a8c000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c11_default>; interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1271,6 +1364,9 @@ spi11: spi@a8c000 { interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1284,6 +1380,9 @@ i2c12: i2c@a90000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c12_default>; interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1297,6 +1396,9 @@ spi12: spi@a90000 { interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1310,6 +1412,9 @@ i2c13: i2c@a94000 { pinctrl-names = "default"; pinctrl-0 = <&qup_i2c13_default>; interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; @@ -1323,6 +1428,9 @@ spi13: spi@a94000 { interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&rpmhpd SM8350_CX>; operating-points-v2 = <&qup_opp_table_100mhz>; + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; #address-cells = <1>; #size-cells = <0>; status = "disabled"; -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels 2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson @ 2022-04-13 3:14 ` Vinod Koul 2022-04-13 3:57 ` Bjorn Andersson 2022-04-18 8:01 ` Vinod Koul 1 sibling, 1 reply; 10+ messages in thread From: Vinod Koul @ 2022-04-13 3:14 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 12-04-22, 14:51, Bjorn Andersson wrote: > The GENI I2C and SPI controllers may use the GPI DMA engine, define the > rx and tx channels for these controllers to enable this. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ > 1 file changed, 108 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 7e585d9e4c68..8547c0b2f060 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -721,6 +721,9 @@ i2c14: i2c@880000 { > pinctrl-names = "default"; > pinctrl-0 = <&qup_i2c14_default>; > interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, > + <&gpi_dma2 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", "rx"; I have been thinking about this. I dont feel this is right approach here as this is board dependent and having the firmware loaded on the board.. This was tested on HDK and can fail in MTP or other boards.. which might be in FIFO mode So, I think it might be apt to move these to board dtsi.. what do you think? -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels 2022-04-13 3:14 ` Vinod Koul @ 2022-04-13 3:57 ` Bjorn Andersson 2022-04-18 7:19 ` Vinod Koul 0 siblings, 1 reply; 10+ messages in thread From: Bjorn Andersson @ 2022-04-13 3:57 UTC (permalink / raw) To: Vinod Koul Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On Tue 12 Apr 20:14 PDT 2022, Vinod Koul wrote: > On 12-04-22, 14:51, Bjorn Andersson wrote: > > The GENI I2C and SPI controllers may use the GPI DMA engine, define the > > rx and tx channels for these controllers to enable this. > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > --- > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ > > 1 file changed, 108 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > index 7e585d9e4c68..8547c0b2f060 100644 > > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > @@ -721,6 +721,9 @@ i2c14: i2c@880000 { > > pinctrl-names = "default"; > > pinctrl-0 = <&qup_i2c14_default>; > > interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > > + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, > > + <&gpi_dma2 1 0 QCOM_GPI_I2C>; > > + dma-names = "tx", "rx"; > > I have been thinking about this. I dont feel this is right approach here > as this is board dependent and having the firmware loaded on the board.. > > This was tested on HDK and can fail in MTP or other boards.. which might > be in FIFO mode > But if the controller is in FIFO mode, then !fifo_disable so we wouldn't try to pick up the dmas. And in the opposite case, i.e. when fifo_disable, the introduction of the GPI implementation meant that the i2c driver wouldn't no longer probe without the dmas specified. Unfortunately we don't have any i2c busses enabled on the MTP currently, so I'm not able to validate this easily. For the SPI driver though, the same logic is used to invoke spi_geni_grab_gpi_chan(). So dmas will only be considered if fifo_disabled is set. That said, in the even that the SPI driver finds a fifo_disabled controller and dma_request_chan() returns an error, we will fall back to fifo mode instead. I'm not sure if that's desirable... If that makes sense, we should at least handle EPROBE_DEFER instead of falling through to fifo mode. Regards, Bjorn > So, I think it might be apt to move these to board dtsi.. what do you > think? > > -- > ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels 2022-04-13 3:57 ` Bjorn Andersson @ 2022-04-18 7:19 ` Vinod Koul 0 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-04-18 7:19 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 12-04-22, 20:57, Bjorn Andersson wrote: > On Tue 12 Apr 20:14 PDT 2022, Vinod Koul wrote: > > > On 12-04-22, 14:51, Bjorn Andersson wrote: > > > The GENI I2C and SPI controllers may use the GPI DMA engine, define the > > > rx and tx channels for these controllers to enable this. > > > > > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > > > --- > > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 108 +++++++++++++++++++++++++++ > > > 1 file changed, 108 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > > index 7e585d9e4c68..8547c0b2f060 100644 > > > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > > > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > > > @@ -721,6 +721,9 @@ i2c14: i2c@880000 { > > > pinctrl-names = "default"; > > > pinctrl-0 = <&qup_i2c14_default>; > > > interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > > > + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, > > > + <&gpi_dma2 1 0 QCOM_GPI_I2C>; > > > + dma-names = "tx", "rx"; > > > > I have been thinking about this. I dont feel this is right approach here > > as this is board dependent and having the firmware loaded on the board.. > > > > This was tested on HDK and can fail in MTP or other boards.. which might > > be in FIFO mode > > > > But if the controller is in FIFO mode, then !fifo_disable so we wouldn't > try to pick up the dmas. And in the opposite case, i.e. when > fifo_disable, the introduction of the GPI implementation meant that the > i2c driver wouldn't no longer probe without the dmas specified. > > Unfortunately we don't have any i2c busses enabled on the MTP currently, > so I'm not able to validate this easily. > > > For the SPI driver though, the same logic is used to invoke > spi_geni_grab_gpi_chan(). So dmas will only be considered if > fifo_disabled is set. Right, I tested that and it works just fine. So lets go ahead with this approach > That said, in the even that the SPI driver finds a fifo_disabled > controller and dma_request_chan() returns an error, we will fall back to > fifo mode instead. I'm not sure if that's desirable... I agree, we should not fall back, that does not make sense at all -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels 2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson 2022-04-13 3:14 ` Vinod Koul @ 2022-04-18 8:01 ` Vinod Koul 1 sibling, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-04-18 8:01 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 12-04-22, 14:51, Bjorn Andersson wrote: > The GENI I2C and SPI controllers may use the GPI DMA engine, define the > rx and tx channels for these controllers to enable this. Reviewed-by: Vinod Koul <vkoul@kernel.org> -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 2022-04-12 21:51 [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Bjorn Andersson 2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson @ 2022-04-12 21:51 ` Bjorn Andersson 2022-04-18 8:02 ` Vinod Koul 2022-04-18 7:18 ` [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Vinod Koul 2022-04-21 14:26 ` Bjorn Andersson 3 siblings, 1 reply; 10+ messages in thread From: Bjorn Andersson @ 2022-04-12 21:51 UTC (permalink / raw) To: Bjorn Andersson, Vinod Koul Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel Some versions of the firmware for the SM8350 Hardware Development Kit (HDK) has FIFO mode disabled for i2c13 and must thus use GPI DMA. Enable &gpi_dma1 to allow this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- arch/arm64/boot/dts/qcom/sm8350-hdk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts index 8c33fce0b414..246006ab4a2b 100644 --- a/arch/arm64/boot/dts/qcom/sm8350-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8350-hdk.dts @@ -213,6 +213,10 @@ &cdsp { firmware-name = "qcom/sm8350/cdsp.mbn"; }; +&gpi_dma1 { + status = "okay"; +}; + &gpu { status = "okay"; }; -- 2.35.1 ^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 2022-04-12 21:51 ` [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Bjorn Andersson @ 2022-04-18 8:02 ` Vinod Koul 0 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-04-18 8:02 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 12-04-22, 14:51, Bjorn Andersson wrote: > Some versions of the firmware for the SM8350 Hardware Development Kit > (HDK) has FIFO mode disabled for i2c13 and must thus use GPI DMA. Enable > &gpi_dma1 to allow this. Reviewed-by: Vinod Koul <vkoul@kernel.org> -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines 2022-04-12 21:51 [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Bjorn Andersson 2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson 2022-04-12 21:51 ` [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Bjorn Andersson @ 2022-04-18 7:18 ` Vinod Koul 2022-04-21 14:26 ` Bjorn Andersson 3 siblings, 0 replies; 10+ messages in thread From: Vinod Koul @ 2022-04-18 7:18 UTC (permalink / raw) To: Bjorn Andersson Cc: Rob Herring, Krzysztof Kozlowski, linux-arm-msm, devicetree, linux-kernel On 12-04-22, 14:51, Bjorn Andersson wrote: > The Qualcomm SM8350 has three GPI DMA engines, add definitions for > these. Reviewed-by: Vinod Koul <vkoul@kernel.org> -- ~Vinod ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines 2022-04-12 21:51 [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Bjorn Andersson ` (2 preceding siblings ...) 2022-04-18 7:18 ` [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Vinod Koul @ 2022-04-21 14:26 ` Bjorn Andersson 3 siblings, 0 replies; 10+ messages in thread From: Bjorn Andersson @ 2022-04-21 14:26 UTC (permalink / raw) To: Vinod Koul, Bjorn Andersson Cc: Krzysztof Kozlowski, devicetree, Rob Herring, linux-kernel, linux-arm-msm On Tue, 12 Apr 2022 14:51:35 -0700, Bjorn Andersson wrote: > The Qualcomm SM8350 has three GPI DMA engines, add definitions for > these. > > Applied, thanks! [1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines commit: bc08fbf49bc87e7613717e41674303905a9934fc [2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels commit: ddc97e7d1765cb2bf6089e211dae8e0b63cb3892 [3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 commit: 83b8347a858d06f7d070663cc3898215d3d299a0 Best regards, -- Bjorn Andersson <bjorn.andersson@linaro.org> ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-04-21 14:27 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-12 21:51 [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Bjorn Andersson 2022-04-12 21:51 ` [PATCH 2/3] arm64: dts: qcom: sm8350: Add GENI I2C/SPI DMA channels Bjorn Andersson 2022-04-13 3:14 ` Vinod Koul 2022-04-13 3:57 ` Bjorn Andersson 2022-04-18 7:19 ` Vinod Koul 2022-04-18 8:01 ` Vinod Koul 2022-04-12 21:51 ` [PATCH 3/3] arm64: dts: qcom: sm8350-hdk: Enable &gpi_dma1 Bjorn Andersson 2022-04-18 8:02 ` Vinod Koul 2022-04-18 7:18 ` [PATCH 1/3] arm64: dts: qcom: sm8350: Define GPI DMA engines Vinod Koul 2022-04-21 14:26 ` Bjorn Andersson
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