[PATCH 1/7] dt-bindings: usb: mediatek,mtu3: add binding for MT8195 SoC

[PATCH 1/7] dt-bindings: usb: mediatek,mtu3: add binding for MT8195 SoC

[Fabien Parent]

Add binding to support the mtu3 driver on the MT8195 SoC.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
index df766f8de872..37b02a841dc4 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
@@ -25,6 +25,7 @@ properties:
           - mediatek,mt8173-mtu3
           - mediatek,mt8183-mtu3
           - mediatek,mt8192-mtu3
+          - mediatek,mt8195-mtu3
       - const: mediatek,mtu3
 
   reg:
-- 
2.36.0

[PATCH 2/7] arm64: dts: mediatek: mt8195: add ssusb support

[Fabien Parent]

Add SSUSB support for MT8195. In order to not break any boards, this
commit also enable SSUSB for every board that has xhci0 enabled. The
boards are configured as host-only, in order to not change the current
behavior of the interface.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8195-demo.dts |  5 +++
 arch/arm64/boot/dts/mediatek/mt8195-evb.dts  |  5 +++
 arch/arm64/boot/dts/mediatek/mt8195.dtsi     | 37 ++++++++++++++------
 3 files changed, 36 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 66037462263e..08cab3b3943b 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -402,6 +402,11 @@ &pmic {
 	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
 };
 
+&ssusb {
+	dr_mode = "host";
+	status = "okay";
+};
+
 &uart0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&uart0_pins>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index db25a515e420..d49ae8605e67 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -138,6 +138,11 @@ pins {
 	};
 };
 
+&ssusb {
+	dr_mode = "host";
+	status = "okay";
+};
+
 &u3phy0 {
 	status="okay";
 };
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 2a525c1c74ef..aa05071a80b8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -912,25 +912,40 @@ spis1: spi@1101e000 {
 			status = "disabled";
 		};
 
-		xhci0: usb@11200000 {
-			compatible = "mediatek,mt8195-xhci",
-				     "mediatek,mtk-xhci";
-			reg = <0 0x11200000 0 0x1000>,
+		ssusb: usb@11201000 {
+			compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
+			reg = <0 0x11201000 0 0x2dff>,
 			      <0 0x11203e00 0 0x0100>;
 			reg-names = "mac", "ippc";
-			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
 			phys = <&u2port0 PHY_TYPE_USB2>,
 			       <&u3port0 PHY_TYPE_USB3>;
-			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
-					  <&topckgen CLK_TOP_SSUSB_XHCI>;
-			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
-						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
 			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
 				 <&topckgen CLK_TOP_SSUSB_REF>,
-				 <&apmixedsys CLK_APMIXED_USB1PLL>,
 				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
-			clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+			clock-names = "sys_ck", "ref_ck", "mcu_ck";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
 			status = "disabled";
+
+			xhci0: usb@11200000 {
+				compatible = "mediatek,mt8195-xhci",
+					     "mediatek,mtk-xhci";
+				reg = <0 0x11200000 0 0x1000>;
+				reg-names = "mac";
+				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+				assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+						  <&topckgen CLK_TOP_SSUSB_XHCI>;
+				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+							 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+				clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+					 <&topckgen CLK_TOP_SSUSB_REF>,
+					 <&apmixedsys CLK_APMIXED_USB1PLL>,
+					 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+				clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+				status = "disabled";
+			};
 		};
 
 		mmc0: mmc@11230000 {
-- 
2.36.0

[PATCH 3/7] arm64: dts: mediatek: mt8195: add ethernet device node

[Fabien Parent]

From: Biao Huang <biao.huang@mediatek.com>

This commit adds device node for mt8195 ethernet.

Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
This patch comes from https://lore.kernel.org/all/20211207015505.16746-7-biao.huang@mediatek.com/

The differences between that patch and this patch is that:
* The EVB dts modification has been split into its own commit
* The patch was rebased to fix merge conflict with the upstream mt8195.dtsi file
* Re-ordered the node to be correctly sorted based on node address

 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70 ++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index aa05071a80b8..a58641d1cab0 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -912,6 +912,76 @@ spis1: spi@1101e000 {
 			status = "disabled";
 		};
 
+		eth: ethernet@11021000 {
+			compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
+			reg = <0 0x11021000 0 0x4000>;
+			interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>;
+			interrupt-names = "macirq";
+			mac-address = [00 55 7b b5 7d f7];
+			clock-names = "axi",
+				      "apb",
+				      "mac_main",
+				      "ptp_ref",
+				      "rmii_internal",
+				      "mac_cg";
+			clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
+				 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>,
+				 <&topckgen CLK_TOP_SNPS_ETH_250M>,
+				 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+				 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
+				 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+			assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
+					  <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>,
+					  <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>;
+			assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
+						 <&topckgen CLK_TOP_ETHPLL_D8>,
+						 <&topckgen CLK_TOP_ETHPLL_D10>;
+			power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
+			mediatek,pericfg = <&infracfg_ao>;
+			snps,axi-config = <&stmmac_axi_setup>;
+			snps,mtl-rx-config = <&mtl_rx_setup>;
+			snps,mtl-tx-config = <&mtl_tx_setup>;
+			snps,txpbl = <16>;
+			snps,rxpbl = <16>;
+			clk_csr = <0>;
+			status = "disabled";
+
+			stmmac_axi_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <0x7>;
+				snps,rd_osr_lmt = <0x7>;
+				snps,blen = <0 0 0 0 16 8 4>;
+			};
+
+			mtl_rx_setup: rx-queues-config {
+				snps,rx-queues-to-use = <1>;
+				snps,rx-sched-sp;
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+					snps,priority = <0x0>;
+				};
+			};
+			mtl_tx_setup: tx-queues-config {
+				snps,tx-queues-to-use = <3>;
+				snps,tx-sched-wrr;
+				queue0 {
+					snps,weight = <0x10>;
+					snps,dcb-algorithm;
+					snps,priority = <0x0>;
+				};
+				queue1 {
+					snps,weight = <0x11>;
+					snps,dcb-algorithm;
+					snps,priority = <0x1>;
+				};
+				queue2 {
+					snps,weight = <0x12>;
+					snps,dcb-algorithm;
+					snps,priority = <0x2>;
+				};
+			};
+		};
+
 		ssusb: usb@11201000 {
 			compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";
 			reg = <0 0x11201000 0 0x2dff>,
-- 
2.36.0

[PATCH 4/7] arm64: dts: mediatek: mt8195-evb: enable ethernet

[Fabien Parent]

From: Biao Huang <biao.huang@mediatek.com>

Add ethernet support for MT8195 EVB.

Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
This patch comes from https://lore.kernel.org/all/20211207015505.16746-7-biao.huang@mediatek.com/

The differences between that patch and this patch is that:
* The EVB dts modification has been split into its own commit
* The patch was rebased to fix merge conflict with the upstream mt8195-evb.dts file
* Re-ordered the node to be correctly sorted based on phandle name 
* Re-ordered the pins for the pinctrl to be sorted by node name
* Fixed dtbs_check: use - instead of _ in node names + prefix pins node with pins-

 arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 90 +++++++++++++++++++++
 1 file changed, 90 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
index d49ae8605e67..0b04421942ac 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -5,6 +5,7 @@
  */
 /dts-v1/;
 #include "mt8195.dtsi"
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "MediaTek MT8195 evaluation board";
@@ -28,6 +29,29 @@ &auxadc {
 	status = "okay";
 };
 
+&eth {
+	phy-mode ="rgmii-rxid";
+	phy-handle = <&eth_phy0>;
+	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+	snps,reset-delays-us = <0 10000 10000>;
+	mediatek,tx-delay-ps = <2030>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&eth_default_pins>;
+	pinctrl-1 = <&eth_sleep_pins>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		eth_phy0: eth_phy0@1 {
+			compatible = "ethernet-phy-id001c.c916";
+			#phy-cells = <0>;
+			reg = <0x1>;
+		};
+	};
+};
+
 &i2c0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&i2c0_pin>;
@@ -69,6 +93,72 @@ flash@0 {
 };
 
 &pio {
+	eth_default_pins: eth-default-pins {
+		pins-cc {
+			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+		pins-mdio {
+			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+			input-enable;
+		};
+		pins-power {
+			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+				 <PINMUX_GPIO92__FUNC_GPIO92>;
+			output-high;
+		};
+		pins-rxd {
+			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+		};
+		pins-txd {
+			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+	};
+
+	eth_sleep_pins: eth-sleep-pins {
+		pins-cc {
+			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+				 <PINMUX_GPIO88__FUNC_GPIO88>,
+				 <PINMUX_GPIO87__FUNC_GPIO87>,
+				 <PINMUX_GPIO86__FUNC_GPIO86>;
+		};
+		pins-mdio {
+			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+				 <PINMUX_GPIO90__FUNC_GPIO90>;
+			input-disable;
+			bias-disable;
+		};
+		pins-power {
+			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+				 <PINMUX_GPIO92__FUNC_GPIO92>;
+			input-disable;
+			bias-disable;
+		};
+		pins-rxd {
+			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+				 <PINMUX_GPIO82__FUNC_GPIO82>,
+				 <PINMUX_GPIO83__FUNC_GPIO83>,
+				 <PINMUX_GPIO84__FUNC_GPIO84>;
+		};
+		pins-txd {
+			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+				 <PINMUX_GPIO78__FUNC_GPIO78>,
+				 <PINMUX_GPIO79__FUNC_GPIO79>,
+				 <PINMUX_GPIO80__FUNC_GPIO80>;
+		};
+	};
+
 	i2c0_pin: i2c0-pins {
 		pins {
 			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
-- 
2.36.0

[PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet

[Fabien Parent]

Enable ethernet on the MT8195 demo board.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108 +++++++++++++++++++
 1 file changed, 108 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 08cab3b3943b..0b7985486e2a 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -80,6 +80,30 @@ optee_reserved: optee@43200000 {
 	};
 };
 
+&eth {
+	phy-mode = "rgmii-rxid";
+	phy-handle = <&eth_phy>;
+	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
+	snps,reset-delays-us = <0 10000 10000>;
+	mediatek,tx-delay-ps = <2030>;
+	pinctrl-names = "default", "sleep";
+	pinctrl-0 = <&eth_default_pins>;
+	pinctrl-1 = <&eth_sleep_pins>;
+	status = "okay";
+
+	mdio {
+		compatible = "snps,dwmac-mdio";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eth_phy: phy@1 {
+			compatible = "ethernet-phy-id001c.c916";
+			#phy-cells = <0>;
+			reg = <0x1>;
+		};
+	};
+};
+
 &i2c6 {
 	clock-frequency = <400000>;
 	pinctrl-0 = <&i2c6_pins>;
@@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
 };
 
 &pio {
+	eth_default_pins: eth-default-pins {
+		pins-cc {
+			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
+				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
+				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
+				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+
+		pins-mdio {
+			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
+				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
+			input-enable;
+		};
+
+		pins-phy-reset {
+			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+		};
+
+		pins-power {
+			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+				 <PINMUX_GPIO92__FUNC_GPIO92>;
+			output-high;
+		};
+
+		pins-rxd {
+			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
+				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
+				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
+				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
+		};
+
+		pins-txd {
+			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
+				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
+				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
+				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
+			drive-strength = <MTK_DRIVE_8mA>;
+		};
+	};
+
+	eth_sleep_pins: eth-sleep-pins {
+		pins-cc {
+			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
+				 <PINMUX_GPIO88__FUNC_GPIO88>,
+				 <PINMUX_GPIO87__FUNC_GPIO87>,
+				 <PINMUX_GPIO86__FUNC_GPIO86>;
+		};
+
+		pins-mdio {
+			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
+				 <PINMUX_GPIO90__FUNC_GPIO90>;
+			input-disable;
+			bias-disable;
+		};
+
+		pins-phy-reset {
+			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
+			input-disable;
+			bias-disable;
+		};
+
+		pins-power {
+			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
+				 <PINMUX_GPIO92__FUNC_GPIO92>;
+			input-disable;
+			bias-disable;
+		};
+
+		pins-rxd {
+			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
+				 <PINMUX_GPIO82__FUNC_GPIO82>,
+				 <PINMUX_GPIO83__FUNC_GPIO83>,
+				 <PINMUX_GPIO84__FUNC_GPIO84>;
+		};
+
+		pins-txd {
+			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
+				 <PINMUX_GPIO78__FUNC_GPIO78>,
+				 <PINMUX_GPIO79__FUNC_GPIO79>,
+				 <PINMUX_GPIO80__FUNC_GPIO80>;
+		};
+	};
+
 	gpio_keys_pins: gpio-keys-pins {
 		pins {
 			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
-- 
2.36.0

[PATCH 6/7] arm64: dts: mediatek: mt8195-demo: Remove input-name property

[Fabien Parent]

This property doesn't seem to exist in the documentation nor
in source code, let's remove it from the device-tree.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
This patch is related to [0].

[0] https://lore.kernel.org/all/20211123065158.1383182-1-danct12@riseup.net/

 arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 1 -
 1 file changed, 1 deletion(-)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index 0b7985486e2a..d1f650d99d7e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -35,7 +35,6 @@ optee {
 
 	gpio-keys {
 		compatible = "gpio-keys";
-		input-name = "gpio-keys";
 		pinctrl-names = "default";
 		pinctrl-0 = <&gpio_keys_pins>;
 
-- 
2.36.0

[PATCH 7/7] arm64: dts: mediatek: mt8195-demo: enable uart1

[Fabien Parent]

The UART1 is exposed on a header. Enable the uart1 node to be able to
use it.

Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
 arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
index d1f650d99d7e..aa41df865c9c 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
@@ -520,6 +520,12 @@ &uart0 {
 	status = "okay";
 };
 
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
 &u3phy0 {
 	status = "okay";
 };
-- 
2.36.0

Re: [PATCH 1/7] dt-bindings: usb: mediatek, mtu3: add binding for MT8195 SoC

[Macpaul Lin]

On Tue, 2022-04-26 at 15:40 +0200, Fabien Parent wrote:
> Add binding to support the mtu3 driver on the MT8195 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
> b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
> index df766f8de872..37b02a841dc4 100644
> --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
> +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml
> @@ -25,6 +25,7 @@ properties:
>            - mediatek,mt8173-mtu3
>            - mediatek,mt8183-mtu3
>            - mediatek,mt8192-mtu3
> +          - mediatek,mt8195-mtu3
>        - const: mediatek,mtu3
>  
>    reg:

Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>

Regards,
Macpaul Lin

Re: [PATCH 3/7] arm64: dts: mediatek: mt8195: add ethernet device node

[Macpaul Lin]

On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
> From: Biao Huang <biao.huang@mediatek.com>
> 
> This commit adds device node for mt8195 ethernet.
> 
> Signed-off-by: Biao Huang <biao.huang@mediatek.com>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
> This patch comes from 
> https://urldefense.com/v3/__https://lore.kernel.org/all/20211207015505.16746-7-biao.huang@mediatek.com/__;!!CTRNKA9wMg0ARbw!zMbdbHaOYVgzrhlWiTJyY40dCmVZaK1jStklyKdY5qoDUoA5uoISlYOx9E801CRuEHQ$
>  
> 
> The differences between that patch and this patch is that:
> * The EVB dts modification has been split into its own commit
> * The patch was rebased to fix merge conflict with the upstream
> mt8195.dtsi file
> * Re-ordered the node to be correctly sorted based on node address
> 
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi | 70
> ++++++++++++++++++++++++
>  1 file changed, 70 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index aa05071a80b8..a58641d1cab0 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -912,6 +912,76 @@ spis1: spi@1101e000 {
>  			status = "disabled";
>  		};
>  
> +		eth: ethernet@11021000 {
> +			compatible = "mediatek,mt8195-gmac",
> "snps,dwmac-5.10a";
> +			reg = <0 0x11021000 0 0x4000>;
> +			interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH
> 0>;
> +			interrupt-names = "macirq";
> +			mac-address = [00 55 7b b5 7d f7];
> +			clock-names = "axi",
> +				      "apb",
> +				      "mac_main",
> +				      "ptp_ref",
> +				      "rmii_internal",
> +				      "mac_cg";
> +			clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>,
> +				 <&pericfg_ao
> CLK_PERI_AO_ETHERNET_BUS>,
> +				 <&topckgen CLK_TOP_SNPS_ETH_250M>,
> +				 <&topckgen
> CLK_TOP_SNPS_ETH_62P4M_PTP>,
> +				 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>,
> +				 <&pericfg_ao
> CLK_PERI_AO_ETHERNET_MAC>;
> +			assigned-clocks = <&topckgen
> CLK_TOP_SNPS_ETH_250M>,
> +					  <&topckgen
> CLK_TOP_SNPS_ETH_62P4M_PTP>,
> +					  <&topckgen
> CLK_TOP_SNPS_ETH_50M_RMII>;
> +			assigned-clock-parents = <&topckgen
> CLK_TOP_ETHPLL_D2>,
> +						 <&topckgen
> CLK_TOP_ETHPLL_D8>,
> +						 <&topckgen
> CLK_TOP_ETHPLL_D10>;
> +			power-domains = <&spm
> MT8195_POWER_DOMAIN_ETHER>;
> +			mediatek,pericfg = <&infracfg_ao>;
> +			snps,axi-config = <&stmmac_axi_setup>;
> +			snps,mtl-rx-config = <&mtl_rx_setup>;
> +			snps,mtl-tx-config = <&mtl_tx_setup>;
> +			snps,txpbl = <16>;
> +			snps,rxpbl = <16>;
> +			clk_csr = <0>;
> +			status = "disabled";
> +
> +			stmmac_axi_setup: stmmac-axi-config {
> +				snps,wr_osr_lmt = <0x7>;
> +				snps,rd_osr_lmt = <0x7>;
> +				snps,blen = <0 0 0 0 16 8 4>;
> +			};
> +
> +			mtl_rx_setup: rx-queues-config {
> +				snps,rx-queues-to-use = <1>;
> +				snps,rx-sched-sp;
> +				queue0 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel =
> <0x0>;
> +					snps,priority = <0x0>;
> +				};
> +			};
> +			mtl_tx_setup: tx-queues-config {
> +				snps,tx-queues-to-use = <3>;
> +				snps,tx-sched-wrr;
> +				queue0 {
> +					snps,weight = <0x10>;
> +					snps,dcb-algorithm;
> +					snps,priority = <0x0>;
> +				};
> +				queue1 {
> +					snps,weight = <0x11>;
> +					snps,dcb-algorithm;
> +					snps,priority = <0x1>;
> +				};
> +				queue2 {
> +					snps,weight = <0x12>;
> +					snps,dcb-algorithm;
> +					snps,priority = <0x2>;
> +				};
> +			};
> +		};
> +
>  		ssusb: usb@11201000 {
>  			compatible ="mediatek,mt8195-mtu3",
> "mediatek,mtu3";
>  			reg = <0 0x11201000 0 0x2dff>,

Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>

Regards,
Macpaul Lin

Re: [PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet

[Macpaul Lin]

On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
> Enable ethernet on the MT8195 demo board.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108
> +++++++++++++++++++
>  1 file changed, 108 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> index 08cab3b3943b..0b7985486e2a 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> @@ -80,6 +80,30 @@ optee_reserved: optee@43200000 {
>  	};
>  };
>  
> +&eth {
> +	phy-mode = "rgmii-rxid";
> +	phy-handle = <&eth_phy>;
> +	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
> +	snps,reset-delays-us = <0 10000 10000>;
> +	mediatek,tx-delay-ps = <2030>;
> +	pinctrl-names = "default", "sleep";
> +	pinctrl-0 = <&eth_default_pins>;
> +	pinctrl-1 = <&eth_sleep_pins>;
> +	status = "okay";
> +
> +	mdio {
> +		compatible = "snps,dwmac-mdio";
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		eth_phy: phy@1 {
> +			compatible = "ethernet-phy-id001c.c916";
> +			#phy-cells = <0>;
> +			reg = <0x1>;
> +		};
> +	};
> +};
> +
>  &i2c6 {
>  	clock-frequency = <400000>;
>  	pinctrl-0 = <&i2c6_pins>;
> @@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
>  };
>  
>  &pio {
> +	eth_default_pins: eth-default-pins {
> +		pins-cc {
> +			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
> +				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
> +				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
> +				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
> +			drive-strength = <MTK_DRIVE_8mA>;
> +		};
> +
> +		pins-mdio {
> +			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
> +				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
> +			input-enable;
> +		};
> +
> +		pins-phy-reset {
> +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> +		};
> +
> +		pins-power {
> +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> +			output-high;
> +		};
> +
> +		pins-rxd {
> +			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
> +				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
> +				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
> +				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
> +		};
> +
> +		pins-txd {
> +			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
> +				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
> +				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
> +				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
> +			drive-strength = <MTK_DRIVE_8mA>;
> +		};
> +	};
> +
> +	eth_sleep_pins: eth-sleep-pins {
> +		pins-cc {
> +			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
> +				 <PINMUX_GPIO88__FUNC_GPIO88>,
> +				 <PINMUX_GPIO87__FUNC_GPIO87>,
> +				 <PINMUX_GPIO86__FUNC_GPIO86>;
> +		};
> +
> +		pins-mdio {
> +			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
> +				 <PINMUX_GPIO90__FUNC_GPIO90>;
> +			input-disable;
> +			bias-disable;
> +		};
> +
> +		pins-phy-reset {
> +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> +			input-disable;
> +			bias-disable;
> +		};
> +
> +		pins-power {
> +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> +			input-disable;
> +			bias-disable;
> +		};
> +
> +		pins-rxd {
> +			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
> +				 <PINMUX_GPIO82__FUNC_GPIO82>,
> +				 <PINMUX_GPIO83__FUNC_GPIO83>,
> +				 <PINMUX_GPIO84__FUNC_GPIO84>;
> +		};
> +
> +		pins-txd {
> +			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
> +				 <PINMUX_GPIO78__FUNC_GPIO78>,
> +				 <PINMUX_GPIO79__FUNC_GPIO79>,
> +				 <PINMUX_GPIO80__FUNC_GPIO80>;
> +		};
> +	};
> +
>  	gpio_keys_pins: gpio-keys-pins {
>  		pins {
>  			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;

Tested-by: Macpaul Lin <macpaul.lin@mediatek.com>

Regards,
Macpaul Lin

Re: [PATCH 1/7] dt-bindings: usb: mediatek,mtu3: add binding for MT8195 SoC

[Krzysztof Kozlowski]

On 26/04/2022 15:40, Fabien Parent wrote:
> Add binding to support the mtu3 driver on the MT8195 SoC.
> 
> Signed-off-by: Fabien Parent <fparent@baylibre.com>


Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>


Best regards,
Krzysztof

Re: [PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet

[Matthias Brugger]

On 27/04/2022 08:25, Macpaul Lin wrote:
> On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
>> Enable ethernet on the MT8195 demo board.
>>
>> Signed-off-by: Fabien Parent <fparent@baylibre.com>
>> ---
>>   arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108
>> +++++++++++++++++++
>>   1 file changed, 108 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
>> b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
>> index 08cab3b3943b..0b7985486e2a 100644
>> --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
>> +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
>> @@ -80,6 +80,30 @@ optee_reserved: optee@43200000 {
>>   	};
>>   };
>>   
>> +&eth {
>> +	phy-mode = "rgmii-rxid";
>> +	phy-handle = <&eth_phy>;
>> +	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
>> +	snps,reset-delays-us = <0 10000 10000>;
>> +	mediatek,tx-delay-ps = <2030>;
>> +	pinctrl-names = "default", "sleep";
>> +	pinctrl-0 = <&eth_default_pins>;
>> +	pinctrl-1 = <&eth_sleep_pins>;
>> +	status = "okay";
>> +
>> +	mdio {
>> +		compatible = "snps,dwmac-mdio";
>> +		#address-cells = <1>;
>> +		#size-cells = <0>;
>> +
>> +		eth_phy: phy@1 {
>> +			compatible = "ethernet-phy-id001c.c916";
>> +			#phy-cells = <0>;
>> +			reg = <0x1>;
>> +		};
>> +	};
>> +};
>> +
>>   &i2c6 {
>>   	clock-frequency = <400000>;
>>   	pinctrl-0 = <&i2c6_pins>;
>> @@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
>>   };
>>   
>>   &pio {
>> +	eth_default_pins: eth-default-pins {
>> +		pins-cc {
>> +			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
>> +				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
>> +				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
>> +				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
>> +			drive-strength = <MTK_DRIVE_8mA>;
>> +		};
>> +
>> +		pins-mdio {
>> +			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
>> +				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
>> +			input-enable;
>> +		};
>> +
>> +		pins-phy-reset {
>> +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
>> +		};
>> +
>> +		pins-power {
>> +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
>> +				 <PINMUX_GPIO92__FUNC_GPIO92>;
>> +			output-high;
>> +		};
>> +
>> +		pins-rxd {
>> +			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
>> +				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
>> +				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
>> +				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
>> +		};
>> +
>> +		pins-txd {
>> +			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
>> +				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
>> +				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
>> +				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
>> +			drive-strength = <MTK_DRIVE_8mA>;
>> +		};
>> +	};
>> +
>> +	eth_sleep_pins: eth-sleep-pins {
>> +		pins-cc {
>> +			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
>> +				 <PINMUX_GPIO88__FUNC_GPIO88>,
>> +				 <PINMUX_GPIO87__FUNC_GPIO87>,
>> +				 <PINMUX_GPIO86__FUNC_GPIO86>;
>> +		};
>> +
>> +		pins-mdio {
>> +			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
>> +				 <PINMUX_GPIO90__FUNC_GPIO90>;
>> +			input-disable;
>> +			bias-disable;
>> +		};
>> +
>> +		pins-phy-reset {
>> +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
>> +			input-disable;
>> +			bias-disable;
>> +		};
>> +
>> +		pins-power {
>> +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
>> +				 <PINMUX_GPIO92__FUNC_GPIO92>;
>> +			input-disable;
>> +			bias-disable;
>> +		};
>> +
>> +		pins-rxd {
>> +			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
>> +				 <PINMUX_GPIO82__FUNC_GPIO82>,
>> +				 <PINMUX_GPIO83__FUNC_GPIO83>,
>> +				 <PINMUX_GPIO84__FUNC_GPIO84>;
>> +		};
>> +
>> +		pins-txd {
>> +			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
>> +				 <PINMUX_GPIO78__FUNC_GPIO78>,
>> +				 <PINMUX_GPIO79__FUNC_GPIO79>,
>> +				 <PINMUX_GPIO80__FUNC_GPIO80>;
>> +		};
>> +	};
>> +
>>   	gpio_keys_pins: gpio-keys-pins {
>>   		pins {
>>   			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
> 
> Tested-by: Macpaul Lin <macpaul.lin@mediatek.com>
> 

I get the following error:
Error: arch/arm64/boot/dts/mediatek/mt8195.dtsi:582.26-27 syntax error



How did you test?

Regards,
Matthias

Re: [PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet

[Fabien Parent]

[-- Attachment #1: Type: text/plain, Size: 5329 bytes --]

On Fri, Apr 29, 2022 at 04:00:32PM +0200, Matthias Brugger wrote:
> 
> 
> On 27/04/2022 08:25, Macpaul Lin wrote:
> > On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
> > > Enable ethernet on the MT8195 demo board.
> > > 
> > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > ---
> > >   arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108
> > > +++++++++++++++++++
> > >   1 file changed, 108 insertions(+)
> > > 
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > index 08cab3b3943b..0b7985486e2a 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > @@ -80,6 +80,30 @@ optee_reserved: optee@43200000 {
> > >   	};
> > >   };
> > > +&eth {
> > > +	phy-mode = "rgmii-rxid";
> > > +	phy-handle = <&eth_phy>;
> > > +	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
> > > +	snps,reset-delays-us = <0 10000 10000>;
> > > +	mediatek,tx-delay-ps = <2030>;
> > > +	pinctrl-names = "default", "sleep";
> > > +	pinctrl-0 = <&eth_default_pins>;
> > > +	pinctrl-1 = <&eth_sleep_pins>;
> > > +	status = "okay";
> > > +
> > > +	mdio {
> > > +		compatible = "snps,dwmac-mdio";
> > > +		#address-cells = <1>;
> > > +		#size-cells = <0>;
> > > +
> > > +		eth_phy: phy@1 {
> > > +			compatible = "ethernet-phy-id001c.c916";
> > > +			#phy-cells = <0>;
> > > +			reg = <0x1>;
> > > +		};
> > > +	};
> > > +};
> > > +
> > >   &i2c6 {
> > >   	clock-frequency = <400000>;
> > >   	pinctrl-0 = <&i2c6_pins>;
> > > @@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
> > >   };
> > >   &pio {
> > > +	eth_default_pins: eth-default-pins {
> > > +		pins-cc {
> > > +			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
> > > +				 <PINMUX_GPIO88__FUNC_GBE_TXEN>,
> > > +				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
> > > +				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
> > > +			drive-strength = <MTK_DRIVE_8mA>;
> > > +		};
> > > +
> > > +		pins-mdio {
> > > +			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
> > > +				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
> > > +			input-enable;
> > > +		};
> > > +
> > > +		pins-phy-reset {
> > > +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> > > +		};
> > > +
> > > +		pins-power {
> > > +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> > > +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> > > +			output-high;
> > > +		};
> > > +
> > > +		pins-rxd {
> > > +			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
> > > +				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
> > > +				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
> > > +				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
> > > +		};
> > > +
> > > +		pins-txd {
> > > +			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
> > > +				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
> > > +				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
> > > +				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
> > > +			drive-strength = <MTK_DRIVE_8mA>;
> > > +		};
> > > +	};
> > > +
> > > +	eth_sleep_pins: eth-sleep-pins {
> > > +		pins-cc {
> > > +			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
> > > +				 <PINMUX_GPIO88__FUNC_GPIO88>,
> > > +				 <PINMUX_GPIO87__FUNC_GPIO87>,
> > > +				 <PINMUX_GPIO86__FUNC_GPIO86>;
> > > +		};
> > > +
> > > +		pins-mdio {
> > > +			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
> > > +				 <PINMUX_GPIO90__FUNC_GPIO90>;
> > > +			input-disable;
> > > +			bias-disable;
> > > +		};
> > > +
> > > +		pins-phy-reset {
> > > +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> > > +			input-disable;
> > > +			bias-disable;
> > > +		};
> > > +
> > > +		pins-power {
> > > +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> > > +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> > > +			input-disable;
> > > +			bias-disable;
> > > +		};
> > > +
> > > +		pins-rxd {
> > > +			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
> > > +				 <PINMUX_GPIO82__FUNC_GPIO82>,
> > > +				 <PINMUX_GPIO83__FUNC_GPIO83>,
> > > +				 <PINMUX_GPIO84__FUNC_GPIO84>;
> > > +		};
> > > +
> > > +		pins-txd {
> > > +			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
> > > +				 <PINMUX_GPIO78__FUNC_GPIO78>,
> > > +				 <PINMUX_GPIO79__FUNC_GPIO79>,
> > > +				 <PINMUX_GPIO80__FUNC_GPIO80>;
> > > +		};
> > > +	};
> > > +
> > >   	gpio_keys_pins: gpio-keys-pins {
> > >   		pins {
> > >   			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
> > 
> > Tested-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > 
> 
> I get the following error:
> Error: arch/arm64/boot/dts/mediatek/mt8195.dtsi:582.26-27 syntax error

I think he used my upstreaming branch where I store the patches I sent
and will send to the mailing list: [0].

I forgot there is a dependency between this patch and [1], and I forgot
to test this patch serie independenly from the other commits from my
branch. I will make sure to not forget next time.

So from this patch serie, only patch 1-2, 6-7 can be applied since they
don't have any hidden dependency:
  dt-bindings: usb: mediatek,mtu3: add binding for MT8195 SoC
  arm64: dts: mediatek: mt8195: add ssusb support
  arm64: dts: mediatek: mt8195-demo: Remove input-name property
  arm64: dts: mediatek: mt8195-demo: enable uart1

[0] https://github.com/Fabo/linux/tree/mt8195-demo
[1] https://lore.kernel.org/all/20210615173233.26682-7-tinghan.shen@mediatek.com/

> 
> 
> 
> How did you test?
> 
> Regards,
> Matthias

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Re: [PATCH 5/7] arm64: dts: mediatek: mt8195-demo: enable ethernet

[Macpaul Lin]

On Fri, 2022-04-29 at 17:22 +0200, Fabien Parent wrote:
> On Fri, Apr 29, 2022 at 04:00:32PM +0200, Matthias Brugger wrote:
> > 
> > 
> > On 27/04/2022 08:25, Macpaul Lin wrote:
> > > On Tue, 2022-04-26 at 15:41 +0200, Fabien Parent wrote:
> > > > Enable ethernet on the MT8195 demo board.
> > > > 
> > > > Signed-off-by: Fabien Parent <fparent@baylibre.com>
> > > > ---
> > > >   arch/arm64/boot/dts/mediatek/mt8195-demo.dts | 108
> > > > +++++++++++++++++++
> > > >   1 file changed, 108 insertions(+)
> > > > 
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > > b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > > index 08cab3b3943b..0b7985486e2a 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts
> > > > @@ -80,6 +80,30 @@ optee_reserved: optee@43200000 {
> > > >   	};
> > > >   };
> > > > +&eth {
> > > > +	phy-mode = "rgmii-rxid";
> > > > +	phy-handle = <&eth_phy>;
> > > > +	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
> > > > +	snps,reset-delays-us = <0 10000 10000>;
> > > > +	mediatek,tx-delay-ps = <2030>;
> > > > +	pinctrl-names = "default", "sleep";
> > > > +	pinctrl-0 = <&eth_default_pins>;
> > > > +	pinctrl-1 = <&eth_sleep_pins>;
> > > > +	status = "okay";
> > > > +
> > > > +	mdio {
> > > > +		compatible = "snps,dwmac-mdio";
> > > > +		#address-cells = <1>;
> > > > +		#size-cells = <0>;
> > > > +
> > > > +		eth_phy: phy@1 {
> > > > +			compatible = "ethernet-phy-
> > > > id001c.c916";
> > > > +			#phy-cells = <0>;
> > > > +			reg = <0x1>;
> > > > +		};
> > > > +	};
> > > > +};
> > > > +
> > > >   &i2c6 {
> > > >   	clock-frequency = <400000>;
> > > >   	pinctrl-0 = <&i2c6_pins>;
> > > > @@ -260,6 +284,90 @@ &mt6359_vsram_others_ldo_reg {
> > > >   };
> > > >   &pio {
> > > > +	eth_default_pins: eth-default-pins {
> > > > +		pins-cc {
> > > > +			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
> > > > +				 <PINMUX_GPIO88__FUNC_GBE_TXEN>
> > > > ,
> > > > +				 <PINMUX_GPIO87__FUNC_GBE_RXDV>
> > > > ,
> > > > +				 <PINMUX_GPIO86__FUNC_GBE_RXC>;
> > > > +			drive-strength = <MTK_DRIVE_8mA>;
> > > > +		};
> > > > +
> > > > +		pins-mdio {
> > > > +			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
> > > > +				 <PINMUX_GPIO90__FUNC_GBE_MDIO>
> > > > ;
> > > > +			input-enable;
> > > > +		};
> > > > +
> > > > +		pins-phy-reset {
> > > > +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> > > > +		};
> > > > +
> > > > +		pins-power {
> > > > +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> > > > +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> > > > +			output-high;
> > > > +		};
> > > > +
> > > > +		pins-rxd {
> > > > +			pinmux =
> > > > <PINMUX_GPIO81__FUNC_GBE_RXD3>,
> > > > +				 <PINMUX_GPIO82__FUNC_GBE_RXD2>
> > > > ,
> > > > +				 <PINMUX_GPIO83__FUNC_GBE_RXD1>
> > > > ,
> > > > +				 <PINMUX_GPIO84__FUNC_GBE_RXD0>
> > > > ;
> > > > +		};
> > > > +
> > > > +		pins-txd {
> > > > +			pinmux =
> > > > <PINMUX_GPIO77__FUNC_GBE_TXD3>,
> > > > +				 <PINMUX_GPIO78__FUNC_GBE_TXD2>
> > > > ,
> > > > +				 <PINMUX_GPIO79__FUNC_GBE_TXD1>
> > > > ,
> > > > +				 <PINMUX_GPIO80__FUNC_GBE_TXD0>
> > > > ;
> > > > +			drive-strength = <MTK_DRIVE_8mA>;
> > > > +		};
> > > > +	};
> > > > +
> > > > +	eth_sleep_pins: eth-sleep-pins {
> > > > +		pins-cc {
> > > > +			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
> > > > +				 <PINMUX_GPIO88__FUNC_GPIO88>,
> > > > +				 <PINMUX_GPIO87__FUNC_GPIO87>,
> > > > +				 <PINMUX_GPIO86__FUNC_GPIO86>;
> > > > +		};
> > > > +
> > > > +		pins-mdio {
> > > > +			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
> > > > +				 <PINMUX_GPIO90__FUNC_GPIO90>;
> > > > +			input-disable;
> > > > +			bias-disable;
> > > > +		};
> > > > +
> > > > +		pins-phy-reset {
> > > > +			pinmux = <PINMUX_GPIO93__FUNC_GPIO93>;
> > > > +			input-disable;
> > > > +			bias-disable;
> > > > +		};
> > > > +
> > > > +		pins-power {
> > > > +			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
> > > > +				 <PINMUX_GPIO92__FUNC_GPIO92>;
> > > > +			input-disable;
> > > > +			bias-disable;
> > > > +		};
> > > > +
> > > > +		pins-rxd {
> > > > +			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
> > > > +				 <PINMUX_GPIO82__FUNC_GPIO82>,
> > > > +				 <PINMUX_GPIO83__FUNC_GPIO83>,
> > > > +				 <PINMUX_GPIO84__FUNC_GPIO84>;
> > > > +		};
> > > > +
> > > > +		pins-txd {
> > > > +			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
> > > > +				 <PINMUX_GPIO78__FUNC_GPIO78>,
> > > > +				 <PINMUX_GPIO79__FUNC_GPIO79>,
> > > > +				 <PINMUX_GPIO80__FUNC_GPIO80>;
> > > > +		};
> > > > +	};
> > > > +
> > > >   	gpio_keys_pins: gpio-keys-pins {
> > > >   		pins {
> > > >   			pinmux =
> > > > <PINMUX_GPIO106__FUNC_GPIO106>;
> > > 
> > > Tested-by: Macpaul Lin <macpaul.lin@mediatek.com>
> > > 
> > 
> > I get the following error:
> > Error: arch/arm64/boot/dts/mediatek/mt8195.dtsi:582.26-27 syntax
> > error
> 
> I think he used my upstreaming branch where I store the patches I
> sent
> and will send to the mailing list: [0].
> 
> I forgot there is a dependency between this patch and [1], and I
> forgot
> to test this patch serie independenly from the other commits from my
> branch. I will make sure to not forget next time.
> 
> So from this patch serie, only patch 1-2, 6-7 can be applied since
> they
> don't have any hidden dependency:
>   dt-bindings: usb: mediatek,mtu3: add binding for MT8195 SoC
>   arm64: dts: mediatek: mt8195: add ssusb support
>   arm64: dts: mediatek: mt8195-demo: Remove input-name property
>   arm64: dts: mediatek: mt8195-demo: enable uart1
> 
> [0] https://github.com/Fabo/linux/tree/mt8195-demo
> [1] 
> https://lore.kernel.org/all/20210615173233.26682-7-tinghan.shen@mediatek.com/
> 
> > 
> > 
> > 
> > How did you test?
> > 
> > Regards,
> > Matthias

Sorry for replying the mail late.

Actually, I've maintained a working tree based on 5.18-rc1 with minimum
changeset support booting to UART. Then pickup required patches for
testing individaul drivers. I should add the patch dependencies in
previous mail if there were a dependency list. However, attach a
dependency list might still be confusing since there is lots of patches
keep updating everyday for mediatek tree. I guess the best practice for
avoiding this kind of mess is using for-next tree to verify new patches
instead of using 5.18-rc1 tree since some of the dependencies were
already merged. Sorry for wasting your time.

I'll replace my local
working tree to Matthias's working tree for verifing these kind of
patches.

Thanks!
Macpaul Lin