From: Ben Dooks <ben.dooks@sifive.com>
To: linux-pwm@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Lee Jones <lee.jones@linaro.org>,
u.kleine-koenig@pengutronix.de,
Thierry Reding <thierry.reding@gmail.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Greentime Hu <greentime.hu@sifive.com>,
Ben Dooks <ben.dooks@sifive.com>
Subject: [[PATCH v2] 9/9] pwm: dwc: add PWM bit unset in get_state call
Date: Mon, 25 Jul 2022 22:21:40 +0100 [thread overview]
Message-ID: <20220725212140.741644-9-ben.dooks@sifive.com> (raw)
In-Reply-To: <20220725212140.741644-1-ben.dooks@sifive.com>
If we are not in PWM mode, then the output is technically a 50%
output based on a single timer instead of the high-low based on
the two counters. Add a check for the PWM mode in dwc_pwm_get_state()
and if DWC_TIM_CTRL_PWM is not set, then return a 50% cycle.
This may only be an issue on initialisation, as the rest of the
code currently assumes we're always going to have the extended
PWM mode using two counters.
Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
---
drivers/pwm/pwm-dwc.c | 34 +++++++++++++++++++++++-----------
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/pwm/pwm-dwc.c b/drivers/pwm/pwm-dwc.c
index da325133d297..f3723c4d1e59 100644
--- a/drivers/pwm/pwm-dwc.c
+++ b/drivers/pwm/pwm-dwc.c
@@ -171,23 +171,35 @@ static void dwc_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
{
struct dwc_pwm *dwc = to_dwc_pwm(chip);
u64 duty, period;
+ u32 ctrl, ld, ld2;
pm_runtime_get_sync(chip->dev);
- state->enabled = !!(dwc_pwm_readl(dwc,
- DWC_TIM_CTRL(pwm->hwpwm)) & DWC_TIM_CTRL_EN);
+ ctrl = dwc_pwm_readl(dwc, DWC_TIM_CTRL(pwm->hwpwm));
+ ld = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
+ ld2 = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
- duty = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT(pwm->hwpwm));
- duty += 1;
- duty *= dwc->clk_ns;
- state->duty_cycle = duty;
+ state->enabled = !!(ctrl & DWC_TIM_CTRL_EN);
- period = dwc_pwm_readl(dwc, DWC_TIM_LD_CNT2(pwm->hwpwm));
- period += 1;
- period *= dwc->clk_ns;
- period += duty;
- state->period = period;
+ /* If we're not in PWM, technically the output is a 50-50
+ * based on the timer load-count only.
+ */
+ if (ctrl & DWC_TIM_CTRL_PWM) {
+ duty = ld;
+ duty += 1;
+ duty *= dwc->clk_ns;
+
+ period = ld2;
+ period += 1;
+ period *= dwc->clk_ns;
+ period += duty;
+ } else {
+ duty = (ld + 1) * dwc->clk_ns;
+ period = duty * 2;
+ }
+ state->period = period;
+ state->duty_cycle = duty;
state->polarity = PWM_POLARITY_INVERSED;
pm_runtime_put_sync(chip->dev);
--
2.35.1
next prev parent reply other threads:[~2022-07-25 21:22 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-25 21:21 [[PATCH v2] 1/9] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 2/9] dt-bindings: pwm: snps,pwm add pwm number Ben Dooks
2022-07-26 10:08 ` Krzysztof Kozlowski
2022-07-26 10:12 ` Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 3/9] pwm: change &pci->dev to dev in probe Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 4/9] pwm: move dwc memory alloc to own function Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 5/9] pwm: dwc: add of/platform support Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 6/9] pwm: dwc: allow driver to be built with COMPILE_TEST Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 7/9] pwm: dwc: add timer clock Ben Dooks
2022-07-25 21:21 ` [[PATCH v2] 8/9] pwm: dwc: add snps,pwm-number to limit pwm count Ben Dooks
2022-07-25 21:21 ` Ben Dooks [this message]
2022-07-25 21:27 ` [[PATCH v2] 1/9] dt-bindings: pwm: Document Synopsys DesignWare snps,pwm Ben Dooks
2022-07-26 10:05 ` Krzysztof Kozlowski
2022-07-26 10:12 ` Ben Dooks
2022-07-26 11:05 ` Krzysztof Kozlowski
2022-07-27 10:32 ` Ben Dooks
2022-07-27 12:02 ` Krzysztof Kozlowski
2022-07-27 13:21 ` Ben Dooks
2022-07-28 7:57 ` Krzysztof Kozlowski
2022-07-27 10:45 ` Ben Dooks
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