[PATCH v3 0/3] Add PHY interrupt support for ETH{0,1} on RZ/G2L and RZ/V2L SMARC EVK

[PATCH v3 0/3] Add PHY interrupt support for ETH{0,1} on RZ/G2L and RZ/V2L SMARC EVK

[Lad Prabhakar]

Hi All,

This patch series is a subset of [0] as patches 1-4 have been already
picked up by Geert for v5.21. Patch 1 introduces macros for NMI/IRQ0-7,
second patch updates the binding doc and the third patch adds PHY
interrupt support for ETH{0,1}.

v2->v3:
* Added a new file irqc-rzg2l.h to include macros as suggested by
  Biju and Geert.
* Updated binding doc
* Updated rzg2l-smarc-som.dtsi to include the header

v1->v2:
* Fixed review comments pointed by Geert

v1: [0]

[0] https://patchwork.kernel.org/project/linux-renesas-soc/cover/
20220718195651.7711-1-prabhakar.mahadev-lad.rj@bp.renesas.com/

Cheers,
Prabhakar

Lad Prabhakar (3):
  dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7
    interrupts present on RZ/G2L SoC
  dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update
    description for '#interrupt-cells' property
  arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for
    ETH{0/1}

 .../renesas,rzg2l-irqc.yaml                   |  5 ++--
 .../boot/dts/renesas/rzg2l-smarc-som.dtsi     | 11 ++++++--
 .../interrupt-controller/irqc-rzg2l.h         | 25 +++++++++++++++++++
 3 files changed, 37 insertions(+), 4 deletions(-)
 create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h

-- 
2.25.1

[PATCH v3 1/3] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC

[Lad Prabhakar]

Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on
RZ/G2L (and alike) SoC's so that these can be used in the first cell of

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3:
* New patch as suggested by Biju and Geert.
---
 .../interrupt-controller/irqc-rzg2l.h         | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)
 create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h

diff --git a/include/dt-bindings/interrupt-controller/irqc-rzg2l.h b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
new file mode 100644
index 000000000000..34ce778885a1
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/irqc-rzg2l.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * This header provides constants for Renesas RZ/G2L family IRQC bindings.
+ *
+ * Copyright (C) 2022 Renesas Electronics Corp.
+ *
+ */
+
+#ifndef __DT_BINDINGS_IRQC_RZG2L_H
+#define __DT_BINDINGS_IRQC_RZG2L_H
+
+/* NMI maps to SPI0 */
+#define RZG2L_NMI	0
+
+/* IRQ0-7 map to SPI1-8 */
+#define RZG2L_IRQ0	1
+#define RZG2L_IRQ1	2
+#define RZG2L_IRQ2	3
+#define RZG2L_IRQ3	4
+#define RZG2L_IRQ4	5
+#define RZG2L_IRQ5	6
+#define RZG2L_IRQ6	7
+#define RZG2L_IRQ7	8
+
+#endif /* __DT_BINDINGS_IRQC_RZG2L_H */
-- 
2.25.1

Re: [PATCH v3 1/3] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC

[Rob Herring]

On Fri, 22 Jul 2022 16:11:53 +0100, Lad Prabhakar wrote:
> Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on
> RZ/G2L (and alike) SoC's so that these can be used in the first cell of
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * New patch as suggested by Biju and Geert.
> ---
>  .../interrupt-controller/irqc-rzg2l.h         | 25 +++++++++++++++++++
>  1 file changed, 25 insertions(+)
>  create mode 100644 include/dt-bindings/interrupt-controller/irqc-rzg2l.h
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 1/3] dt-bindings: interrupt-controller: Add macros for NMI and IRQ0-7 interrupts present on RZ/G2L SoC

[Geert Uytterhoeven]

On Fri, Jul 22, 2022 at 5:12 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> Add macros for NMI and IRQ0-7 interrupts which map to SPI0-8 present on
> RZ/G2L (and alike) SoC's so that these can be used in the first cell of
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * New patch as suggested by Biju and Geert.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[Lad Prabhakar]

Update description for '#interrupt-cells' property to utilize the
RZG2L_{NMI,IRQX} for the first cell defined in the
include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3:
* New patch
---
 .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml    | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 33b90e975e33..ea7db3618b23 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -31,8 +31,9 @@ properties:
       - const: renesas,rzg2l-irqc
 
   '#interrupt-cells':
-    description: The first cell should contain external interrupt number (IRQ0-7) and the
-                 second cell is used to specify the flag.
+    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
+                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
+                 cell is used to specify the flag.
     const: 2
 
   '#address-cells':
-- 
2.25.1

Re: [PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[Marc Zyngier]

On Fri, 22 Jul 2022 16:11:54 +0100,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> 
> Update description for '#interrupt-cells' property to utilize the
> RZG2L_{NMI,IRQX} for the first cell defined in the
> include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3:
> * New patch
> ---
>  .../bindings/interrupt-controller/renesas,rzg2l-irqc.yaml    | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> index 33b90e975e33..ea7db3618b23 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> @@ -31,8 +31,9 @@ properties:
>        - const: renesas,rzg2l-irqc
>  
>    '#interrupt-cells':
> -    description: The first cell should contain external interrupt number (IRQ0-7) and the
> -                 second cell is used to specify the flag.
> +    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
> +                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
> +                 cell is used to specify the flag.

I think a binding should be self describing, and not rely on an opaque
macro. Mentioning that there is a macro that encodes it is fine, but
the values are what matter, specially when considering that other OSs
could (and should be able to) write their own DTs from scratch without
depending on something that is very much Linux-specific.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[Geert Uytterhoeven]

Hi Marc,

On Sun, Jul 24, 2022 at 1:01 PM Marc Zyngier <maz@kernel.org> wrote:
> On Fri, 22 Jul 2022 16:11:54 +0100,
> Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> >
> > Update description for '#interrupt-cells' property to utilize the
> > RZG2L_{NMI,IRQX} for the first cell defined in the
> > include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v3:
> > * New patch

> > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > @@ -31,8 +31,9 @@ properties:
> >        - const: renesas,rzg2l-irqc
> >
> >    '#interrupt-cells':
> > -    description: The first cell should contain external interrupt number (IRQ0-7) and the
> > -                 second cell is used to specify the flag.
> > +    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
> > +                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
> > +                 cell is used to specify the flag.
>
> I think a binding should be self describing, and not rely on an opaque
> macro. Mentioning that there is a macro that encodes it is fine, but
> the values are what matter, specially when considering that other OSs
> could (and should be able to) write their own DTs from scratch without
> depending on something that is very much Linux-specific.

The macros are not Linux-specific, and are part of the bindings.
But the only hard dependency on <dt-bindings/interrupt-controller/irqc-rzg2l.h>
is the DT source file describing the board.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[Geert Uytterhoeven]

Hi Marc,

On Thu, Aug 11, 2022 at 4:50 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Sun, Jul 24, 2022 at 1:01 PM Marc Zyngier <maz@kernel.org> wrote:
> > On Fri, 22 Jul 2022 16:11:54 +0100,
> > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > >
> > > Update description for '#interrupt-cells' property to utilize the
> > > RZG2L_{NMI,IRQX} for the first cell defined in the
> > > include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v3:
> > > * New patch
>
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > @@ -31,8 +31,9 @@ properties:
> > >        - const: renesas,rzg2l-irqc
> > >
> > >    '#interrupt-cells':
> > > -    description: The first cell should contain external interrupt number (IRQ0-7) and the
> > > -                 second cell is used to specify the flag.
> > > +    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
> > > +                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
> > > +                 cell is used to specify the flag.
> >
> > I think a binding should be self describing, and not rely on an opaque
> > macro. Mentioning that there is a macro that encodes it is fine, but
> > the values are what matter, specially when considering that other OSs
> > could (and should be able to) write their own DTs from scratch without
> > depending on something that is very much Linux-specific.
>
> The macros are not Linux-specific, and are part of the bindings.
> But the only hard dependency on <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> is the DT source file describing the board.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Looks like this fell through the cracks?
The two other patches from this series were applied in v6.1.

Note that the current DT bindings are incorrect, as they do not take into
account that the value of zero is used to represent the NMI.

Fixes: 96fed779d3d4cb3c ("dt-bindings: interrupt-controller: Add
Renesas RZ/G2L Interrupt Controller")

Should we resend instead?
Thanks!

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v3 2/3] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[Marc Zyngier]

On Fri, 08 Sep 2023 10:31:35 +0100,
Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> 
> Hi Marc,
> 
> On Thu, Aug 11, 2022 at 4:50 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Sun, Jul 24, 2022 at 1:01 PM Marc Zyngier <maz@kernel.org> wrote:
> > > On Fri, 22 Jul 2022 16:11:54 +0100,
> > > Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> > > >
> > > > Update description for '#interrupt-cells' property to utilize the
> > > > RZG2L_{NMI,IRQX} for the first cell defined in the
> > > > include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v3:
> > > > * New patch
> >
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
> > > > @@ -31,8 +31,9 @@ properties:
> > > >        - const: renesas,rzg2l-irqc
> > > >
> > > >    '#interrupt-cells':
> > > > -    description: The first cell should contain external interrupt number (IRQ0-7) and the
> > > > -                 second cell is used to specify the flag.
> > > > +    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
> > > > +                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
> > > > +                 cell is used to specify the flag.
> > >
> > > I think a binding should be self describing, and not rely on an opaque
> > > macro. Mentioning that there is a macro that encodes it is fine, but
> > > the values are what matter, specially when considering that other OSs
> > > could (and should be able to) write their own DTs from scratch without
> > > depending on something that is very much Linux-specific.
> >
> > The macros are not Linux-specific, and are part of the bindings.
> > But the only hard dependency on <dt-bindings/interrupt-controller/irqc-rzg2l.h>
> > is the DT source file describing the board.
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> 
> Looks like this fell through the cracks?
> The two other patches from this series were applied in v6.1.
> 
> Note that the current DT bindings are incorrect, as they do not take into
> account that the value of zero is used to represent the NMI.
> 
> Fixes: 96fed779d3d4cb3c ("dt-bindings: interrupt-controller: Add
> Renesas RZ/G2L Interrupt Controller")
> 
> Should we resend instead?

It applied cleanly to v6.6-rc1, so there should be no need.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

[irqchip: irq/irqchip-fixes] dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

[irqchip-bot for Lad Prabhakar]

The following commit has been merged into the irq/irqchip-fixes branch of irqchip:

Commit-ID:     cfa1f9db6d6088118ef311c0927c66072665b47e
Gitweb:        https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/cfa1f9db6d6088118ef311c0927c66072665b47e
Author:        Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
AuthorDate:    Fri, 22 Jul 2022 16:11:54 +01:00
Committer:     Marc Zyngier <maz@kernel.org>
CommitterDate: Tue, 12 Sep 2023 13:40:52 +01:00

dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Update description for '#interrupt-cells' property

Update description for '#interrupt-cells' property to utilize the
RZG2L_{NMI,IRQX} for the first cell defined in the
include/dt-bindings/interrupt-controller/irqc-rzg2l.h file.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Fixes: 96fed779d3d4cb3c ("dt-bindings: interrupt-controller: Add Renesas RZ/G2L Interrupt Controller")
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20220722151155.21100-3-prabhakar.mahadev-lad.rj@bp.renesas.com
---
 Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
index 33b90e9..ea7db36 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,rzg2l-irqc.yaml
@@ -31,8 +31,9 @@ properties:
       - const: renesas,rzg2l-irqc
 
   '#interrupt-cells':
-    description: The first cell should contain external interrupt number (IRQ0-7) and the
-                 second cell is used to specify the flag.
+    description: The first cell should contain a macro RZG2L_{NMI,IRQX} included in the
+                 include/dt-bindings/interrupt-controller/irqc-rzg2l.h and the second
+                 cell is used to specify the flag.
     const: 2
 
   '#address-cells':

[PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

[Lad Prabhakar]

The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
and ETH1 respectively.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
* Included irqc-rzg2l.h header

v1->v2
* Used macros of IRQ numbers
---
 arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
index 9410796c8ad6..c4faff092380 100644
--- a/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg2l-smarc-som.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 
 /* SW1[2] should be at position 2/OFF to enable 64 GB eMMC */
@@ -94,6 +95,8 @@ phy0: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
+		interrupt-parent = <&irqc>;
+		interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
@@ -120,6 +123,8 @@ phy1: ethernet-phy@7 {
 		compatible = "ethernet-phy-id0022.1640",
 			     "ethernet-phy-ieee802.3-c22";
 		reg = <7>;
+		interrupt-parent = <&irqc>;
+		interrupts = <RZG2L_IRQ3 IRQ_TYPE_LEVEL_LOW>;
 		rxc-skew-psec = <2400>;
 		txc-skew-psec = <2400>;
 		rxdv-skew-psec = <0>;
@@ -171,7 +176,8 @@ eth0_pins: eth0 {
 			 <RZG2L_PORT_PINMUX(25, 0, 1)>, /* ET0_RXD0 */
 			 <RZG2L_PORT_PINMUX(25, 1, 1)>, /* ET0_RXD1 */
 			 <RZG2L_PORT_PINMUX(26, 0, 1)>, /* ET0_RXD2 */
-			 <RZG2L_PORT_PINMUX(26, 1, 1)>; /* ET0_RXD3 */
+			 <RZG2L_PORT_PINMUX(26, 1, 1)>, /* ET0_RXD3 */
+			 <RZG2L_PORT_PINMUX(1, 0, 1)>;  /* IRQ2 */
 	};
 
 	eth1_pins: eth1 {
@@ -189,7 +195,8 @@ eth1_pins: eth1 {
 			 <RZG2L_PORT_PINMUX(34, 1, 1)>, /* ET1_RXD0 */
 			 <RZG2L_PORT_PINMUX(35, 0, 1)>, /* ET1_RXD1 */
 			 <RZG2L_PORT_PINMUX(35, 1, 1)>, /* ET1_RXD2 */
-			 <RZG2L_PORT_PINMUX(36, 0, 1)>; /* ET1_RXD3 */
+			 <RZG2L_PORT_PINMUX(36, 0, 1)>, /* ET1_RXD3 */
+			 <RZG2L_PORT_PINMUX(1, 1, 1)>;  /* IRQ3 */
 	};
 
 	gpio-sd0-pwr-en-hog {
-- 
2.25.1

Re: [PATCH v3 3/3] arm64: dts: renesas: rzg2l-smarc-som: Add PHY interrupt support for ETH{0/1}

[Geert Uytterhoeven]

On Fri, Jul 22, 2022 at 5:12 PM Lad Prabhakar
<prabhakar.mahadev-lad.rj@bp.renesas.com> wrote:
> The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ3 for ETH0
> and ETH1 respectively.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v2->v3
> * Included irqc-rzg2l.h header

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.1.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds