From: Sudip Mukherjee <sudip.mukherjee@sifive.com>
To: Serge Semin <fancer.lancer@gmail.com>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: greentime.hu@sifive.com, jude.onyenegecha@sifive.com,
william.salmon@sifive.com, adnan.chowdhury@sifive.com,
ben.dooks@sifive.com, linux-spi@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
jeegar.lakhani@sifive.com,
Sudip Mukherjee <sudip.mukherjee@sifive.com>
Subject: [PATCH 03/11] spi: dw: define spi_frf for dual/quad/octal modes
Date: Tue, 2 Aug 2022 18:57:47 +0100 [thread overview]
Message-ID: <20220802175755.6530-4-sudip.mukherjee@sifive.com> (raw)
In-Reply-To: <20220802175755.6530-1-sudip.mukherjee@sifive.com>
The SPI mode needs to be mentioned in CTRLR0[23:22] register. Define a
configuration variable to keep the mode based on the buswidth, which will
then be used to update CR0. If the transfer is using dual/quad/octal
mode then mark enhanced_spi as true.
Signed-off-by: Sudip Mukherjee <sudip.mukherjee@sifive.com>
---
drivers/spi/spi-dw-core.c | 29 +++++++++++++++++++++++++++++
drivers/spi/spi-dw.h | 7 +++++++
2 files changed, 36 insertions(+)
diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
index 77529e359b6d..8c84a2e991b5 100644
--- a/drivers/spi/spi-dw-core.c
+++ b/drivers/spi/spi-dw-core.c
@@ -333,6 +333,14 @@ void dw_spi_update_config(struct dw_spi *dws, struct spi_device *spi,
/* CTRLR0[11:10] Transfer Mode */
cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_TMOD_MASK, cfg->tmode);
+ if (dws->caps & DW_SPI_CAP_EXT_SPI) {
+ if (cfg->spi_frf)
+ cr0 |= FIELD_PREP(DW_HSSI_CTRLR0_SPI_FRF_MASK,
+ cfg->spi_frf);
+ else
+ cr0 &= ~DW_HSSI_CTRLR0_SPI_FRF_MASK;
+ }
+
dw_writel(dws, DW_SPI_CTRLR0, cr0);
if (cfg->tmode == DW_SPI_CTRLR0_TMOD_EPROMREAD ||
@@ -679,10 +687,31 @@ static void dw_spi_stop_mem_op(struct dw_spi *dws, struct spi_device *spi)
static int dw_spi_exec_mem_op(struct spi_mem *mem, const struct spi_mem_op *op)
{
struct dw_spi *dws = spi_controller_get_devdata(mem->spi->controller);
+ bool enhanced_spi = false;
struct dw_spi_cfg cfg;
unsigned long flags;
int ret;
+ if (dws->caps & DW_SPI_CAP_EXT_SPI) {
+ switch (op->data.buswidth) {
+ case 2:
+ cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI;
+ enhanced_spi = true;
+ break;
+ case 4:
+ cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI;
+ enhanced_spi = true;
+ break;
+ case 8:
+ cfg.spi_frf = DW_SSI_CTRLR0_SPI_FRF_OCT_SPI;
+ enhanced_spi = true;
+ break;
+ default:
+ cfg.spi_frf = 0;
+ break;
+ }
+ }
+
/*
* Collect the outbound data into a single buffer to speed the
* transmission up at least on the initial stage.
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 71d18e9291a3..b8cc20e0deaa 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -96,6 +96,12 @@
#define DW_HSSI_CTRLR0_SRL BIT(13)
#define DW_HSSI_CTRLR0_MST BIT(31)
+/* Bit fields in CTRLR0 for enhanced SPI */
+#define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
+#define DW_SSI_CTRLR0_SPI_FRF_DUAL_SPI 0x1
+#define DW_SSI_CTRLR0_SPI_FRF_QUAD_SPI 0x2
+#define DW_SSI_CTRLR0_SPI_FRF_OCT_SPI 0x3
+
/* Bit fields in CTRLR1 */
#define DW_SPI_NDF_MASK GENMASK(15, 0)
@@ -136,6 +142,7 @@ struct dw_spi_cfg {
u8 dfs;
u32 ndf;
u32 freq;
+ u8 spi_frf;
};
struct dw_spi;
--
2.30.2
next prev parent reply other threads:[~2022-08-02 17:58 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-02 17:57 [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Sudip Mukherjee
2022-08-02 17:57 ` [PATCH 01/11] spi: dw: define capability for enhanced spi Sudip Mukherjee
2022-08-02 18:47 ` Mark Brown
2022-08-03 17:34 ` Sudip Mukherjee
2022-08-03 17:40 ` Mark Brown
2022-08-26 18:16 ` Serge Semin
2022-08-02 17:57 ` [PATCH 02/11] spi: dw: add check for support of dual/quad/octal Sudip Mukherjee
2022-08-26 21:36 ` Serge Semin
2022-08-02 17:57 ` Sudip Mukherjee [this message]
2022-08-26 22:03 ` [PATCH 03/11] spi: dw: define spi_frf for dual/quad/octal modes Serge Semin
2022-08-26 22:22 ` Serge Semin
2022-08-02 17:57 ` [PATCH 04/11] spi: dw: use TMOD_RO to read in enhanced spi modes Sudip Mukherjee
2022-08-02 19:13 ` Mark Brown
2022-08-03 17:35 ` Sudip Mukherjee
2022-08-26 22:12 ` Serge Semin
2022-08-02 17:57 ` [PATCH 05/11] spi: dw: define SPI_CTRLR0 register and its fields Sudip Mukherjee
2022-08-26 22:19 ` Serge Semin
2022-08-02 17:57 ` [PATCH 06/11] spi: dw: update SPI_CTRLR0 register Sudip Mukherjee
2022-08-26 22:50 ` Serge Semin
2022-08-02 17:57 ` [PATCH 07/11] spi: dw: update NDF while writing in enhanced spi mode Sudip Mukherjee
2022-08-26 22:54 ` Serge Semin
2022-08-02 17:57 ` [PATCH 08/11] spi: dw: update buffer for " Sudip Mukherjee
2022-08-26 23:05 ` Serge Semin
2022-08-02 17:57 ` [PATCH 09/11] spi: dw: prepare the transfer routine for enhanced mode Sudip Mukherjee
2022-08-26 23:19 ` Serge Semin
2022-08-02 17:57 ` [PATCH 10/11] spi: dw-apb-ssi: add generic 1.03a version Sudip Mukherjee
2022-08-03 6:35 ` Krzysztof Kozlowski
2022-08-26 23:23 ` Serge Semin
2022-08-26 23:33 ` Serge Semin
2022-08-02 17:57 ` [PATCH 11/11] spi: dw: initialize dwc-ssi-1.03a controller Sudip Mukherjee
2022-08-26 23:31 ` Serge Semin
2022-08-03 18:56 ` [PATCH 00/11] Add support for enhanced SPI for Designware SPI controllers Serge Semin
2022-08-04 9:43 ` Sudip Mukherjee
2022-08-21 20:37 ` Serge Semin
2022-08-26 18:03 ` Serge Semin
2022-08-30 8:48 ` Sudip Mukherjee
2022-09-02 23:03 ` Serge Semin
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