* [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers
@ 2022-08-05 9:09 Ken Chen
2022-08-08 0:30 ` Andrew Jeffery
2022-09-27 7:57 ` Joel Stanley
0 siblings, 2 replies; 3+ messages in thread
From: Ken Chen @ 2022-08-05 9:09 UTC (permalink / raw)
To: Rob Herring, Joel Stanley, Andrew Jeffery
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Potin.Lai, Cosmo.Chou, Michael Garner, Ken Chen
Setup the configuration of UART6, UART7, UART8, and UART9 in
aspeed-g6.dtsi.
Signed-off-by: Ken Chen <j220584470k@gmail.com>
---
arch/arm/boot/dts/aspeed-g6.dtsi | 64 +++++++++++++++++++++++++++++++-
1 file changed, 62 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
index 8c0de3f27883b..fe7cef6b5e976 100644
--- a/arch/arm/boot/dts/aspeed-g6.dtsi
+++ b/arch/arm/boot/dts/aspeed-g6.dtsi
@@ -34,8 +34,12 @@ aliases {
serial2 = &uart3;
serial3 = &uart4;
serial4 = &uart5;
- serial5 = &vuart1;
- serial6 = &vuart2;
+ serial5 = &uart6;
+ serial6 = &uart7;
+ serial7 = &uart8;
+ serial8 = &uart9;
+ serial9 = &vuart1;
+ serial10 = &vuart2;
};
@@ -745,6 +749,62 @@ uart4: serial@1e78f000 {
status = "disabled";
};
+ uart6: serial@1e790000 {
+ compatible = "ns16550a";
+ reg = <0x1e790000 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart6_default>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@1e790100 {
+ compatible = "ns16550a";
+ reg = <0x1e790100 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart7_default>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@1e790200 {
+ compatible = "ns16550a";
+ reg = <0x1e790200 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8_default>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@1e790300 {
+ compatible = "ns16550a";
+ reg = <0x1e790300 0x20>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
+ no-loopback-test;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart9_default>;
+
+ status = "disabled";
+ };
+
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;
--
2.31.1
^ permalink raw reply related [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers
2022-08-05 9:09 [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers Ken Chen
@ 2022-08-08 0:30 ` Andrew Jeffery
2022-09-27 7:57 ` Joel Stanley
1 sibling, 0 replies; 3+ messages in thread
From: Andrew Jeffery @ 2022-08-08 0:30 UTC (permalink / raw)
To: Ken Chen, Rob Herring, Joel Stanley
Cc: devicetree, linux-arm-kernel, linux-aspeed, linux-kernel,
Potin Lai, Cosmo.Chou, Michael Garner
On Fri, 5 Aug 2022, at 18:39, Ken Chen wrote:
> Setup the configuration of UART6, UART7, UART8, and UART9 in
> aspeed-g6.dtsi.
>
> Signed-off-by: Ken Chen <j220584470k@gmail.com>
> ---
> arch/arm/boot/dts/aspeed-g6.dtsi | 64 +++++++++++++++++++++++++++++++-
> 1 file changed, 62 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 8c0de3f27883b..fe7cef6b5e976 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -34,8 +34,12 @@ aliases {
> serial2 = &uart3;
> serial3 = &uart4;
> serial4 = &uart5;
> - serial5 = &vuart1;
> - serial6 = &vuart2;
> + serial5 = &uart6;
> + serial6 = &uart7;
> + serial7 = &uart8;
> + serial8 = &uart9;
> + serial9 = &vuart1;
> + serial10 = &vuart2;
> };
>
Have you tested the AST2600 systems in OpenBMC with this patch to see
if you're not breaking any assumptions made by userspace about serial
numbering, given the aliases exist?
Andrew
^ permalink raw reply [flat|nested] 3+ messages in thread* Re: [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers
2022-08-05 9:09 [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers Ken Chen
2022-08-08 0:30 ` Andrew Jeffery
@ 2022-09-27 7:57 ` Joel Stanley
1 sibling, 0 replies; 3+ messages in thread
From: Joel Stanley @ 2022-09-27 7:57 UTC (permalink / raw)
To: Ken Chen
Cc: Rob Herring, Andrew Jeffery, devicetree, linux-arm-kernel,
linux-aspeed, linux-kernel, Potin.Lai, Cosmo.Chou,
Michael Garner
On Fri, 5 Aug 2022 at 09:13, Ken Chen <j220584470k@gmail.com> wrote:
>
> Setup the configuration of UART6, UART7, UART8, and UART9 in
> aspeed-g6.dtsi.
>
> Signed-off-by: Ken Chen <j220584470k@gmail.com>
> ---
> arch/arm/boot/dts/aspeed-g6.dtsi | 64 +++++++++++++++++++++++++++++++-
> 1 file changed, 62 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
> index 8c0de3f27883b..fe7cef6b5e976 100644
> --- a/arch/arm/boot/dts/aspeed-g6.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g6.dtsi
> @@ -34,8 +34,12 @@ aliases {
> serial2 = &uart3;
> serial3 = &uart4;
> serial4 = &uart5;
> - serial5 = &vuart1;
> - serial6 = &vuart2;
As Andrew mentioned, this may be "ABI" for existing systems. They
expect the vuart to be ttyS5. However, since the beinning they also
have a udev rule that creates a symlink, so it may not be an issue:
bmc:~# ls -la /dev/ttyVUART0
lrwxrwxrwx 1 root root 5 Jun 10 05:25 /dev/ttyVUART0 -> ttyS5
Can you test your patch with an existing userspace to verify?
I have applied the rest of the patch with the aliases part removed.
> + serial5 = &uart6;
> + serial6 = &uart7;
> + serial7 = &uart8;
> + serial8 = &uart9;
> + serial9 = &vuart1;
> + serial10 = &vuart2;
> };
>
>
> @@ -745,6 +749,62 @@ uart4: serial@1e78f000 {
> status = "disabled";
> };
>
> + uart6: serial@1e790000 {
> + compatible = "ns16550a";
> + reg = <0x1e790000 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
> + no-loopback-test;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart6_default>;
> +
> + status = "disabled";
> + };
> +
> + uart7: serial@1e790100 {
> + compatible = "ns16550a";
> + reg = <0x1e790100 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
> + no-loopback-test;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart7_default>;
> +
> + status = "disabled";
> + };
> +
> + uart8: serial@1e790200 {
> + compatible = "ns16550a";
> + reg = <0x1e790200 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
> + no-loopback-test;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart8_default>;
> +
> + status = "disabled";
> + };
> +
> + uart9: serial@1e790300 {
> + compatible = "ns16550a";
> + reg = <0x1e790300 0x20>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
> + no-loopback-test;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart9_default>;
> +
> + status = "disabled";
> + };
> +
> i2c: bus@1e78a000 {
> compatible = "simple-bus";
> #address-cells = <1>;
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
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2022-08-05 9:09 [PATCH 1/1] ARM: dts: aspeed-g6: enable more UART controllers Ken Chen
2022-08-08 0:30 ` Andrew Jeffery
2022-09-27 7:57 ` Joel Stanley
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