* [PATCH v3 00/10] Update UniPhier armv8 devicetree
@ 2022-09-13 4:23 Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 01/10] arm64: dts: uniphier: Rename pvtctl node to thermal-sensor Kunihiko Hayashi
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Update devicetree sources for UniPhier armv8 SoCs to remove dtschema
warnings, add support existing features that haven't yet been
described, and replace constants with macros.
Changes since v2:
- Rename the nodes for usb external controller to "usb-controller"
- Fix the node names for sata
Changes since v1:
- Exclude usb fixed patch (already applied)
- Describe the reason why removing generic pcie compatible
- Add L2 cache node patch
Kunihiko Hayashi (10):
arm64: dts: uniphier: Rename pvtctl node to thermal-sensor
arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
arm64: dts: uniphier: Rename gpio-hog nodes
arm64: dts: uniphier: Use GIC interrupt definitions
arm64: dts: uniphier: Add ahci controller nodes for PXs3
arm64: dts: uniphier: Add USB-device support for PXs3 reference board
arm64: dts: uniphier: Fix opp-table node name for LD20
arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node
arm64: dts: uniphier: Add L2 cache node
arch/arm/boot/dts/uniphier-pinctrl.dtsi | 10 ++
arch/arm64/boot/dts/socionext/Makefile | 4 +-
.../boot/dts/socionext/uniphier-ld11-ref.dts | 6 +-
.../boot/dts/socionext/uniphier-ld11.dtsi | 59 ++++---
.../dts/socionext/uniphier-ld20-akebi96.dts | 6 +-
.../boot/dts/socionext/uniphier-ld20-ref.dts | 6 +-
.../boot/dts/socionext/uniphier-ld20.dtsi | 82 ++++++----
.../socionext/uniphier-pxs3-ref-gadget0.dts | 41 +++++
.../socionext/uniphier-pxs3-ref-gadget1.dts | 40 +++++
.../boot/dts/socionext/uniphier-pxs3-ref.dts | 14 +-
.../boot/dts/socionext/uniphier-pxs3.dtsi | 152 ++++++++++++++----
11 files changed, 316 insertions(+), 104 deletions(-)
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
--
2.25.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 01/10] arm64: dts: uniphier: Rename pvtctl node to thermal-sensor
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 02/10] arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller Kunihiko Hayashi
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
The pvtctl node belongs to thermal-sensor, so the node name should be
renamed to thermal-sensor.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 8f2c1c1e2c64..debab9f0e3e1 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -715,7 +715,7 @@ watchdog {
compatible = "socionext,uniphier-wdt";
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
interrupts = <0 3 4>;
#thermal-sensor-cells = <0>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index ba75adedbf79..e96e7ed98717 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -545,7 +545,7 @@ watchdog {
compatible = "socionext,uniphier-wdt";
};
- pvtctl: pvtctl {
+ pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs3-thermal";
interrupts = <0 3 4>;
#thermal-sensor-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 02/10] arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 01/10] arm64: dts: uniphier: Rename pvtctl node to thermal-sensor Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 03/10] arm64: dts: uniphier: Rename usb-glue node for USB3 " Kunihiko Hayashi
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Actual phy nodes are each child node. The parent node should be
usb-controller node as a representation of the phy integration.
This applies to the devicetree for LD11 SoC.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 15dcfc259854..16d281cae31d 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -530,7 +530,7 @@ pinctrl: pinctrl {
compatible = "socionext,uniphier-ld11-pinctrl";
};
- usb-phy {
+ usb-controller {
compatible = "socionext,uniphier-ld11-usb2-phy";
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 03/10] arm64: dts: uniphier: Rename usb-glue node for USB3 to usb-controller
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 01/10] arm64: dts: uniphier: Rename pvtctl node to thermal-sensor Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 02/10] arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 04/10] arm64: dts: uniphier: Rename gpio-hog nodes Kunihiko Hayashi
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
This "usb-glue" stands for an external controller associated with USB core,
however, this is not common. So rename to "usb-controller".
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index debab9f0e3e1..6466c9213bb7 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -762,7 +762,7 @@ usb: usb@65a00000 {
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-ld20-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index e96e7ed98717..513a2b91dc97 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -611,7 +611,7 @@ usb0: usb@65a00000 {
dr_mode = "host";
};
- usb-glue@65b00000 {
+ usb-controller@65b00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
@@ -713,7 +713,7 @@ usb1: usb@65c00000 {
dr_mode = "host";
};
- usb-glue@65d00000 {
+ usb-controller@65d00000 {
compatible = "socionext,uniphier-pxs3-dwc3-glue",
"simple-mfd";
#address-cells = <1>;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 04/10] arm64: dts: uniphier: Rename gpio-hog nodes
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (2 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 03/10] arm64: dts: uniphier: Rename usb-glue node for USB3 " Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 05/10] arm64: dts: uniphier: Use GIC interrupt definitions Kunihiko Hayashi
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
According to gpio-hog schema, should add the suffix "-hog" to the node
names including gpio-hog to fix the following warning.
uniphier-ld11-ref.dtb: gpio@55000000: 'xirq0' does not match any of the regexes: '^.+-hog(-[0-9+)?$', 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/gpio/socionext,uniphier-gpio.yaml
This applies to the devicetre for LD11, LD20 and PXs3 SoCs.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts | 2 +-
arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts | 4 ++--
arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts | 2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
index 617d2b1e9b1e..41b47f5d2ed7 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
@@ -51,7 +51,7 @@ &serial0 {
};
&gpio {
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
index aa159a11292c..b55b70ded015 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
@@ -168,12 +168,12 @@ &pcie {
&gpio {
/* IRQs for Max3421 */
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 1>;
input;
};
- xirq10 {
+ xirq10-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(10) 1>;
input;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 39ee279a1eb9..8c111588c9a1 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -51,7 +51,7 @@ &serial0 {
};
&gpio {
- xirq0 {
+ xirq0-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(0) 0>;
input;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index 086040306fb3..feb070f934e9 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -68,7 +68,7 @@ &serial3 {
};
&gpio {
- xirq4 {
+ xirq4-hog {
gpio-hog;
gpios = <UNIPHIER_GPIO_IRQ(4) 0>;
input;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 05/10] arm64: dts: uniphier: Use GIC interrupt definitions
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (3 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 04/10] arm64: dts: uniphier: Rename gpio-hog nodes Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 06/10] arm64: dts: uniphier: Add ahci controller nodes for PXs3 Kunihiko Hayashi
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Use human-readable definitions for GIC interrupt type and flag, instead of
hard-coding the numbers. No functional change.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../boot/dts/socionext/uniphier-ld11-ref.dts | 4 +-
.../boot/dts/socionext/uniphier-ld11.dtsi | 51 ++++++++--------
.../dts/socionext/uniphier-ld20-akebi96.dts | 2 +-
.../boot/dts/socionext/uniphier-ld20-ref.dts | 4 +-
.../boot/dts/socionext/uniphier-ld20.dtsi | 60 ++++++++++---------
.../boot/dts/socionext/uniphier-pxs3-ref.dts | 4 +-
.../boot/dts/socionext/uniphier-pxs3.dtsi | 56 ++++++++---------
7 files changed, 93 insertions(+), 88 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
index 41b47f5d2ed7..414aeb99e68f 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11-ref.dts
@@ -39,11 +39,11 @@ memory@80000000 {
};
ðsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 16d281cae31d..525bff79efea 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "socionext,uniphier-ld11";
@@ -102,10 +103,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
reserved-memory {
@@ -131,7 +132,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -144,7 +145,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -155,7 +156,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -166,7 +167,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -177,7 +178,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -188,7 +189,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -223,7 +224,7 @@ gpio: gpio@55000000 {
audio@56000000 {
compatible = "socionext,uniphier-ld11-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
@@ -323,7 +324,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -337,7 +338,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -350,7 +351,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
@@ -362,7 +363,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -376,7 +377,7 @@ i2c4: i2c@58784000 {
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
@@ -389,7 +390,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -440,7 +441,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -460,7 +461,7 @@ usb0: usb@5a800100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a800100 0x100>;
- interrupts = <0 243 4>;
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>,
@@ -476,7 +477,7 @@ usb1: usb@5a810100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a810100 0x100>;
- interrupts = <0 244 4>;
+ interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>,
@@ -492,7 +493,7 @@ usb2: usb@5a820100 {
compatible = "socionext,uniphier-ehci", "generic-ehci";
status = "disabled";
reg = <0x5a820100 0x100>;
- interrupts = <0 245 4>;
+ interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb2>;
clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>,
@@ -573,7 +574,7 @@ efuse@200 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -591,7 +592,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe40000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
@@ -618,7 +619,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld11-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "ether";
clocks = <&sys_clk 6>;
reset-names = "ether";
@@ -640,7 +641,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
index b55b70ded015..fba454adae7d 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-akebi96.dts
@@ -110,7 +110,7 @@ usb-over-spi@0 {
spi-max-frequency = <12500000>;
interrupt-parent = <&gpio>;
interrupt-names = "udc";
- interrupts = <0 2>;
+ interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
};
};
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
index 8c111588c9a1..a5f2083f8b75 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20-ref.dts
@@ -39,11 +39,11 @@ memory@80000000 {
};
ðsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <0 8>;
+ interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
};
&serial0 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 6466c9213bb7..b7896541d7c1 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -176,10 +177,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
@@ -236,7 +237,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -249,7 +250,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -262,7 +263,7 @@ spi2: spi@54006200 {
reg = <0x54006200 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 229 4>;
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi2>;
clocks = <&peri_clk 13>;
@@ -275,7 +276,7 @@ spi3: spi@54006300 {
reg = <0x54006300 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 230 4>;
+ interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi3>;
clocks = <&peri_clk 14>;
@@ -286,7 +287,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -297,7 +298,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -308,7 +309,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -319,7 +320,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -348,7 +349,7 @@ gpio: gpio@55000000 {
audio@56000000 {
compatible = "socionext,uniphier-ld20-aio";
reg = <0x56000000 0x80000>;
- interrupts = <0 144 4>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_aout1>,
<&pinctrl_aoutiec1>;
@@ -448,7 +449,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -462,7 +463,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -475,7 +476,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 6>;
resets = <&peri_rst 6>;
clock-frequency = <400000>;
@@ -487,7 +488,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -501,7 +502,7 @@ i2c4: i2c@58784000 {
reg = <0x58784000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 45 4>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
clocks = <&peri_clk 8>;
@@ -514,7 +515,7 @@ i2c5: i2c@58785000 {
reg = <0x58785000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 25 4>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 9>;
resets = <&peri_rst 9>;
clock-frequency = <400000>;
@@ -570,7 +571,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -590,7 +591,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sd>;
clocks = <&sd_clk 0>;
@@ -675,7 +676,7 @@ usb_hs_i2: trim@5a,0 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -693,7 +694,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
@@ -717,7 +718,7 @@ watchdog {
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-ld20-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
@@ -727,7 +728,7 @@ eth: ethernet@65000000 {
compatible = "socionext,uniphier-ld20-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -749,7 +750,7 @@ usb: usb@65a00000 {
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "host";
- interrupts = <0 134 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb1>,
<&pinctrl_usb2>, <&pinctrl_usb3>;
@@ -915,7 +916,8 @@ pcie: pcie@66000000 {
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
- interrupts = <0 224 4>, <0 225 4>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
@@ -928,7 +930,7 @@ pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 226 4>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -950,7 +952,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index feb070f934e9..506c7b9ff50d 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -40,11 +40,11 @@ memory@80000000 {
};
ðsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&serialsc {
- interrupts = <4 8>;
+ interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
};
&spi0 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index 513a2b91dc97..bd5c1e3b64b0 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/gpio/uniphier-gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -135,10 +136,10 @@ emmc_pwrseq: emmc-pwrseq {
timer {
compatible = "arm,armv8-timer";
- interrupts = <1 13 4>,
- <1 14 4>,
- <1 11 4>,
- <1 10 4>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
};
thermal-zones {
@@ -195,7 +196,7 @@ spi0: spi@54006000 {
reg = <0x54006000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 39 4>;
+ interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0>;
clocks = <&peri_clk 11>;
@@ -208,7 +209,7 @@ spi1: spi@54006100 {
reg = <0x54006100 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 216 4>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1>;
clocks = <&peri_clk 12>;
@@ -219,7 +220,7 @@ serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006800 0x40>;
- interrupts = <0 33 4>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart0>;
clocks = <&peri_clk 0>;
@@ -230,7 +231,7 @@ serial1: serial@54006900 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006900 0x40>;
- interrupts = <0 35 4>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
clocks = <&peri_clk 1>;
@@ -241,7 +242,7 @@ serial2: serial@54006a00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006a00 0x40>;
- interrupts = <0 37 4>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
clocks = <&peri_clk 2>;
@@ -252,7 +253,7 @@ serial3: serial@54006b00 {
compatible = "socionext,uniphier-uart";
status = "disabled";
reg = <0x54006b00 0x40>;
- interrupts = <0 177 4>;
+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
clocks = <&peri_clk 3>;
@@ -284,7 +285,7 @@ i2c0: i2c@58780000 {
reg = <0x58780000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 41 4>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
clocks = <&peri_clk 4>;
@@ -298,7 +299,7 @@ i2c1: i2c@58781000 {
reg = <0x58781000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 42 4>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
clocks = <&peri_clk 5>;
@@ -312,7 +313,7 @@ i2c2: i2c@58782000 {
reg = <0x58782000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 43 4>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
clocks = <&peri_clk 6>;
@@ -326,7 +327,7 @@ i2c3: i2c@58783000 {
reg = <0x58783000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 44 4>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
clocks = <&peri_clk 7>;
@@ -340,7 +341,7 @@ i2c6: i2c@58786000 {
reg = <0x58786000 0x80>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 26 4>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&peri_clk 10>;
resets = <&peri_rst 10>;
clock-frequency = <400000>;
@@ -396,7 +397,7 @@ peri_rst: reset {
emmc: mmc@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
reg = <0x5a000000 0x400>;
- interrupts = <0 78 4>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_emmc>;
clocks = <&sys_clk 4>;
@@ -416,7 +417,7 @@ sd: mmc@5a400000 {
compatible = "socionext,uniphier-sd-v3.1.1";
status = "disabled";
reg = <0x5a400000 0x800>;
- interrupts = <0 76 4>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default", "uhs";
pinctrl-0 = <&pinctrl_sd>;
pinctrl-1 = <&pinctrl_sd_uhs>;
@@ -505,7 +506,7 @@ usb_hs_i2: trim@5a,0 {
xdmac: dma-controller@5fc10000 {
compatible = "socionext,uniphier-xdmac";
reg = <0x5fc10000 0x5300>;
- interrupts = <0 188 4>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
dma-channels = <16>;
#dma-cells = <2>;
};
@@ -523,7 +524,7 @@ gic: interrupt-controller@5fe00000 {
<0x5fe80000 0x80000>; /* GICR */
interrupt-controller;
#interrupt-cells = <3>;
- interrupts = <1 9 4>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
sysctrl@61840000 {
@@ -547,7 +548,7 @@ watchdog {
pvtctl: thermal-sensor {
compatible = "socionext,uniphier-pxs3-thermal";
- interrupts = <0 3 4>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
#thermal-sensor-cells = <0>;
socionext,tmod-calibration = <0x0f22 0x68ee>;
};
@@ -557,7 +558,7 @@ eth0: ethernet@65000000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65000000 0x8500>;
- interrupts = <0 66 4>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether_rgmii>;
clock-names = "ether";
@@ -578,7 +579,7 @@ eth1: ethernet@65200000 {
compatible = "socionext,uniphier-pxs3-ave4";
status = "disabled";
reg = <0x65200000 0x8500>;
- interrupts = <0 67 4>;
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ether1_rgmii>;
clock-names = "ether";
@@ -600,7 +601,7 @@ usb0: usb@65a00000 {
status = "disabled";
reg = <0x65a00000 0xcd00>;
interrupt-names = "dwc_usb3";
- interrupts = <0 134 4>;
+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb0>, <&pinctrl_usb2>;
clock-names = "ref", "bus_early", "suspend";
@@ -702,7 +703,7 @@ usb1: usb@65c00000 {
status = "disabled";
reg = <0x65c00000 0xcd00>;
interrupt-names = "dwc_usb3";
- interrupts = <0 137 4>;
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb1>, <&pinctrl_usb3>;
clock-names = "ref", "bus_early", "suspend";
@@ -812,7 +813,8 @@ pcie: pcie@66000000 {
<0x82000000 0 0x20000000 0x20000000 0 0x0ffe0000>;
#interrupt-cells = <1>;
interrupt-names = "dma", "msi";
- interrupts = <0 224 4>, <0 225 4>;
+ interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie_intc 0>, /* INTA */
<0 0 0 2 &pcie_intc 1>, /* INTB */
@@ -825,7 +827,7 @@ pcie_intc: legacy-interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
- interrupts = <0 226 4>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
};
};
@@ -847,7 +849,7 @@ nand: nand-controller@68000000 {
reg = <0x68000000 0x20>, <0x68100000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <0 65 4>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand>;
clock-names = "nand", "nand_x", "ecc";
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 06/10] arm64: dts: uniphier: Add ahci controller nodes for PXs3
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (4 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 05/10] arm64: dts: uniphier: Use GIC interrupt definitions Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 07/10] arm64: dts: uniphier: Add USB-device support for PXs3 reference board Kunihiko Hayashi
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add ahci core controller and glue layer nodes including reset-controller
and sata-phy.
This supports for PXs3 and the boards.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
.../boot/dts/socionext/uniphier-pxs3-ref.dts | 8 ++
.../boot/dts/socionext/uniphier-pxs3.dtsi | 80 +++++++++++++++++++
2 files changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
index 506c7b9ff50d..1ced6190ab2b 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref.dts
@@ -137,6 +137,14 @@ nand@0 {
};
};
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
+
&pinctrl_ether_rgmii {
tx {
pins = "RGMII0_TXCLK", "RGMII0_TXD0", "RGMII0_TXD1",
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index bd5c1e3b64b0..c93b380fce94 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -596,6 +596,86 @@ mdio1: mdio {
};
};
+ ahci0: sata@65600000 {
+ compatible = "socionext,uniphier-pxs3-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65600000 0x10000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 28>;
+ resets = <&sys_rst 28>, <&ahci0_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci0_phy>;
+ };
+
+ sata-controller@65700000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65700000 0x100>;
+
+ ahci0_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 28>;
+ reset-names = "link";
+ resets = <&sys_rst 28>;
+ #reset-cells = <1>;
+ };
+
+ ahci0_phy: sata-phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 28>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 28>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
+ ahci1: sata@65800000 {
+ compatible = "socionext,uniphier-pxs3-ahci",
+ "generic-ahci";
+ status = "disabled";
+ reg = <0x65800000 0x10000>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&sys_clk 29>;
+ resets = <&sys_rst 29>, <&ahci1_rst 0>;
+ ports-implemented = <1>;
+ phys = <&ahci1_phy>;
+ };
+
+ sata-controller@65900000 {
+ compatible = "socionext,uniphier-pxs3-ahci-glue",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x65900000 0x100>;
+
+ ahci1_rst: reset-controller@0 {
+ compatible = "socionext,uniphier-pxs3-ahci-reset";
+ reg = <0x0 0x4>;
+ clock-names = "link";
+ clocks = <&sys_clk 29>;
+ reset-names = "link";
+ resets = <&sys_rst 29>;
+ #reset-cells = <1>;
+ };
+
+ ahci1_phy: sata-phy@10 {
+ compatible = "socionext,uniphier-pxs3-ahci-phy";
+ reg = <0x10 0x10>;
+ clock-names = "link", "phy";
+ clocks = <&sys_clk 29>, <&sys_clk 30>;
+ reset-names = "link", "phy";
+ resets = <&sys_rst 29>, <&sys_rst 30>;
+ #phy-cells = <0>;
+ };
+ };
+
usb0: usb@65a00000 {
compatible = "socionext,uniphier-dwc3", "snps,dwc3";
status = "disabled";
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 07/10] arm64: dts: uniphier: Add USB-device support for PXs3 reference board
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (5 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 06/10] arm64: dts: uniphier: Add ahci controller nodes for PXs3 Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 08/10] arm64: dts: uniphier: Fix opp-table node name for LD20 Kunihiko Hayashi
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
PXs3 reference board can change each USB port 0 and 1 to device mode
with jumpers. Prepare devicetree sources for USB port 0 and 1.
This specifies dr_mode, pinctrl, and some quirks and removes nodes for
unused phys and vbus-supply properties.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm/boot/dts/uniphier-pinctrl.dtsi | 10 +++++
arch/arm64/boot/dts/socionext/Makefile | 4 +-
.../socionext/uniphier-pxs3-ref-gadget0.dts | 41 +++++++++++++++++++
.../socionext/uniphier-pxs3-ref-gadget1.dts | 40 ++++++++++++++++++
4 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
create mode 100644 arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
diff --git a/arch/arm/boot/dts/uniphier-pinctrl.dtsi b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
index c0fd029b37e5..f909ec2e5333 100644
--- a/arch/arm/boot/dts/uniphier-pinctrl.dtsi
+++ b/arch/arm/boot/dts/uniphier-pinctrl.dtsi
@@ -196,11 +196,21 @@ pinctrl_usb0: usb0 {
function = "usb0";
};
+ pinctrl_usb0_device: usb0-device {
+ groups = "usb0_device";
+ function = "usb0";
+ };
+
pinctrl_usb1: usb1 {
groups = "usb1";
function = "usb1";
};
+ pinctrl_usb1_device: usb1-device {
+ groups = "usb1_device";
+ function = "usb1";
+ };
+
pinctrl_usb2: usb2 {
groups = "usb2";
function = "usb2";
diff --git a/arch/arm64/boot/dts/socionext/Makefile b/arch/arm64/boot/dts/socionext/Makefile
index dda3da33614b..33989a9643ac 100644
--- a/arch/arm64/boot/dts/socionext/Makefile
+++ b/arch/arm64/boot/dts/socionext/Makefile
@@ -5,4 +5,6 @@ dtb-$(CONFIG_ARCH_UNIPHIER) += \
uniphier-ld20-akebi96.dtb \
uniphier-ld20-global.dtb \
uniphier-ld20-ref.dtb \
- uniphier-pxs3-ref.dtb
+ uniphier-pxs3-ref.dtb \
+ uniphier-pxs3-ref-gadget0.dtb \
+ uniphier-pxs3-ref-gadget1.dtb
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
new file mode 100644
index 000000000000..7069f51bc120
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget0.dts
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+//
+// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #0)
+//
+// Copyright (C) 2021 Socionext Inc.
+// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+/dts-v1/;
+#include "uniphier-pxs3-ref.dts"
+
+/ {
+ model = "UniPhier PXs3 Reference Board (USB-Device #0)";
+};
+
+/* I2C3 pinctrl is shared with USB*VBUSIN */
+&i2c3 {
+ status = "disabled";
+};
+
+&usb0 {
+ status = "okay";
+ dr_mode = "peripheral";
+ pinctrl-0 = <&pinctrl_usb0_device>;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2_gadget_lpm_disable;
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usb0_hsphy0>, <&usb0_ssphy0>;
+};
+
+&usb0_hsphy0 {
+ /delete-property/ vbus-supply;
+};
+
+&usb0_ssphy0 {
+ /delete-property/ vbus-supply;
+};
+
+/delete-node/ &usb0_hsphy1;
+/delete-node/ &usb0_ssphy1;
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
new file mode 100644
index 000000000000..a3cfa8113ffb
--- /dev/null
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3-ref-gadget1.dts
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+//
+// Device Tree Source for UniPhier PXs3 Reference Board (for USB-Device #1)
+//
+// Copyright (C) 2021 Socionext Inc.
+// Author: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
+
+/dts-v1/;
+#include "uniphier-pxs3-ref.dts"
+
+/ {
+ model = "UniPhier PXs3 Reference Board (USB-Device #1)";
+};
+
+/* I2C3 pinctrl is shared with USB*VBUSIN */
+&i2c3 {
+ status = "disabled";
+};
+
+&usb1 {
+ status = "okay";
+ dr_mode = "peripheral";
+ pinctrl-0 = <&pinctrl_usb1_device>;
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_u3_susphy_quirk;
+ snps,usb2_gadget_lpm_disable;
+ phy-names = "usb2-phy", "usb3-phy";
+ phys = <&usb1_hsphy0>, <&usb1_ssphy0>;
+};
+
+&usb1_hsphy0 {
+ /delete-property/ vbus-supply;
+};
+
+&usb1_ssphy0 {
+ /delete-property/ vbus-supply;
+};
+
+/delete-node/ &usb1_hsphy1;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 08/10] arm64: dts: uniphier: Fix opp-table node name for LD20
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (6 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 07/10] arm64: dts: uniphier: Add USB-device support for PXs3 reference board Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 09/10] arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 10/10] arm64: dts: uniphier: Add L2 cache node Kunihiko Hayashi
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
To fix dtbs_check warning:
uniphier-ld20-akebi96.dt.yaml: opp-table0: $nodename:0: 'opp-table0' does not match '^opp-table(-[a-z0-9]+)?$'
From schema: Documentation/devicetree/bindings/opp/opp-v2.yaml
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index b7896541d7c1..bb52dcb45777 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -81,7 +81,7 @@ cpu3: cpu@101 {
};
};
- cluster0_opp: opp-table0 {
+ cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
@@ -119,7 +119,7 @@ opp-1100000000 {
};
};
- cluster1_opp: opp-table1 {
+ cluster1_opp: opp-table-1 {
compatible = "operating-points-v2";
opp-shared;
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 09/10] arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (7 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 08/10] arm64: dts: uniphier: Fix opp-table node name for LD20 Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 10/10] arm64: dts: uniphier: Add L2 cache node Kunihiko Hayashi
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
The generic platform driver pcie-designware-plat.c doesn't work for
UniPhier PCIe host controller, because the controller has some
necessary initialization sequence for the controller-specific logic.
Currently the controller doesn't use "snps,dw-pcie" compatible,
so this is no longer needed. Remove the compatible string from the
pcie node.
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 2 +-
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index bb52dcb45777..938753ded7c0 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -896,7 +896,7 @@ usb_ssphy1: ss-phy@310 {
};
pcie: pcie@66000000 {
- compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index c93b380fce94..f10685625b6a 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -873,7 +873,7 @@ usb1_ssphy0: ss-phy@300 {
};
pcie: pcie@66000000 {
- compatible = "socionext,uniphier-pcie", "snps,dw-pcie";
+ compatible = "socionext,uniphier-pcie";
status = "disabled";
reg-names = "dbi", "link", "config";
reg = <0x66000000 0x1000>, <0x66010000 0x10000>,
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v3 10/10] arm64: dts: uniphier: Add L2 cache node
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
` (8 preceding siblings ...)
2022-09-13 4:23 ` [PATCH v3 09/10] arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node Kunihiko Hayashi
@ 2022-09-13 4:23 ` Kunihiko Hayashi
9 siblings, 0 replies; 11+ messages in thread
From: Kunihiko Hayashi @ 2022-09-13 4:23 UTC (permalink / raw)
To: soc, Arnd Bergmann, Olof Johansson
Cc: Rob Herring, Krzysztof Kozlowski, Masami Hiramatsu, devicetree,
linux-arm-kernel, linux-kernel, Kunihiko Hayashi
Add a L2 cache node referenced from CPU nodes as the missing cache hierarchy
information because the following warning was issued.
cacheinfo: Unable to detect cache hierarchy for CPU 0
Early cacheinfo failed, ret = -2
Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi | 6 ++++++
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi | 12 ++++++++++++
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 8 ++++++++
3 files changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
index 525bff79efea..1c76b4375b2e 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
@@ -36,6 +36,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -45,8 +46,13 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
};
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
};
cluster0_opp: opp-table {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
index 938753ded7c0..9308458f9611 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
@@ -46,6 +46,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
+ next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -56,6 +57,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
+ next-level-cache = <&a72_l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -66,6 +68,7 @@ cpu2: cpu@100 {
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
@@ -76,9 +79,18 @@ cpu3: cpu@101 {
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&a53_l2>;
operating-points-v2 = <&cluster1_opp>;
#cooling-cells = <2>;
};
+
+ a72_l2: l2-cache0 {
+ compatible = "cache";
+ };
+
+ a53_l2: l2-cache1 {
+ compatible = "cache";
+ };
};
cluster0_opp: opp-table-0 {
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index f10685625b6a..b0c29510a7da 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -43,6 +43,7 @@ cpu0: cpu@0 {
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -53,6 +54,7 @@ cpu1: cpu@1 {
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -63,6 +65,7 @@ cpu2: cpu@2 {
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
@@ -73,9 +76,14 @@ cpu3: cpu@3 {
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
+ next-level-cache = <&l2>;
operating-points-v2 = <&cluster0_opp>;
#cooling-cells = <2>;
};
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
};
cluster0_opp: opp-table {
--
2.25.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
end of thread, other threads:[~2022-09-13 4:29 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-13 4:23 [PATCH v3 00/10] Update UniPhier armv8 devicetree Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 01/10] arm64: dts: uniphier: Rename pvtctl node to thermal-sensor Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 02/10] arm64: dts: uniphier: Rename usb-phy node for USB2 to usb-controller Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 03/10] arm64: dts: uniphier: Rename usb-glue node for USB3 " Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 04/10] arm64: dts: uniphier: Rename gpio-hog nodes Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 05/10] arm64: dts: uniphier: Use GIC interrupt definitions Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 06/10] arm64: dts: uniphier: Add ahci controller nodes for PXs3 Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 07/10] arm64: dts: uniphier: Add USB-device support for PXs3 reference board Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 08/10] arm64: dts: uniphier: Fix opp-table node name for LD20 Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 09/10] arm64: dts: uniphier: Remove compatible "snps,dw-pcie" from pcie node Kunihiko Hayashi
2022-09-13 4:23 ` [PATCH v3 10/10] arm64: dts: uniphier: Add L2 cache node Kunihiko Hayashi
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