From: Xin Li <xin3.li@intel.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org,
brgerst@gmail.com, chang.seok.bae@intel.com
Subject: [PATCH v3 1/6] x86/cpufeature: add cpu feature bit for LKGS
Date: Thu, 13 Oct 2022 13:01:29 -0700 [thread overview]
Message-ID: <20221013200134.1487-2-xin3.li@intel.com> (raw)
In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com>
From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
Add the CPU feature bit for LKGS (Load "Kernel" GS).
LKGS instruction is introduced with Intel FRED (flexible return and
event delivery) specificaton
https://cdrdv2.intel.com/v1/dl/getContent/678938.
LKGS behaves like the MOV to GS instruction except that it loads
the base address into the IA32_KERNEL_GS_BASE MSR instead of the
GS segment’s descriptor cache, which is exactly what Linux kernel
does to load a user level GS base. Thus, with LKGS, there is no
need to SWAPGS away from the kernel GS base.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Chang S. Bae <chang.seok.bae@intel.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
Link: https://lkml.org/lkml/2022/10/11/1139
---
arch/x86/include/asm/cpufeatures.h | 1 +
tools/arch/x86/include/asm/cpufeatures.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index b71f4f2ecdd5..3dc1a48c2796 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index ef4775c6db01..9d45071d1730 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -308,6 +308,7 @@
/* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
#define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */
#define X86_FEATURE_AVX512_BF16 (12*32+ 5) /* AVX512 BFLOAT16 instructions */
+#define X86_FEATURE_LKGS (12*32+ 18) /* "" Load "kernel" (userspace) gs */
/* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
#define X86_FEATURE_CLZERO (13*32+ 0) /* CLZERO instruction */
--
2.34.1
next prev parent reply other threads:[~2022-10-13 20:23 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 20:01 [PATCH v3 0/6] Enable LKGS instruction Xin Li
2022-10-13 20:01 ` Xin Li [this message]
2022-10-13 20:01 ` [PATCH v3 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Xin Li
2022-10-13 20:01 ` [PATCH v3 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Xin Li
2022-10-14 12:28 ` David Laight
2022-10-15 0:13 ` Li, Xin3
2022-10-15 2:41 ` H. Peter Anvin
2022-10-17 7:49 ` David Laight
2022-10-17 18:39 ` H. Peter Anvin
2022-10-13 20:01 ` [PATCH v3 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Xin Li
2022-10-15 8:51 ` Thomas Gleixner
2022-10-18 17:25 ` Li, Xin3
2022-10-18 18:13 ` H. Peter Anvin
2022-10-18 21:29 ` Li, Xin3
2022-10-13 20:01 ` [PATCH v3 5/6] x86/gsseg: move load_gs_index() to its own header file Xin Li
2022-10-13 20:01 ` [PATCH v3 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index() Xin Li
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