From: Xin Li <xin3.li@intel.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org
Cc: tglx@linutronix.de, mingo@redhat.com, bp@alien8.de,
dave.hansen@linux.intel.com, hpa@zytor.com, peterz@infradead.org,
brgerst@gmail.com, chang.seok.bae@intel.com
Subject: [PATCH v3 6/6] x86/gsseg: use the LKGS instruction if available for load_gs_index()
Date: Thu, 13 Oct 2022 13:01:34 -0700 [thread overview]
Message-ID: <20221013200134.1487-7-xin3.li@intel.com> (raw)
In-Reply-To: <20221013200134.1487-1-xin3.li@intel.com>
From: "H. Peter Anvin (Intel)" <hpa@zytor.com>
The LKGS instruction atomically loads a segment descriptor into the
%gs descriptor registers, *except* that %gs.base is unchanged, and the
base is instead loaded into MSR_IA32_KERNEL_GS_BASE, which is exactly
what we want this function to do.
Signed-off-by: H. Peter Anvin (Intel) <hpa@zytor.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Brian Gerst <brgerst@gmail.com>
Signed-off-by: Xin Li <xin3.li@intel.com>
link: https://lkml.org/lkml/2022/10/7/352
link: https://lkml.org/lkml/2022/10/7/373
link: https://lkml.org/lkml/2022/10/10/1286
---
arch/x86/include/asm/gsseg.h | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/arch/x86/include/asm/gsseg.h b/arch/x86/include/asm/gsseg.h
index 5e3b56a17098..7463ac65ef56 100644
--- a/arch/x86/include/asm/gsseg.h
+++ b/arch/x86/include/asm/gsseg.h
@@ -3,15 +3,39 @@
#define _ASM_X86_GSSEG_H
#include <linux/types.h>
+
+#include <asm/asm.h>
+#include <asm/cpufeature.h>
+#include <asm/alternative.h>
#include <asm/processor.h>
+#include <asm/nops.h>
#ifdef CONFIG_X86_64
extern asmlinkage void asm_load_gs_index(u16 selector);
+/* Replace with "lkgs %di" once binutils support LKGS instruction */
+#define LKGS_DI _ASM_BYTES(0xf2,0x0f,0x00,0xf7)
+
static inline void native_load_gs_index(unsigned int selector)
{
- asm_load_gs_index(selector);
+ u16 sel = selector;
+
+ /*
+ * Note: the fixup is used for the LKGS instruction, but
+ * it needs to be attached to the primary instruction sequence
+ * as it isn't something that gets patched.
+ *
+ * %rax is provided to the assembly routine as a scratch
+ * register.
+ */
+ asm_inline volatile("1:\n"
+ ALTERNATIVE("call asm_load_gs_index\n",
+ _ASM_BYTES(0x3e) LKGS_DI,
+ X86_FEATURE_LKGS)
+ _ASM_EXTABLE_TYPE_REG(1b, 1b, EX_TYPE_ZERO_REG, %k[sel])
+ : ASM_OUTPUT2([sel] "+D" (sel), ASM_CALL_CONSTRAINT)
+ : : _ASM_AX);
}
#endif /* CONFIG_X86_64 */
--
2.34.1
prev parent reply other threads:[~2022-10-13 20:24 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-13 20:01 [PATCH v3 0/6] Enable LKGS instruction Xin Li
2022-10-13 20:01 ` [PATCH v3 1/6] x86/cpufeature: add cpu feature bit for LKGS Xin Li
2022-10-13 20:01 ` [PATCH v3 2/6] x86/opcode: add LKGS instruction to x86-opcode-map Xin Li
2022-10-13 20:01 ` [PATCH v3 3/6] x86/gsseg: make asm_load_gs_index() take an u16 Xin Li
2022-10-14 12:28 ` David Laight
2022-10-15 0:13 ` Li, Xin3
2022-10-15 2:41 ` H. Peter Anvin
2022-10-17 7:49 ` David Laight
2022-10-17 18:39 ` H. Peter Anvin
2022-10-13 20:01 ` [PATCH v3 4/6] x86/gsseg: move local_irq_save/restore() into asm_load_gs_index() Xin Li
2022-10-15 8:51 ` Thomas Gleixner
2022-10-18 17:25 ` Li, Xin3
2022-10-18 18:13 ` H. Peter Anvin
2022-10-18 21:29 ` Li, Xin3
2022-10-13 20:01 ` [PATCH v3 5/6] x86/gsseg: move load_gs_index() to its own header file Xin Li
2022-10-13 20:01 ` Xin Li [this message]
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