From: Bjorn Andersson <quic_bjorande@quicinc.com>
To: Georgi Djakov <djakov@kernel.org>, Sibi Sankar <quic_sibis@quicinc.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@somainline.org>,
"Rob Herring" <robh+dt@kernel.org>,
Mike Tipton <quic_mdtipton@quicinc.com>,
"Johan Hovold" <johan+linaro@kernel.org>,
<linux-arm-msm@vger.kernel.org>, <linux-pm@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: [PATCH v2 03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support
Date: Thu, 10 Nov 2022 19:25:08 -0800 [thread overview]
Message-ID: <20221111032515.3460-4-quic_bjorande@quicinc.com> (raw)
In-Reply-To: <20221111032515.3460-1-quic_bjorande@quicinc.com>
The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting
enabled. In this configuration, the "shared" vote is done using the
REG_L3_VOTE register instead of PERF_STATE.
Rename epss_l3 to clarify that it's affecting the PERF_STATE register
and add a new L3_VOTE description. Given platform lineage it's assumed
that the L3_VOTE-based case will be the predominant one, so use this for
a new generic qcom,epss-l3 compatible.
While adding the EPSS generic, also add qcom,osm-l3.
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
---
Changes since v1:
- None
drivers/interconnect/qcom/osm-l3.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index 7d6844253241..469be732a00b 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -34,6 +34,7 @@
/* EPSS Register offsets */
#define EPSS_LUT_ROW_SIZE 4
+#define EPSS_REG_L3_VOTE 0x90
#define EPSS_REG_FREQ_LUT 0x100
#define EPSS_REG_PERF_STATE 0x320
@@ -112,7 +113,7 @@ static const struct qcom_osm_l3_desc osm_l3 = {
.reg_perf_state = OSM_REG_PERF_STATE,
};
-static const struct qcom_osm_l3_desc epss_l3 = {
+static const struct qcom_osm_l3_desc epss_l3_perf_state = {
.nodes = epss_l3_nodes,
.num_nodes = ARRAY_SIZE(epss_l3_nodes),
.lut_row_size = EPSS_LUT_ROW_SIZE,
@@ -120,6 +121,14 @@ static const struct qcom_osm_l3_desc epss_l3 = {
.reg_perf_state = EPSS_REG_PERF_STATE,
};
+static const struct qcom_osm_l3_desc epss_l3_l3_vote = {
+ .nodes = epss_l3_nodes,
+ .num_nodes = ARRAY_SIZE(epss_l3_nodes),
+ .lut_row_size = EPSS_LUT_ROW_SIZE,
+ .reg_freq_lut = EPSS_REG_FREQ_LUT,
+ .reg_perf_state = EPSS_REG_L3_VOTE,
+};
+
static int qcom_osm_l3_set(struct icc_node *src, struct icc_node *dst)
{
struct qcom_osm_l3_icc_provider *qp;
@@ -285,12 +294,14 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
}
static const struct of_device_id osm_l3_of_match[] = {
+ { .compatible = "qcom,epss-l3", .data = &epss_l3_l3_vote },
+ { .compatible = "qcom,osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc7180-osm-l3", .data = &osm_l3 },
- { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3 },
+ { .compatible = "qcom,sc7280-epss-l3", .data = &epss_l3_perf_state },
{ .compatible = "qcom,sdm845-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &osm_l3 },
{ .compatible = "qcom,sc8180x-osm-l3", .data = &osm_l3 },
- { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3 },
+ { .compatible = "qcom,sm8250-epss-l3", .data = &epss_l3_perf_state },
{ }
};
MODULE_DEVICE_TABLE(of, osm_l3_of_match);
--
2.17.1
next prev parent reply other threads:[~2022-11-11 3:25 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-11 3:25 [PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling Bjorn Andersson
2022-11-11 3:25 ` [PATCH v2 01/10] interconnect: qcom: osm-l3: Use platform-independent node ids Bjorn Andersson
2022-11-11 10:23 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 02/10] interconnect: qcom: osm-l3: Squash common descriptors Bjorn Andersson
2022-11-11 10:24 ` Sibi Sankar
2022-11-11 3:25 ` Bjorn Andersson [this message]
2022-11-11 10:24 ` [PATCH v2 03/10] interconnect: qcom: osm-l3: Add per-core EPSS L3 support Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 04/10] interconnect: qcom: osm-l3: Simplify osm_l3_set() Bjorn Andersson
2022-11-11 10:26 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 05/10] dt-bindings: interconnect: Add sm8350, sc8280xp and generic OSM L3 compatibles Bjorn Andersson
2022-11-11 8:36 ` Krzysztof Kozlowski
2022-11-11 10:32 ` Sibi Sankar
2022-11-11 18:08 ` Bjorn Andersson
2022-11-16 6:56 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 06/10] arm64: dts: qcom: Align with generic osm-l3/epss-l3 Bjorn Andersson
2022-11-11 10:44 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 07/10] arm64: dts: qcom: sc8280xp: Add epss_l3 node Bjorn Andersson
2022-11-11 10:33 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 08/10] arm64: dts: qcom: sc8280xp: Set up L3 scaling Bjorn Andersson
2022-11-16 11:01 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 09/10] dt-bindings: interconnect: qcom,msm8998-bwmon: Add sc8280xp bwmon instances Bjorn Andersson
2022-11-11 8:35 ` Krzysztof Kozlowski
2022-11-11 10:53 ` Sibi Sankar
2022-11-11 3:25 ` [PATCH v2 10/10] arm64: dts: qcom: sc8280xp: Add " Bjorn Andersson
2022-11-11 11:03 ` Sibi Sankar
2022-11-17 16:25 ` [PATCH v2 00/10] interconnect: osm-l3: SC8280XP L3 and DDR scaling Georgi Djakov
2022-12-06 18:19 ` (subset) " Bjorn Andersson
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