[PATCH v2 1/5] drm/msm/a6xx: Add support for A640 speed binning

[PATCH v2 1/5] drm/msm/a6xx: Add support for A640 speed binning

[Konrad Dybcio]

Add support for matching QFPROM fuse values to get the correct speed bin
on A640 (SM8150) GPUs.

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index aae60cbd9164..0ee8cb3e490c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1884,6 +1884,16 @@ static u32 a619_get_speed_bin(u32 fuse)
 	return UINT_MAX;
 }
 
+static u32 a640_get_speed_bin(u32 fuse)
+{
+	if (fuse == 0)
+		return 0;
+	else if (fuse == 1)
+		return 1;
+
+	return UINT_MAX;
+}
+
 static u32 adreno_7c3_get_speed_bin(u32 fuse)
 {
 	if (fuse == 0)
@@ -1909,6 +1919,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 	if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
 		val = adreno_7c3_get_speed_bin(fuse);
 
+	if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
+		val = a640_get_speed_bin(fuse);
+
 	if (val == UINT_MAX) {
 		DRM_DEV_ERROR(dev,
 			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
-- 
2.39.1

[PATCH v2 2/5] drm/msm/a6xx: Add support for A650 speed binning

[Konrad Dybcio]

Add support for matching QFPROM fuse values to get the correct speed bin
on A650 (SM8250) GPUs.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 0ee8cb3e490c..c5f5d0bb3fdc 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse)
 	return UINT_MAX;
 }
 
+static u32 a650_get_speed_bin(u32 fuse)
+{
+	if (fuse == 0)
+		return 0;
+	else if (fuse == 1)
+		return 1;
+	else if (fuse == 2)
+		return 2;
+	else if (fuse == 3)
+		return 3;
+
+	return UINT_MAX;
+}
+
 static u32 adreno_7c3_get_speed_bin(u32 fuse)
 {
 	if (fuse == 0)
@@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
 	if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
 		val = a640_get_speed_bin(fuse);
 
+	if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
+		val = a650_get_speed_bin(fuse);
+
 	if (val == UINT_MAX) {
 		DRM_DEV_ERROR(dev,
 			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
-- 
2.39.1

[PATCH v2 3/5] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode

[Konrad Dybcio]

Now that there's display support, there is no reason to assume the default
mode for Adreno should be headless. Keep it like that for boards that
previously enabled it, so as not to create regressions though.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8150-hdk.dts |  5 +++++
 arch/arm64/boot/dts/qcom/sm8150-mtp.dts |  5 +++++
 arch/arm64/boot/dts/qcom/sm8150.dtsi    | 10 +---------
 3 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
index 3331ee957d64..0ee5309408b9 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-hdk.dts
@@ -359,6 +359,11 @@ &gmu {
 };
 
 &gpu {
+	/*
+	 * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
+	 * after display support is added on this board.
+	 */
+	compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
index 46b5cf9a1192..9dfecbf89b21 100644
--- a/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
+++ b/arch/arm64/boot/dts/qcom/sm8150-mtp.dts
@@ -354,6 +354,11 @@ &gmu {
 };
 
 &gpu {
+	/*
+	 * NOTE: "amd,imageon" makes Adreno start in headless mode, remove it
+	 * after display support is added on this board.
+	 */
+	compatible = "qcom,adreno-640.1", "qcom,adreno", "amd,imageon";
 	status = "okay";
 };
 
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index fd20096cfc6e..e3059f9b98de 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -2133,15 +2133,7 @@ compute-cb@3 {
 		};
 
 		gpu: gpu@2c00000 {
-			/*
-			 * note: the amd,imageon compatible makes it possible
-			 * to use the drm/msm driver without the display node,
-			 * make sure to remove it when display node is added
-			 */
-			compatible = "qcom,adreno-640.1",
-				     "qcom,adreno",
-				     "amd,imageon";
-
+			compatible = "qcom,adreno-640.1", "qcom,adreno";
 			reg = <0 0x02c00000 0 0x40000>;
 			reg-names = "kgsl_3d0_reg_memory";
 
-- 
2.39.1

[PATCH v2 4/5] arm64: dts: qcom: sm8150: Add GPU speedbin support

[Konrad Dybcio]

SM8150 has (at least) two GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 (speed bin 0x3)
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 ++++++++++++++++++++-
 1 file changed, 20 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index e3059f9b98de..1c7ee0cd816d 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -945,6 +945,17 @@ ethernet: ethernet@20000 {
 			status = "disabled";
 		};
 
+		qfprom: efuse@784000 {
+			compatible = "qcom,sm8150-qfprom", "qcom,qfprom";
+			reg = <0 0x00784000 0 0x8ff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpu_speed_bin: gpu_speed_bin@133 {
+				reg = <0x133 0x1>;
+				bits = <5 3>;
+			};
+		};
 
 		qupv3_id_0: geniqup@8c0000 {
 			compatible = "qcom,geni-se-qup";
@@ -2145,44 +2156,52 @@ gpu: gpu@2c00000 {
 
 			qcom,gmu = <&gmu>;
 
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
 			status = "disabled";
 
 			zap-shader {
 				memory-region = <&gpu_mem>;
 			};
 
-			/* note: downstream checks gpu binning for 675 Mhz */
 			gpu_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-675000000 {
 					opp-hz = /bits/ 64 <675000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-supported-hw = <0x2>;
 				};
 
 				opp-585000000 {
 					opp-hz = /bits/ 64 <585000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x3>;
 				};
 
 				opp-499200000 {
 					opp-hz = /bits/ 64 <499200000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-supported-hw = <0x3>;
 				};
 
 				opp-427000000 {
 					opp-hz = /bits/ 64 <427000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0x3>;
 				};
 
 				opp-345000000 {
 					opp-hz = /bits/ 64 <345000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0x3>;
 				};
 
 				opp-257000000 {
 					opp-hz = /bits/ 64 <257000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0x3>;
 				};
 			};
 		};
-- 
2.39.1

[PATCH v2 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support

[Konrad Dybcio]

SM8250 has (at least) four GPU speed bins. With the support added on the
driver side, wire up bin detection in the DTS to restrict lower-quality
SKUs from running at frequencies they were not validated at.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7)
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 059c83003fb6..95f1a6afcd43 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -981,6 +981,18 @@ ipcc: mailbox@408000 {
 			#mbox-cells = <2>;
 		};
 
+		qfprom: efuse@784000 {
+			compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
+			reg = <0 0x00784000 0 0x8ff>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpu_speed_bin: gpu_speed_bin@19b {
+				reg = <0x19b 0x1>;
+				bits = <5 3>;
+			};
+		};
+
 		rng: rng@793000 {
 			compatible = "qcom,prng-ee";
 			reg = <0 0x00793000 0 0x1000>;
@@ -2576,49 +2588,58 @@ gpu: gpu@3d00000 {
 
 			qcom,gmu = <&gmu>;
 
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
 			status = "disabled";
 
 			zap-shader {
 				memory-region = <&gpu_mem>;
 			};
 
-			/* note: downstream checks gpu binning for 670 Mhz */
 			gpu_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
 				opp-670000000 {
 					opp-hz = /bits/ 64 <670000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+					opp-supported-hw = <0x6>;
 				};
 
 				opp-587000000 {
 					opp-hz = /bits/ 64 <587000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+					opp-supported-hw = <0x7>;
 				};
 
 				opp-525000000 {
 					opp-hz = /bits/ 64 <525000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
+					opp-supported-hw = <0xf>;
 				};
 
 				opp-490000000 {
 					opp-hz = /bits/ 64 <490000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+					opp-supported-hw = <0xf>;
 				};
 
 				opp-441600000 {
 					opp-hz = /bits/ 64 <441600000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
+					opp-supported-hw = <0xf>;
 				};
 
 				opp-400000000 {
 					opp-hz = /bits/ 64 <400000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+					opp-supported-hw = <0xf>;
 				};
 
 				opp-305000000 {
 					opp-hz = /bits/ 64 <305000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+					opp-supported-hw = <0xf>;
 				};
 			};
 		};
-- 
2.39.1

Re: [PATCH v2 2/5] drm/msm/a6xx: Add support for A650 speed binning

[Dmitry Baryshkov]

On 20/01/2023 19:22, Konrad Dybcio wrote:
> Add support for matching QFPROM fuse values to get the correct speed bin
> on A650 (SM8250) GPUs.
> 
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Thank you for the patch. It took me a while to dive into various ways 
vendor kernels handle GPU speed bins.

> ---
>   drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 17 +++++++++++++++++
>   1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> index 0ee8cb3e490c..c5f5d0bb3fdc 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
> @@ -1894,6 +1894,20 @@ static u32 a640_get_speed_bin(u32 fuse)
>   	return UINT_MAX;
>   }
>   
> +static u32 a650_get_speed_bin(u32 fuse)
> +{
> +	if (fuse == 0)
> +		return 0;
> +	else if (fuse == 1)
> +		return 1;
> +	else if (fuse == 2)
> +		return 2;
> +	else if (fuse == 3)
> +		return 3;
> +
> +	return UINT_MAX;
> +}
> +
>   static u32 adreno_7c3_get_speed_bin(u32 fuse)
>   {
>   	if (fuse == 0)
> @@ -1922,6 +1936,9 @@ static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
>   	if (adreno_cmp_rev(ADRENO_REV(6, 4, 0, ANY_ID), rev))
>   		val = a640_get_speed_bin(fuse);
>   
> +	if (adreno_cmp_rev(ADRENO_REV(6, 5, 0, ANY_ID), rev))
> +		val = a650_get_speed_bin(fuse);
> +
>   	if (val == UINT_MAX) {
>   		DRM_DEV_ERROR(dev,
>   			"missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",

-- 
With best wishes
Dmitry

Re: [PATCH v2 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support

[Dmitry Baryshkov]

On 20/01/2023 19:22, Konrad Dybcio wrote:
> SM8250 has (at least) four GPU speed bins. With the support added on the
> driver side, wire up bin detection in the DTS to restrict lower-quality
> SKUs from running at frequencies they were not validated at.
> 
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7)
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++-
>   1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> index 059c83003fb6..95f1a6afcd43 100644
> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
> @@ -981,6 +981,18 @@ ipcc: mailbox@408000 {
>   			#mbox-cells = <2>;
>   		};
>   
> +		qfprom: efuse@784000 {
> +			compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
> +			reg = <0 0x00784000 0 0x8ff>;
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +
> +			gpu_speed_bin: gpu_speed_bin@19b {
> +				reg = <0x19b 0x1>;
> +				bits = <5 3>;
> +			};
> +		};
> +
>   		rng: rng@793000 {
>   			compatible = "qcom,prng-ee";
>   			reg = <0 0x00793000 0 0x1000>;
> @@ -2576,49 +2588,58 @@ gpu: gpu@3d00000 {
>   
>   			qcom,gmu = <&gmu>;
>   
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";
> +
>   			status = "disabled";
>   
>   			zap-shader {
>   				memory-region = <&gpu_mem>;
>   			};
>   
> -			/* note: downstream checks gpu binning for 670 Mhz */
>   			gpu_opp_table: opp-table {
>   				compatible = "operating-points-v2";
>   
>   				opp-670000000 {
>   					opp-hz = /bits/ 64 <670000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
> +					opp-supported-hw = <0x6>;

opp-supported-hw = <0xa>; /* 3 & 1 */

>   				};
>   
>   				opp-587000000 {
>   					opp-hz = /bits/ 64 <587000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> +					opp-supported-hw = <0x7>;

opp-supported-hw = <0xb>; /* 3, 1, 0 */


>   				};
>   
>   				opp-525000000 {
>   					opp-hz = /bits/ 64 <525000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
> +					opp-supported-hw = <0xf>;
>   				};
>   
>   				opp-490000000 {
>   					opp-hz = /bits/ 64 <490000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> +					opp-supported-hw = <0xf>;
>   				};
>   
>   				opp-441600000 {
>   					opp-hz = /bits/ 64 <441600000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
> +					opp-supported-hw = <0xf>;
>   				};
>   
>   				opp-400000000 {
>   					opp-hz = /bits/ 64 <400000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
> +					opp-supported-hw = <0xf>;
>   				};
>   
>   				opp-305000000 {
>   					opp-hz = /bits/ 64 <305000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
> +					opp-supported-hw = <0xf>;
>   				};
>   			};
>   		};

-- 
With best wishes
Dmitry

Re: [PATCH v2 4/5] arm64: dts: qcom: sm8150: Add GPU speedbin support

[Dmitry Baryshkov]

On 20/01/2023 19:22, Konrad Dybcio wrote:
> SM8150 has (at least) two GPU speed bins. With the support added on the
> driver side, wire up bin detection in the DTS to restrict lower-quality
> SKUs from running at frequencies they were not validated at.
> 
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 (speed bin 0x3)
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8150.dtsi | 21 ++++++++++++++++++++-
>   1 file changed, 20 insertions(+), 1 deletion(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH v2 3/5] arm64: dts: qcom: sm8150: Don't start Adreno in headless mode

[Dmitry Baryshkov]

On 20/01/2023 19:22, Konrad Dybcio wrote:
> Now that there's display support, there is no reason to assume the default
> mode for Adreno should be headless. Keep it like that for boards that
> previously enabled it, so as not to create regressions though.
> 
> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
>   arch/arm64/boot/dts/qcom/sm8150-hdk.dts |  5 +++++
>   arch/arm64/boot/dts/qcom/sm8150-mtp.dts |  5 +++++
>   arch/arm64/boot/dts/qcom/sm8150.dtsi    | 10 +---------
>   3 files changed, 11 insertions(+), 9 deletions(-)

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

-- 
With best wishes
Dmitry

Re: [PATCH v2 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support

[Konrad Dybcio]

On 31.03.2023 02:43, Dmitry Baryshkov wrote:
> On 20/01/2023 19:22, Konrad Dybcio wrote:
>> SM8250 has (at least) four GPU speed bins. With the support added on the
>> driver side, wire up bin detection in the DTS to restrict lower-quality
>> SKUs from running at frequencies they were not validated at.
>>
>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony Xperia 5 II (speed bin 0x7)
>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++-
>>   1 file changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index 059c83003fb6..95f1a6afcd43 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -981,6 +981,18 @@ ipcc: mailbox@408000 {
>>               #mbox-cells = <2>;
>>           };
>>   +        qfprom: efuse@784000 {
>> +            compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
>> +            reg = <0 0x00784000 0 0x8ff>;
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            gpu_speed_bin: gpu_speed_bin@19b {
>> +                reg = <0x19b 0x1>;
>> +                bits = <5 3>;
>> +            };
>> +        };
>> +
>>           rng: rng@793000 {
>>               compatible = "qcom,prng-ee";
>>               reg = <0 0x00793000 0 0x1000>;
>> @@ -2576,49 +2588,58 @@ gpu: gpu@3d00000 {
>>                 qcom,gmu = <&gmu>;
>>   +            nvmem-cells = <&gpu_speed_bin>;
>> +            nvmem-cell-names = "speed_bin";
>> +
>>               status = "disabled";
>>                 zap-shader {
>>                   memory-region = <&gpu_mem>;
>>               };
>>   -            /* note: downstream checks gpu binning for 670 Mhz */
>>               gpu_opp_table: opp-table {
>>                   compatible = "operating-points-v2";
>>                     opp-670000000 {
>>                       opp-hz = /bits/ 64 <670000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> +                    opp-supported-hw = <0x6>;
> 
> opp-supported-hw = <0xa>; /* 3 & 1 */
> 
>>                   };
>>                     opp-587000000 {
>>                       opp-hz = /bits/ 64 <587000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +                    opp-supported-hw = <0x7>;
> 
> opp-supported-hw = <0xb>; /* 3, 1, 0 */
The values here are correct, however I remapped the bins against
qcom logic.. will fix that in the next rev!

Konrad
> 
> 
>>                   };
>>                     opp-525000000 {
>>                       opp-hz = /bits/ 64 <525000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                     opp-490000000 {
>>                       opp-hz = /bits/ 64 <490000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                     opp-441600000 {
>>                       opp-hz = /bits/ 64 <441600000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                     opp-400000000 {
>>                       opp-hz = /bits/ 64 <400000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                     opp-305000000 {
>>                       opp-hz = /bits/ 64 <305000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>               };
>>           };
> 

Re: [PATCH v2 5/5] arm64: dts: qcom: sm8250: Add GPU speedbin support

[Dmitry Baryshkov]

On 31/03/2023 03:43, Dmitry Baryshkov wrote:
> On 20/01/2023 19:22, Konrad Dybcio wrote:
>> SM8250 has (at least) four GPU speed bins. With the support added on the
>> driver side, wire up bin detection in the DTS to restrict lower-quality
>> SKUs from running at frequencies they were not validated at.
>>
>> Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Sony 
>> Xperia 5 II (speed bin 0x7)
>> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> ---
>>   arch/arm64/boot/dts/qcom/sm8250.dtsi | 23 ++++++++++++++++++++++-
>>   1 file changed, 22 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi 
>> b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> index 059c83003fb6..95f1a6afcd43 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
>> @@ -981,6 +981,18 @@ ipcc: mailbox@408000 {
>>               #mbox-cells = <2>;
>>           };
>> +        qfprom: efuse@784000 {
>> +            compatible = "qcom,sm8250-qfprom", "qcom,qfprom";
>> +            reg = <0 0x00784000 0 0x8ff>;
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            gpu_speed_bin: gpu_speed_bin@19b {
>> +                reg = <0x19b 0x1>;
>> +                bits = <5 3>;
>> +            };
>> +        };
>> +
>>           rng: rng@793000 {
>>               compatible = "qcom,prng-ee";
>>               reg = <0 0x00793000 0 0x1000>;
>> @@ -2576,49 +2588,58 @@ gpu: gpu@3d00000 {
>>               qcom,gmu = <&gmu>;
>> +            nvmem-cells = <&gpu_speed_bin>;
>> +            nvmem-cell-names = "speed_bin";
>> +
>>               status = "disabled";
>>               zap-shader {
>>                   memory-region = <&gpu_mem>;
>>               };
>> -            /* note: downstream checks gpu binning for 670 Mhz */
>>               gpu_opp_table: opp-table {
>>                   compatible = "operating-points-v2";
>>                   opp-670000000 {
>>                       opp-hz = /bits/ 64 <670000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>> +                    opp-supported-hw = <0x6>;
> 
> opp-supported-hw = <0xa>; /* 3 & 1 */

Konrad pointed out that vendor dtsi has pwrlevel #3 for speed-bin=2 and 
vice versa, so the patch is correct (it has mapped speed-bin to hw as 
1:1 instead of weird 2<->3 mapping).

Ideally there should be a comment regarding this.
Nevertheless:

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

> 
>>                   };
>>                   opp-587000000 {
>>                       opp-hz = /bits/ 64 <587000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>> +                    opp-supported-hw = <0x7>;
> 
> opp-supported-hw = <0xb>; /* 3, 1, 0 */
> 
> 
>>                   };
>>                   opp-525000000 {
>>                       opp-hz = /bits/ 64 <525000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                   opp-490000000 {
>>                       opp-hz = /bits/ 64 <490000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                   opp-441600000 {
>>                       opp-hz = /bits/ 64 <441600000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                   opp-400000000 {
>>                       opp-hz = /bits/ 64 <400000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>                   opp-305000000 {
>>                       opp-hz = /bits/ 64 <305000000>;
>>                       opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>> +                    opp-supported-hw = <0xf>;
>>                   };
>>               };
>>           };
> 

-- 
With best wishes
Dmitry