From: Bjorn Helgaas <helgaas@kernel.org>
To: Cai Huoqing <cai.huoqing@linux.dev>
Cc: Sergey.Semin@baikalelectronics.ru,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Vinod Koul" <vkoul@kernel.org>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org,
linux-pci@vger.kernel.org
Subject: Re: [PATCH v3 3/4] dmaengine: dw-edma: Add support for native HDMA
Date: Mon, 13 Feb 2023 14:59:27 -0600 [thread overview]
Message-ID: <20230213205927.GA2930625@bhelgaas> (raw)
In-Reply-To: <20230213132411.65524-4-cai.huoqing@linux.dev>
On Mon, Feb 13, 2023 at 09:24:08PM +0800, Cai Huoqing wrote:
> From: Cai huoqing <cai.huoqing@linux.dev>
>
> Add support for HDMA NATIVE, as long the IP design has set
> the compatible register map parameter-HDMA_NATIVE,
> which allows compatibility for native HDMA register configuration.
Rewrap to fill 75 columns. Also applies below.
> The HDMA Hyper-DMA IP is an enhancement of the eDMA embedded-DMA IP.
> And the native HDMA registers are different from eDMA,
> so this patch add support for HDMA NATIVE mode.
>
> HDMA write and read channels operate independently to maximize
> the performance of the HDMA read and write data transfer over
> the link When you configure the HDMA with multiple read channels,
> then it uses a round robin (RR) arbitration scheme to select
> the next read channel to be serviced.
> The same applies when you have multiple write channels.
Wrap into a single paragraph or add a blank line if you want the last
sentence to be a new paragraph.
> The native HDMA driver also supports a maximum of 16 independent
> channels (8 write + 8 read), which can run simultaneously.
> Both SAR (Source Address Register) and DAR (Destination Address Register)
> are alignmented to byte.
s/alignmented/aligned/
> + u32 watermark_en; /* 0x0030 */
> + u32 control1; /* 0x0034 */
> + u32 func_num; /* 0x0038 */
> + u32 qos; /* 0x003c */
> + u32 reserved; /* 0x0040..0x007c */
> + u32 ch_stat; /* 0x0080 */
Weird indentation of control1, func_num, etc. Is that meaningful or a
mistake?
> + union {
> + u64 reg; /* 0x00a0..0x00a4 */
> + struct {
> + u32 lsb; /* 0x00a0 */
> + u32 msb; /* 0x00a4 */
> + };
> + } msi_abort;
> + u32 msi_msgdata; /* 0x00a8 */
Again here.
Bjorn
next prev parent reply other threads:[~2023-02-13 20:59 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-13 13:24 [PATCH v3 0/4] dmaengine: dw-edma: Add support for native HDMA Cai Huoqing
2023-02-13 13:24 ` [PATCH v3 1/4] dmaengine: dw-edma: Rename dw_edma_core_ops structure to dw_edma_plat_ops Cai Huoqing
2023-02-16 13:41 ` Serge Semin
2023-02-13 13:24 ` [PATCH v3 2/4] dmaengine: dw-edma: Create a new dw_edma_core_ops structure to abstract controller operation Cai Huoqing
2023-02-16 16:17 ` Serge Semin
2023-02-20 6:01 ` Cai Huoqing
2023-02-20 10:52 ` Serge Semin
2023-02-16 16:25 ` Serge Semin
2023-02-13 13:24 ` [PATCH v3 3/4] dmaengine: dw-edma: Add support for native HDMA Cai Huoqing
2023-02-13 15:20 ` kernel test robot
2023-02-14 2:00 ` Cai Huoqing
2023-02-13 20:59 ` Bjorn Helgaas [this message]
2023-02-14 2:03 ` Cai Huoqing
2023-02-16 16:38 ` Serge Semin
2023-02-16 16:41 ` Serge Semin
2023-02-13 13:24 ` [PATCH v3 4/4] dmaengine: dw-edma: Add HDMA DebugFS support Cai Huoqing
2023-02-16 17:10 ` Serge Semin
2023-02-16 2:08 ` [PATCH v3 0/4] dmaengine: dw-edma: Add support for native HDMA Cai Huoqing
2023-02-16 8:56 ` Serge Semin
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