Re: [PATCH v10 2/9] arm64: dts: ti: k3-j721s2-main: Add support for USB

[Nishanth Menon <nm@ti.com>]

On 17:36-20230221, Ravi Gunasekaran wrote:
> From: Aswath Govindraju <a-govindraju@ti.com>
> 
> Add support for single instance of USB 3.0 controller in J721S2 SoC.
> 
> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
> Signed-off-by: Matt Ranostay <mranostay@ti.com>
> Link: https://lore.kernel.org/r/20221122101616.770050-2-mranostay@ti.com

Is the link supposed to signify some reference we need to keep for ever?

> Signed-off-by: Ravi Gunasekaran <r-gunasekaran@ti.com>
> ---
> I had reviewed this patch in the v5 series [1].
> Since I'm taking over upstreaming this series, I removed the self
> Reviewed-by tag.
> 
> Links:
> 
> [1] - https://lore.kernel.org/all/134c28a0-2d49-549c-dc8d-0887d8fd29c3@ti.com/


What changed in this rev of the patch?

> 
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 46 ++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index 8915132efcc1..84e5689fff9f 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -26,6 +26,20 @@
>  		};
>  	};
>  
> +	scm_conf: syscon@104000 {
> +		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
> +		reg = <0x00 0x00104000 0x00 0x18000>;
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x00 0x00 0x00104000 0x18000>;
> +
> +		usb_serdes_mux: mux-controller@0 {
> +			compatible = "mmio-mux";
> +			#mux-control-cells = <1>;
> +			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> +		};
> +	};
> +
>  	gic500: interrupt-controller@1800000 {
>  		compatible = "arm,gic-v3";
>  		#address-cells = <2>;
> @@ -745,6 +759,38 @@
>  		};
>  	};
>  
> +	usbss0: cdns-usb@4104000 {
> +		compatible = "ti,j721e-usb";
> +		reg = <0x00 0x04104000 0x00 0x100>;
> +		clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
> +		clock-names = "ref", "lpm";
> +		assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
> +		assigned-clock-parents = <&k3_clks 360 17>;
> +		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;
> +		ranges;
> +		dma-coherent;
> +
> +		status = "disabled";

Why disabled by default?

> +
> +		usb0: usb@6000000 {
> +			compatible = "cdns,usb3";
> +			reg = <0x00 0x06000000 0x00 0x10000>,
> +			      <0x00 0x06010000 0x00 0x10000>,
> +			      <0x00 0x06020000 0x00 0x10000>;
> +			reg-names = "otg", "xhci", "dev";
> +			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
> +				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "host", "peripheral", "otg";
> +			maximum-speed = "super-speed";
> +			dr_mode = "otg";
> +
> +			status = "disabled";

Why disabled by default?

> +		};
> +	};
> +
>  	main_mcan0: can@2701000 {
>  		compatible = "bosch,m_can";
>  		reg = <0x00 0x02701000 0x00 0x200>,
> -- 
> 2.17.1
>